JPH06204287A - Integrated circuit - Google Patents
Integrated circuitInfo
- Publication number
- JPH06204287A JPH06204287A JP4360771A JP36077192A JPH06204287A JP H06204287 A JPH06204287 A JP H06204287A JP 4360771 A JP4360771 A JP 4360771A JP 36077192 A JP36077192 A JP 36077192A JP H06204287 A JPH06204287 A JP H06204287A
- Authority
- JP
- Japan
- Prior art keywords
- metal conductor
- chip
- conductor wiring
- contact
- film sheet
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
Landscapes
- Wire Bonding (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】この発明は一度に多数の金属導体
配線を配線できる集積回路に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an integrated circuit capable of wiring a large number of metal conductor wirings at one time.
【０００２】[0002]
【従来の技術】図５は従来のワイヤボンド法による集積
回路の分解図、図６は従来のＴＡＢ（テープ自動ボンデ
ィング）法による集積回路の分解図である。図５におい
て１はダイパッド、３はダイパッド１上にろう材２によ
りダイボンディングされるチップ、４はチップ３上に形
成される電極、５は電極４上に接続される金ワイヤ、８
は金ワイヤ５に接続される外部リード線である。2. Description of the Related Art FIG. 5 is an exploded view of an integrated circuit by a conventional wire bonding method, and FIG. 6 is an exploded view of an integrated circuit by a conventional TAB (tape automatic bonding) method. In FIG. 5, 1 is a die pad, 3 is a chip that is die-bonded on the die pad 1 with a brazing material 2, 4 is an electrode formed on the chip 3, 5 is a gold wire connected to the electrode 4, 8
Is an external lead wire connected to the gold wire 5.
【０００３】次に図５の動作について説明する。チップ
３はダイパッド１上にろう材２によりダイボンディング
され固定される。次にチップ３上に形成される電極４と
外部リード線８が、金ワイヤ５により１本ずつ熱圧着法
等により接続される。Next, the operation of FIG. 5 will be described. The chip 3 is die-bonded and fixed on the die pad 1 by the brazing material 2. Next, the electrodes 4 formed on the chip 3 and the external lead wires 8 are connected one by one by the gold wire 5 by a thermocompression bonding method or the like.
【０００４】次に図６のＴＡＢ（テープ自動ボンディン
グ）法について説明する。図６において１はダイパッ
ド、３はダイパッド１上にろう材２によりダイボンディ
ングされるチップ、６はチップ３上に形成されるバン
プ、７はバンプ６上に接続される内部リード線、８は内
部リード線７に接続される外部リード線である。Next, the TAB (tape automatic bonding) method of FIG. 6 will be described. In FIG. 6, 1 is a die pad, 3 is a chip that is die-bonded on the die pad 1 with a brazing material 2, 6 is a bump formed on the chip 3, 7 is an internal lead wire connected to the bump 6, and 8 is an internal It is an external lead wire connected to the lead wire 7.
【０００５】次に図６の動作について説明する。チップ
３はダイパッド１上にろう材２によりダイボンディング
され固定される。次にチップ３上に形成されるバンプ６
と外部リード線８が、内部リード線７により熱圧着法や
溶接法により接続される。Next, the operation of FIG. 6 will be described. The chip 3 is die-bonded and fixed on the die pad 1 by the brazing material 2. Next, the bumps 6 formed on the chip 3
The external lead wire 8 is connected to the external lead wire 8 by a thermocompression bonding method or a welding method.
【０００６】[0006]
【発明が解決しようとする課題】従来の集積回路は以上
のように構成されていたので、ワイヤボンド法では多数
の金ワイヤを１本ずつ接続することが必要であり接続に
時間を要し、またボンディングの位置精度が劣るという
問題点があった。Since the conventional integrated circuit is constructed as described above, it is necessary to connect a large number of gold wires one by one in the wire bonding method, which requires time for connection. Further, there is a problem that the positioning accuracy of bonding is poor.
【０００７】またＴＡＢ法では、チップの上面電極とし
てバンプを形成する必要があるために、バンプのないチ
ップは内部リード線の接続が不可能になるという問題点
があった。In the TAB method, since it is necessary to form a bump as an upper surface electrode of the chip, there is a problem that a chip without a bump cannot be connected to an internal lead wire.
【０００８】さらにワイヤボンド法およびＴＡＢ法とも
に、金ワイヤまたは内部リード線が曲がり、金ワイヤま
たは内部リード線同士、あるいはチップと接触し不良と
なるという問題点があった。Further, both the wire bond method and the TAB method have a problem that the gold wire or the internal lead wire is bent, and the gold wire or the internal lead wire is in contact with each other or with the chip, resulting in a defect.
【０００９】この発明は上記のような問題点を解消する
ためになされたもので、精度よく多数の金属導体配線を
一度に接続することができるとともに、チップ上面にバ
ンプを形成する必要がなく、配線同士または配線とチッ
プとの接触不良を防止できる集積回路を得ることを目的
とする。The present invention has been made in order to solve the above-mentioned problems, and it is possible to accurately connect a large number of metal conductor wirings at one time, and it is not necessary to form bumps on the chip upper surface. An object of the present invention is to obtain an integrated circuit capable of preventing a contact failure between wirings or between a wiring and a chip.
【００１０】[0010]
【課題を解決するための手段】請求項１の発明に係る集
積回路は、チップの表面電極と外部リード線の間を、上
記電極と接続する１端に圧着部材を持つ、フィルムシー
トの平面上に密着形成した複数の金属導体配線で接続し
たものである。According to a first aspect of the present invention, there is provided an integrated circuit in which a surface of a chip and an external lead wire have a crimping member at one end for connecting the electrode on the plane of a film sheet. Are connected by a plurality of metal conductor wirings formed in close contact with each other.
【００１１】請求項２の発明に係る集積回路は、チップ
の表面電極と外部リード線の間を、上記電極と接続する
１端に圧着部材を持つ、フィルムシートの平面上に密着
形成された複数の金属導体配線で接続し、保護フィルム
シートを上記金属導体配線表面に密着させたものであ
る。According to a second aspect of the present invention, there is provided an integrated circuit in which a plurality of electrodes are formed in close contact with each other on a flat surface of a film sheet having a pressure-bonding member at one end connecting the surface electrode of the chip and the external lead wire to the electrode. The metal conductor wiring is used for connection, and the protective film sheet is brought into close contact with the surface of the metal conductor wiring.
【００１２】[0012]
【作用】請求項１の発明における集積回路は、チップ上
に形成される電極とフィルムシートの平面上に密着形成
された金属導体配線の１端に形成される圧着部材が複数
同時に熱圧着法や超音波熱圧着法により接続される。According to the integrated circuit of the invention of claim 1, a plurality of pressure-bonding members formed at one end of the electrodes formed on the chip and one end of the metal conductor wiring closely formed on the flat surface of the film sheet are subjected to the thermocompression bonding method and It is connected by the ultrasonic thermocompression bonding method.
【００１３】請求項２の発明における保護フィルムシー
トは金属導体配線とチップの接触を防止するためのスペ
ーサの役を担う。The protective film sheet according to the second aspect of the present invention functions as a spacer for preventing contact between the metal conductor wiring and the chip.
【００１４】[0014]
【実施例】実施例１．以下この発明の第１の実施例を図
について説明する。図１はこの発明の実施例１による集
積回路の断面側面図、図３はこの発明の実施例１による
金属導体配線を形成したフィルムシートの平面図、図４
はこの発明の実施例１による金属導体配線を形成したフ
ィルムシートの断面図である。EXAMPLES Example 1. A first embodiment of the present invention will be described below with reference to the drawings. 1 is a sectional side view of an integrated circuit according to a first embodiment of the present invention, FIG. 3 is a plan view of a film sheet on which metal conductor wiring is formed according to the first embodiment of the present invention, and FIG.
FIG. 3 is a cross-sectional view of a film sheet on which a metal conductor wiring is formed according to Example 1 of the present invention.
【００１５】図において、１はダイパッド、３はダイパ
ッド１上にろう材２によりダイボンディングされるチッ
プ、４はチップ３上に形成される電極、１１はフィルム
シート１０上に複数形成される金属導体配線、１２は電
極４に接続される、金属導体配線１１の１端に形成され
る圧着部材、１３はチップ３と金属導体配線１１の間に
挿入され接触を防止する保護フィルムシート、８は金属
導体配線１１の他端に接続される外部リード線、１０は
以上のものを外装封止するモールド樹脂である。In the figure, 1 is a die pad, 3 is a chip which is die-bonded on the die pad 1 by a brazing material 2, 4 is an electrode formed on the chip 3, and 11 is a plurality of metal conductors formed on the film sheet 10. Wiring, 12 is a crimping member formed at one end of the metal conductor wiring 11 connected to the electrode 4, 13 is a protective film sheet inserted between the chip 3 and the metal conductor wiring 11 to prevent contact, 8 is a metal External lead wires 10 connected to the other end of the conductor wiring 11 are mold resins for encapsulating the above.
【００１６】次に動作について説明する。チップ３はダ
イパッド１上にろう材２によりダイボンディングされ固
定される。次にチップ３上に形成される電極４と金属導
体配線１１の１端に形成される圧着部材１２が複数同時
に熱圧着法や超音波熱圧着法により接続され、次に金属
導体配線１１の他端と外部リード線８が接続され、最後
に外部リード線８を除く以上の物がモールド樹脂１０で
外装封止される。保護フィルムシート１３はチップ３と
金属導体配線１１の間に挿入され接触を防止している。
また金属導体配線１１はフィルムシート１０上に密着形
成されているので配線同士の接触不良は防止されてい
る。また熱圧着法や超音波熱圧着法による接続に必要な
圧着部材１２は金属導体配線１１の１端に形成されてい
るのでバンプをチップ３上に形成する必要がなくなって
いる。Next, the operation will be described. The chip 3 is die-bonded and fixed on the die pad 1 by the brazing material 2. Next, a plurality of electrodes 4 formed on the chip 3 and a crimping member 12 formed at one end of the metal conductor wiring 11 are simultaneously connected by thermocompression bonding or ultrasonic thermocompression bonding. The end and the external lead wire 8 are connected, and finally the above-mentioned objects except the external lead wire 8 are externally sealed with the mold resin 10. The protective film sheet 13 is inserted between the chip 3 and the metal conductor wiring 11 to prevent contact.
Further, since the metal conductor wiring 11 is formed in close contact with the film sheet 10, contact failure between the wirings is prevented. Further, since the crimping member 12 required for connection by the thermocompression bonding method or the ultrasonic thermocompression bonding method is formed at one end of the metal conductor wiring 11, it is not necessary to form bumps on the chip 3.
【００１７】実施例２．次にこの発明の第２の実施例を
図について説明する。図２はこの発明の実施例２による
集積回路の断面側面図である。図において１〜１３は実
施例１と同様である。Example 2. Next, a second embodiment of the present invention will be described with reference to the drawings. 2 is a sectional side view of an integrated circuit according to a second embodiment of the present invention. In the figure, 1 to 13 are the same as in the first embodiment.
【００１８】次に動作について説明する。実施例１と比
較してダイパッド１の沈みが大きく、チップ３の表面と
外部リード線８の高さが同じなので、電極４と金属導体
配線１１の１端に形成される圧着部材１２、および金属
導体配線１１の他端と外部リード線８が同時にボンディ
ングされる。Next, the operation will be described. Since the sinking of the die pad 1 is larger than that of the first embodiment and the height of the surface of the chip 3 and the height of the external lead wire 8 are the same, the pressure bonding member 12 formed at one end of the electrode 4 and the metal conductor wiring 11, and the metal. The other end of the conductor wiring 11 and the external lead wire 8 are simultaneously bonded.
【００１９】[0019]
【発明の効果】以上のように、請求項１の発明によれば
集積回路を、１端に圧着部材を持つ、フィルムシートの
平面上に密着形成した複数の金属導体配線で、チップの
表面電極と外部リード線の間を接続するように構成した
ので、精度よく多数の金属導体配線を一度に接続するこ
とができるとともに、チップ上面にバンプを形成する必
要がなく、配線同士の接触不良を防止できる集積回路が
得られるという効果がある。As described above, according to the first aspect of the present invention, the integrated circuit has a plurality of metal conductor wirings which are formed in close contact with each other on the flat surface of the film sheet and which have a pressure-bonding member at one end thereof. Since it is configured to connect between the lead wire and the external lead wire, it is possible to accurately connect many metal conductor wirings at one time, and it is not necessary to form bumps on the chip top surface, preventing contact failure between wirings. There is an effect that a possible integrated circuit can be obtained.
【００２０】請求項２の発明によれば、請求項１の発明
に加えて、保護フィルムシートをチップと金属導体配線
の間に挿入するように構成したので、チップと配線との
接触不良を防止できる集積回路が得られるという効果が
ある。According to the invention of claim 2, in addition to the invention of claim 1, since the protective film sheet is inserted between the chip and the metal conductor wiring, the contact failure between the chip and the wiring is prevented. There is an effect that a possible integrated circuit can be obtained.
【図１】請求項２の発明の実施例１による集積回路の断
面側面図である。1 is a cross-sectional side view of an integrated circuit according to a first embodiment of the invention of claim 2;
【図２】請求項２の発明の実施例２による集積回路の断
面側面図である。FIG. 2 is a sectional side view of an integrated circuit according to a second embodiment of the invention of claim 2;
【図３】請求項２の発明の実施例１、２による金属導体
配線を形成したフィルムシートの平面図である。FIG. 3 is a plan view of a film sheet on which metal conductor wirings according to Examples 1 and 2 of the invention of claim 2 are formed.
【図４】請求項２の発明の実施例１、２による金属導体
配線を形成したフィルムシートの断面図である。FIG. 4 is a cross-sectional view of a film sheet on which metal conductor wiring according to Examples 1 and 2 of the invention of claim 2 is formed.
【図５】従来技術のワイヤボンド法による集積回路の断
面側面図である。FIG. 5 is a cross-sectional side view of an integrated circuit according to a conventional wire bonding method.
【図６】従来技術のＴＡＢ法による集積回路の断面側面
図である。FIG. 6 is a cross-sectional side view of a conventional TAB integrated circuit.
３ チップ ４ 電極 ８ 外部リード線 １０ フィルムシート １１ 金属導体配線 １２ 圧着部材 １３ 保護フィルムシート 3 chip 4 electrode 8 external lead wire 10 film sheet 11 metal conductor wiring 12 crimping member 13 protective film sheet
Claims (2)
と、フィルムシートの平面上に密着形成され、一端が上
記電極と接続する複数の金属導体配線と、上記金属導体
配線の一端に形成され、その金属導体配線の一端と上記
電極を圧着して固定する圧着部材と、上記金属導体配線
の他端に接続される外部リード線とを備えた集積回路。1. A plurality of electrodes formed on the surface of a chip, a plurality of metal conductor wirings formed in close contact with each other on the plane of a film sheet, one end of which is connected to the electrodes, and a plurality of metal conductor wirings formed at one end of the metal conductor wirings. An integrated circuit comprising a crimping member for crimping and fixing one end of the metal conductor wiring and the electrode, and an external lead wire connected to the other end of the metal conductor wiring.
と、フィルムシートの平面上に密着形成され、一端が上
記電極と接続する複数の金属導体配線と、上記金属導体
配線の一端に形成され、その金属導体配線の一端と上記
電極を圧着して固定する圧着部材と、上記金属導体配線
の両端の接続部分以外の部分に密着させた保護フィルム
シートと、上記金属導体配線の他端に接続される外部リ
ード線とを備えた集積回路。2. A plurality of electrodes formed on the surface of the chip, a plurality of metal conductor wirings formed in close contact with each other on the plane of the film sheet, one end of which is connected to the electrodes, and a plurality of metal conductor wirings formed at one end of the metal conductor wirings. , A crimping member for crimping and fixing one end of the metal conductor wiring and the electrode, a protective film sheet adhered to a portion other than the connecting portions at both ends of the metal conductor wiring, and connected to the other end of the metal conductor wiring Integrated circuit with external leads.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4360771A JPH06204287A (en) | 1992-12-29 | 1992-12-29 | Integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4360771A JPH06204287A (en) | 1992-12-29 | 1992-12-29 | Integrated circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH06204287A true JPH06204287A (en) | 1994-07-22 |
Family
ID=18470852
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4360771A Pending JPH06204287A (en) | 1992-12-29 | 1992-12-29 | Integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH06204287A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006344652A (en) * | 2005-06-07 | 2006-12-21 | Toshiba Components Co Ltd | Semiconductor device and method of mounting semiconductor component |
-
1992
- 1992-12-29 JP JP4360771A patent/JPH06204287A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006344652A (en) * | 2005-06-07 | 2006-12-21 | Toshiba Components Co Ltd | Semiconductor device and method of mounting semiconductor component |
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