JPH03265148A - Semiconductor device and manufacture thereof - Google Patents

Semiconductor device and manufacture thereof

Info

Publication number
JPH03265148A
JPH03265148A JP2064872A JP6487290A JPH03265148A JP H03265148 A JPH03265148 A JP H03265148A JP 2064872 A JP2064872 A JP 2064872A JP 6487290 A JP6487290 A JP 6487290A JP H03265148 A JPH03265148 A JP H03265148A
Authority
JP
Japan
Prior art keywords
substrate
electrode
semiconductor chip
chip
region
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2064872A
Other languages
Japanese (ja)
Inventor
Nobuyoshi Isomura
磯村　信芳
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu VLSI Ltd
Fujitsu Ltd
Original Assignee
Fujitsu VLSI Ltd
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu VLSI Ltd, Fujitsu Ltd filed Critical Fujitsu VLSI Ltd
Priority to JP2064872A priority Critical patent/JPH03265148A/en
Publication of JPH03265148A publication Critical patent/JPH03265148A/en
Pending legal-status Critical Current

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE:To avoid a wiring from coming into contact with a chip mounting region even if a stress is applied from the upper direction by a method wherein an insulating film is provided on a region between a lead frame with a semiconductor chip mounted thereon and metal leads and the wiring, such as a copper wire, a gold wire or the like, is formed on this film while being given a proper looseness. CONSTITUTION:When an extraction electrode 12a on a semiconductor chip 12 mounted on a conductive substrate 11 is connected with a wiring electrode 11a isolated from the substrate 11 by a conductor 13, an insulative and filmlike substrate 14 is provided on a region between the electrode 11a and the substrate 11 and the conductor 13 is wired with a proper looseness so that it is positioned on this substrate 14. For that purpose, an opening is formed in the substrate 11, the substrate 11 is divided into an electrode formation region Al for forming an electrode 11a, and a chip mountable region A2 for mounting the chip 12, and the insulative substrate 14 is made to position on a region between the region A1 and the region A2. According to the method, at the time of treatment of a package subsequent to a wire bonding process, the substrate 14 works as a stopper and there is no possibility that the conductor 13 comes into contact electrically with the substrate 11.

Description

【発明の詳細な説明】 〔目　次〕 ・概要 ・産業上の利用分野 ・従来の技術（第５図） ・発明が解決しようとする課題（第６図）・課題を解決
するための手段（第１図）・作用 ・実施例 （１）第１の実施例の説明（第２．第３図）（ｉｉ）第
２の実施例の説明（第４図）・発明の効果 〔概　要〕 半導体装置、特にリードフレームに搭載された半導体チ
ップと金属リードとを配線するワイヤーボンディング技
術に関し、 該リードフレームに設計サイズよりも小さな半導体チッ
プを取り付けた場合であっても、金属線間の短絡等を阻
止し、総合的な開発工程数の低減化及び生産コストの低
廉化を図ることを目的とし、その装置は、導電性の基板
に搭載された半導体チップの引出電極と前記導電性の基
板から分離された配線電極とが導電体により接続された
半導体装置であって、前記導電性の基板から配置ｉｌＡ
！極に至る領域に絶縁性の基板が設けられ、前記導電体
が、予め、絶縁性の基板上で適当な強度を持って配線さ
れていることを含み構成する。[Detailed Description of the Invention] [Table of Contents] - Overview - Field of industrial application - Conventional technology (Fig. 5) - Problem to be solved by the invention (Fig. 6) - Means for solving the problem ( Figure 1), Effects, Examples (1) Explanation of the first embodiment (Figures 2 and 3) (ii) Explanation of the second embodiment (Figure 4), Effects of the invention [Summary] Regarding wire bonding technology for wiring semiconductor devices, especially semiconductor chips mounted on lead frames and metal leads, even if a semiconductor chip smaller than the designed size is attached to the lead frame, short circuits between metal wires etc. may occur. The purpose of this device is to reduce the overall number of development steps and reduce production costs by preventing A semiconductor device in which separated wiring electrodes are connected to each other by a conductor, the semiconductor device being arranged from the conductive substrate.
! An insulating substrate is provided in a region reaching the pole, and the conductor is previously wired with appropriate strength on the insulating substrate.

Ｃ産業上の利用分野〕 本発明は、半導体装置及びその製造方法に関するもので
あり、さらに詳しく言えばパッケージ処理等に移行する
前工程における半導体チップと金属リードとを配線する
ワイヤーボンディング技術に関するものである。C. Industrial Application Field] The present invention relates to a semiconductor device and a method for manufacturing the same, and more specifically, it relates to a wire bonding technique for wiring a semiconductor chip and metal leads in a pre-process before proceeding to packaging processing, etc. be.

近年、ユーザの使用態様から特定用途の半導体集積回路
装置（以下単にＩＣという）等の製造要求があり、該Ｉ
Ｃの多品種化及び多様化の傾向がある。In recent years, there has been a demand for manufacturing semiconductor integrated circuit devices (hereinafter simply referred to as ICs) for specific applications due to user usage patterns.
There is a tendency for C to become more diverse and diversified.

ところで、集積回路等を組み込んだ半導体チップをパン
ケージングする前工程において、該半導体チップがリー
ドフレームに搭載され、金属リードと該チップとが銅線
等により配線（ワイヤーボンディング配線法）されてい
る。By the way, in a pre-pancaging process for a semiconductor chip incorporating an integrated circuit or the like, the semiconductor chip is mounted on a lead frame, and metal leads and the chip are wired with copper wire or the like (wire bonding wiring method).

これによれば、既存のリードフレームにチップサイズの
小さな半導体チップを取り付けた場合であっても、金属
線間の短絡等を阻止し、総合的な開発工程数の低減化及
び生産コストの低廉化を図ることができる装置とその方
法が望まれている。According to this, even when a small semiconductor chip is attached to an existing lead frame, short circuits between metal wires can be prevented, reducing the overall number of development steps and lowering production costs. There is a need for a device and method that can achieve this.

〔従来の技術〕[Conventional technology]

第４，５図は、従来例に係る説明図である。 4 and 5 are explanatory diagrams relating to the conventional example.

第４図は、従来例の半導体装置に係る構成図を示してい
る。FIG. 4 shows a configuration diagram of a conventional semiconductor device.

図において、パッケージ処理に移行する前の半導体装置
は、リードフレーム１のステージ部にエポキシ樹脂等に
より接着された半導体チップ２と、リードフレーム１か
ら分離された金属リード１ａから戒る。また、金属リー
ド１ａと半導体チップ２のパッド電極２ａとは銅線３等
により接続されている。In the figure, a semiconductor device before proceeding to packaging processing is separated from a semiconductor chip 2 bonded to a stage portion of a lead frame 1 with epoxy resin or the like, and a metal lead 1a separated from the lead frame 1. Further, the metal lead 1a and the pad electrode 2a of the semiconductor chip 2 are connected by a copper wire 3 or the like.

また、リードフレーム１はパッケージ処理後に外部端子
となる金属リード１ａを形成する電極形成領域ＡＩと半
導体チップ２を固定するチップ搭載可能領域Ａ２とが一
つの導電性の基板を打ち抜くことによって形成されてい
る。In addition, the lead frame 1 is formed by punching out a single conductive substrate, in which an electrode forming area AI for forming metal leads 1a that will become external terminals after packaging processing and a chip mounting area A2 for fixing the semiconductor chip 2 are formed. There is.

さらに、金属リード１ａとバンド電極２ａとの間の銅線
３は、ワイヤーボンディング装置の自動配線具のストロ
ークの移動軌跡等により余裕を持って配線処理がされて
いる。Further, the copper wire 3 between the metal lead 1a and the band electrode 2a is wired with a margin depending on the movement locus of the stroke of the automatic wiring tool of the wire bonding device.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

ところで、従来例によれば半導体回路の高密度化、高集
積化によりチップサイズの縮小化が図られている。また
、ユーザの使用態様から特定用途のＩＣの製造要求があ
り、該ＩＣの多品種化及び多様化の傾向がある。By the way, according to conventional examples, the chip size has been reduced by increasing the density and integration of semiconductor circuits. In addition, there is a demand for manufacturing ICs for specific applications due to user usage patterns, and there is a trend toward multi-product and diversification of such ICs.

このため、チップサイズの変更により、リードフレーム
１やパッケージサイズの設計変更をしなければならず、
その種類の増加が余ｌＩ＆無くされている。Therefore, due to a change in chip size, it is necessary to change the design of the lead frame 1 and package size.
The number of types is increasing and is being eliminated.

そこで、既存のリードフレーム１のチップ搭載可能領域
Ａ２に設計サイズよりも小さい半導体チップを取り付け
ることによって製造コストの低減化が図られている。Therefore, manufacturing costs are reduced by attaching a semiconductor chip smaller than the designed size to the chip mounting area A2 of the existing lead frame 1.

しかし、第５図（ａ）、　　（ｂ）に示すような問題点
を生ずることがある。However, problems as shown in FIGS. 5(a) and 5(b) may occur.

同図（ａ）において、バンド電極２ａと金属リード１ａ
との径間が長くなることから銅線３がチップ搭載可能領
域Ａ２に触れることがある。In the same figure (a), a band electrode 2a and a metal lead 1a
Since the distance between the copper wire 3 and the copper wire 3 becomes long, the copper wire 3 may touch the chip mounting area A2.

これは、樹脂封止型のＩＣに先住する恐れがあり、ワイ
ヤーボンディング工程後において、特にバフケージ処理
の際に上方向からの樹脂の流入圧力ＰＩにより生ずるも
のと考えられる。This is likely to occur in resin-sealed ICs, and is thought to be caused by the resin inflow pressure PI from above after the wire bonding process, especially during buff cage processing.

これにより、銅線３がステージ部に短絡をして当該半導
体装置の誤動作の原因を招くという第１の問題がある。This causes the first problem that the copper wire 3 causes a short circuit to the stage section, causing malfunction of the semiconductor device.

また、同図（ｂ）において、バッド電極２ａと金属リー
ド１ａとの径間が長くなることで隣接する銅線３同士が
何らかの原因で接触することがある。Further, in FIG. 2B, as the distance between the bad electrode 2a and the metal lead 1a becomes longer, adjacent copper wires 3 may come into contact with each other for some reason.

これは、気密封止型のＩＣに発生する恐れがあり、製品
化されたＩＣの使用態様により、特に振動等の激しい条
件下において横方向Ｐ２からの応力により生ずるものと
考えられる。This is likely to occur in hermetically sealed ICs, and is thought to be caused by stress from the lateral direction P2, particularly under severe conditions such as vibrations, depending on the usage of the commercialized IC.

これにより、銅ｌ１１３間が短絡をして当該半導体装置
の誤動作の原因を招くという第２の問題がある。This causes a second problem in that a short circuit occurs between the copper parts 113, causing a malfunction of the semiconductor device.

本発明は、かかる従来例の問題点に鑑み創作されたもの
であり、リードフレームに設計サイズよりも小さな半導
体チップを取り付けた場合であっても、金属線間の短絡
等を阻止し、総合的な開発工程数の低減化及び生産コス
トの低廉化を図ることが可能となる半導体装置及びその
製造方法の提供を目的とする。The present invention was created in view of the problems of the conventional example, and even when a semiconductor chip smaller than the design size is attached to a lead frame, it prevents short circuits between metal wires and provides a comprehensive An object of the present invention is to provide a semiconductor device and a method for manufacturing the same, which make it possible to reduce the number of development steps and reduce production costs.

〔課題を解決するための手段〕[Means to solve the problem]

第１図は、本発明に係る半導体装置の原理図である。 FIG. 1 is a principle diagram of a semiconductor device according to the present invention.

その装置は、導電性の基板１１に搭載された半導体チッ
プ１２の引出電極１２ａと前記導電性の基板１１から分
離された配ｇＡｔ極１１ａとが導電体１３により接続さ
れた半導体装置であって、前記導電性の基板１１から配
線電極１１ａに至る領域に絶縁性の基板１４が設けられ
、前記導電体１３が絶縁性の基板１４上で適当な強度を
持って配線されていることを特徴とし、 その製造方法は、導電性の基板１１を開口して配線電極
１１ａとなる電極形成領域Ａ１と半導体チップ１２を搭
載するチップ搭載可能領域Ａ２とを形成する工程と、前
記チップ搭載可能領域Ａ２に半導体チップ１２を搭載す
る工程と、前記半導体チップ１２を搭載した領域以外の
チップ搭載可能領域Ａ２から電極形成領域Ａ１に至る領
域に絶縁性の基板１４を形成する工程と、前記電極形成
領域ＡＩの配線電極１１ａと前記半導体チップの引出電
極１２ａとを導電体１３により弛ませて配線する工程と
を有することを特徴とし、上記目的を達成する。The device is a semiconductor device in which a lead electrode 12a of a semiconductor chip 12 mounted on a conductive substrate 11 and a distributed At electrode 11a separated from the conductive substrate 11 are connected by a conductor 13, An insulating substrate 14 is provided in a region from the conductive substrate 11 to the wiring electrode 11a, and the conductor 13 is wired with appropriate strength on the insulating substrate 14, The manufacturing method includes the steps of opening a conductive substrate 11 to form an electrode forming area A1 that will become the wiring electrode 11a and a chip mounting area A2 for mounting a semiconductor chip 12, and forming a semiconductor chip in the chip mounting area A2. a step of mounting the chip 12; a step of forming an insulating substrate 14 in an area other than the area where the semiconductor chip 12 is mounted from the chip mountable area A2 to the electrode formation area A1; and wiring of the electrode formation area AI. The above object is achieved by including a step of wiring the electrode 11a and the lead electrode 12a of the semiconductor chip by loosening the conductor 13.

〔作　用〕[For production]

本発明の装置によれば、半導体チップ１２を搭載した導
電性の基板１１から配線電極１１ａに至る領域に絶縁性
の基板１４が設けられている。According to the device of the present invention, the insulating substrate 14 is provided in the region extending from the conductive substrate 11 on which the semiconductor chip 12 is mounted to the wiring electrode 11a.

このため、ワイヤーボンディング工程後におけるパッケ
ージ処理の際に、例えば、上方向からの樹脂の流入圧力
が生じた場合であっても、絶縁性の基板１４がストッパ
ーとなって、導電体１３がチップ搭載可能領域Ａ２のＨ
Ｌｔ性の基板１１に電気的に接触することがない。Therefore, even if, for example, inflow pressure of resin from above occurs during package processing after the wire bonding process, the insulating substrate 14 acts as a stopper, and the conductor 13 is prevented from mounting the chip. H in possible area A2
There is no electrical contact with the Lt-based substrate 11.

また、導電体１３が絶縁性の基板１４上で適当な強度を
持って配線されている。Further, the conductor 13 is wired with appropriate strength on the insulating substrate 14.

このため、製品化されたＩＣの使用態様により、該ＩＣ
が振動等を受けた際に、例えば、横方向からの応力が生
した場合であっても、導電体１３の横方向の自由度が制
限されることにより、隣接する導電体１３同士の接触を
極力抑制することができる。For this reason, depending on the usage of the commercialized IC,
When the conductors 13 are subjected to vibrations, for example, even if stress is generated in the lateral direction, the degree of freedom of the conductors 13 in the lateral direction is limited, so that adjacent conductors 13 cannot contact each other. It can be suppressed as much as possible.

これにより、当該半導体装置の信頼度の向上を図ること
が可能となる。This makes it possible to improve the reliability of the semiconductor device.

また、本発明の方法によれば、半導体チップ１２を搭載
した領域以外のチップ搭載可能領域Ａ２から電極形成領
域ＡＩに至る領域に絶縁性の基板１４を形成している。Furthermore, according to the method of the present invention, the insulating substrate 14 is formed in an area other than the area where the semiconductor chip 12 is mounted, ranging from the chip mounting area A2 to the electrode forming area AI.

このため、特定用途のＩＣの製造要求があった場合、導
電性の基板（リードフレーム）１１やパッケージサイズ
の設計変更をすることなく、既存のリードフレームを使
用して、そのチップ搭載可能領域Ａ２に設計サイズより
も小さい半導体チップを取り付け、信頼性の良い半導体
装置を製造することが可能となる。Therefore, when there is a request to manufacture an IC for a specific purpose, the existing lead frame can be used without changing the design of the conductive substrate (lead frame) 11 or the package size, and the chip can be mounted in the area A2. It becomes possible to manufacture highly reliable semiconductor devices by attaching semiconductor chips that are smaller than the designed size to the device.

これにより、総合的な開発工程数の低減化及び生産コス
トの低廉化を図ることが可能となる。This makes it possible to reduce the overall number of development steps and reduce production costs.

〔実施例〕〔Example〕

次に図を参照しながら本発明の実施例について説明をす
る。Next, embodiments of the present invention will be described with reference to the drawings.

第２〜第４図は、本発明の実施例に係る半導体装置及び
その製造方法を説明する図である。2 to 4 are diagrams illustrating a semiconductor device and a method of manufacturing the same according to an embodiment of the present invention.

（ｉ）第１の実施例の説明 第２図（ａ）〜（ｃ）は、本発明の第１の実施例に係る
半導体装置の構成国を示している。(i) Description of the First Embodiment FIGS. 2(a) to 2(c) show the constituent countries of the semiconductor device according to the first embodiment of the present invention.

同図（ａ）は、パンケージ処理に移行する前の半導体装
置を示しており、同図（ｂ）はその上面の部分拡大図、
同図（Ｃ）はそのＸ−Ｙ矢視断面図を示している。Figure (a) shows the semiconductor device before moving to pancage processing, and Figure (b) is a partially enlarged view of the top surface.
The same figure (C) has shown the XY arrow sectional view.

同図（ａ）において、２１はｓＷ性の基板１１の一実施
例となるリードフレームであり、配線電極１１ａの一実
施例となる金属リード２１ａ（１を極形成領域Ａ１）と
半導体チップ２２を搭載したステージ部２１ｂ（チップ
搭載可能領域Ａ２）から成る。In the same figure (a), 21 is a lead frame which is an example of the SW substrate 11, and a semiconductor chip 22 is connected to a metal lead 21a (1 is an electrode forming area A1) which is an example of the wiring electrode 11a. It consists of a mounted stage portion 21b (chip mountable area A2).

金属リード２１ａは、パッケージ処理工程後において、
リードフレーム２１から切り離され、外部入出力ビンを
構成する。また、リードフレーム２Ｉは、鉄・ニッケル
合金や銅合金等から威る。After the packaging process, the metal lead 21a is
It is separated from the lead frame 21 and constitutes an external input/output bin. Further, the lead frame 2I is made of iron-nickel alloy, copper alloy, etc.

２２はリードフレーム２１に搭載された半導体チップで
あり、半導体集積回路を組み込んだＩＣチップ等である
。このＩＣチップはユーザの使用態様から多品種化及び
多様化の傾向にある。A semiconductor chip 22 is mounted on the lead frame 21, and is an IC chip or the like incorporating a semiconductor integrated circuit. These IC chips tend to be diversified and diversified due to the usage patterns of users.

また、リードフレーム２１と半導体チップ２２とは、エ
ポキシ樹脂材にＡｇ（銀）又はＡｕ（金）等の粉末を含
有した接着剤２５により接着されている。Further, the lead frame 21 and the semiconductor chip 22 are bonded together using an adhesive 25 containing powder such as Ag (silver) or Au (gold) in an epoxy resin material.

また、同図（ｂ）において、２３は導電体１３の一実施
例となる銅線や金線等であり、半導体チップ２工のパッ
ｌ″電極２２ａとリードフレーム２１から分離された金
属リード２１ａとを電気的に接続するものである。Further, in FIG. 2B, reference numeral 23 is a copper wire, gold wire, etc., which is an example of the conductor 13, and a metal lead 21a separated from the pad 1'' electrode 22a of the semiconductor chip 2 and the lead frame 21. It electrically connects the

２４は絶縁性の基板１４の一実施例となる絶縁フィルム
であり、リードフレーム２】から金属リード２１ａに至
る領域に設けられている。絶縁フィルム２４は、プラス
チインク薄膜等が用いられ、ワイヤーボンディング工程
前に挿入されたものである。An insulating film 24 is an example of the insulating substrate 14, and is provided in an area extending from the lead frame 2 to the metal lead 21a. The insulating film 24 is made of plastin ink thin film or the like, and is inserted before the wire bonding process.

さらに、同図（ｃ）において、ｖ４線２３は絶縁フィル
ム２４上で適当な強度を持って配線されている０例えば
、絶縁フィルム２４面に銅線２３が２点ないし３点に渡
って接触している。なお、気密封止型のＩＣについては
、予め、絶縁フィルム２４面と綱ｖＡ２３との接触点が
接着剤により固定されている。Furthermore, in the same figure (c), the V4 wire 23 is wired with appropriate strength on the insulating film 24. For example, the copper wire 23 is in contact with the surface of the insulating film 24 at two or three points. ing. Note that for the hermetically sealed IC, the contact point between the insulating film 24 surface and the rope vA23 is fixed in advance with an adhesive.

このようにして、本発明の第１の装置によれば半導体チ
ップ２２を搭載したり一ドフレーム２１から金属リード
２１ａに至る領域に絶縁フィルム２４が設けられている
。In this way, according to the first device of the present invention, the insulating film 24 is provided in the area where the semiconductor chip 22 is mounted and from the lead frame 21 to the metal lead 21a.

このため、ワイヤーボンディング工程後におけるパッケ
ージ処理の際に、例えば、上方向からの樹脂の流入圧力
が生じた場合であっても、絶縁フィルム２４がストツバ
−となって、銅線２３が導電性を有するステージ部２１
　ｂ　ｌこ接触することがない また、銅線２３が絶縁フィルム２４上で適当な強度を持
って配線されている。Therefore, even if, for example, inflow pressure of resin from above occurs during package processing after the wire bonding process, the insulating film 24 acts as a stopper and the copper wire 23 becomes conductive. Stage section 21 having
In addition, the copper wire 23 is wired with appropriate strength on the insulating film 24 so that the wires do not come into contact with each other.

このため、特に気密封止型のＩＣにおいて、製品化され
たｒＣの使用態様により、例えば、該ＩＣが振動等を受
けた際に、例えば、横方向からの応力が生した場合であ
っても、銅線２３の横方向の自由度が制限されることに
より、隣接する銅線２３同士の接触を極力抑制すること
ができる。For this reason, especially in hermetically sealed ICs, depending on how the commercialized rC is used, for example, when the IC is subjected to vibration, etc., even if lateral stress is generated, By restricting the degree of freedom of the copper wires 23 in the lateral direction, contact between adjacent copper wires 23 can be suppressed as much as possible.

これにより、銅線２３の配線間隔を所定の幅に維持する
ことができ、当該半導体装置の信頼度の向上と、その生
産歩留りの向上と＠図ることが可能となる。Thereby, the wiring interval between the copper wires 23 can be maintained at a predetermined width, and it is possible to improve the reliability of the semiconductor device and its production yield.

第３図（Ａ）〜（Ｆ）、　　（ａ）〜（ｆ）は、本発明
の第１の実施例に係る半導体装置の形成工程図である。FIGS. 3A to 3F and 3A to 3F are process diagrams for forming a semiconductor device according to the first embodiment of the present invention.

なお、同図（Ａ）〜（Ｆ）は、本発明の実施例に係る上
面の形成工程図を示し、リードフレーム２１の全体図に
おいて破線円で囲んだ部分の拡大図番こ係る形成工程図
を示すものとする。Note that (A) to (F) of the same figure show the formation process diagram of the upper surface according to the embodiment of the present invention, and the enlarged view number of the part surrounded by a broken line circle in the overall view of the lead frame 21 is the formation process diagram. shall be shown.

また、同図（ａ）〜（ｆ）は、そのＸ−Ｙ矢視断面に係
る形成工程図を示すものとする。Moreover, the same figures (a)-(f) shall show the formation process diagram based on the X-Y arrow cross section.

同図（Ａ）、　　（ａ）において、まず、リードフレー
ム２１を開口して金属リード２１ａとなる電極形成領域
Ａ１と半導体チップ２２を搭載する半導体チップ搭載可
能領域Ａ２とを形成する。開口方法は帯状の鉄・ニッケ
ル合金や銅合金等の部材をエンチング処理や打ち抜き処
理することにより行う（同図（Ａ）、（ａ））。In FIGS. 2A and 2B, first, the lead frame 21 is opened to form an electrode forming area A1 that will become the metal lead 21a and a semiconductor chip mounting area A2 in which the semiconductor chip 22 is to be mounted. The opening method is performed by etching or punching a band-shaped member of iron-nickel alloy, copper alloy, etc. ((A) and (a) in the same figure).

次に、チップ搭載可能領域Ａ２に半導体チップ２２を搭
載する。該半導体チップ２２はリードフレーム２１にエ
ポキシ樹脂材にＡｇ（銀）又はＡｕ（金）等の粉末を含
有した接着剤２５により接着する（同図（Ｂ）、　　（
ｂ））。Next, the semiconductor chip 22 is mounted in the chip mounting area A2. The semiconductor chip 22 is bonded to the lead frame 21 with an adhesive 25 containing an epoxy resin material containing powder such as Ag (silver) or Au (gold) (see FIG. 2B).
b)).

次いで、半導体チップ２２を搭載した領域以外のチップ
搭載可能領域Ａ２から電極形成領域Ａ１に至る領域に絶
縁フィルム２４を形成する。絶縁フィルム２４は、例え
ば、半導体チンプ２２の最大設計サイズを定義し、これ
を基準にして大きさを規定する。これにより、汎用性の
拡充を図ることができる。Next, an insulating film 24 is formed in an area other than the area where the semiconductor chip 22 is mounted, ranging from the chip mounting area A2 to the electrode forming area A1. For example, the insulating film 24 defines the maximum design size of the semiconductor chip 22, and its size is determined based on this. This makes it possible to expand versatility.

また、絶縁フィルム２４には、予め、半導体チップ２２
に応して、その上面形状よりもわずかに大きい開口部を
設けて置く。その後、半導体チップ２２と絶縁フィルム
２４の開口部とを位置合わせして、該フィルム２４をチ
ップ搭載可能領域Ａ２に配置する。これによって、絶縁
フィルム２４を半導体チップ２２の周辺領域から各金属
リード２１ａに架橋させることができる。（同図（Ｃ）
（Ｃ〉）。Further, the insulating film 24 is provided with a semiconductor chip 22 in advance.
An opening slightly larger than the top surface shape is provided according to the shape of the top surface. Thereafter, the semiconductor chip 22 and the opening of the insulating film 24 are aligned, and the film 24 is placed in the chip mounting area A2. This allows the insulating film 24 to be bridged from the peripheral area of the semiconductor chip 22 to each metal lead 21a. (Figure (C)
(C>).

さらに、自動配線具２６を半導体チップ２２のパッド電
極２２ａに位置合わせする。この際の配線具２６は、直
径２５〔μｍ〕程度の銅線や金線等２３が筒状（キャピ
ラリ）から自動送出されるものである。また、ボンディ
ング距離により１ステツプの移動距離が可変できるもの
である（同図（Ｄ）、（ｄ））。Furthermore, the automatic wiring tool 26 is aligned with the pad electrode 22a of the semiconductor chip 22. The wiring fitting 26 at this time is one in which a copper wire, gold wire, etc. 23 having a diameter of about 25 [μm] is automatically fed out from a cylindrical (capillary). Furthermore, the moving distance of one step can be varied by changing the bonding distance ((D) and (d) in the same figure).

その後、自動配線具２６を電極形成領域Ａ１の金属リー
ド２１ａと半導体チップ２２のパッド電極２２ａとの間
に往復させる。この際に、金属リード２１ａや口径９０
〔μｍ〕程度のパッド電極２２ａと銅線等２３とは熱に
よって接合される。また、銅線２３の弛ませ方法は、ワ
イヤーボンディング装置の自動配線具の一回の移動距離
を従来例の移動距離よりも小さくすることにより行う０
例えば、ボンディング距離が３　（ｍｍ）程度の場合に
は、銅線等２３と絶縁フィルム２４との接触点数を２〜
３程度とする。また、その切断は超音波等により銅線等
２３を振動することにより行わう。（同図（Ｅ）、（ｅ
））。Thereafter, the automatic wiring tool 26 is moved back and forth between the metal lead 21a of the electrode formation area A1 and the pad electrode 22a of the semiconductor chip 22. At this time, the metal lead 21a and the diameter 90
The pad electrode 22a having a diameter of approximately [μm] and the copper wire 23 are bonded by heat. In addition, the method for loosening the copper wire 23 is to make the distance traveled by the automatic wiring tool of the wire bonding device smaller than that of the conventional example.
For example, when the bonding distance is about 3 (mm), the number of contact points between the copper wire etc. 23 and the insulating film 24 is 2 to 3 mm.
It should be about 3. Further, the cutting is performed by vibrating the copper wire 23 using ultrasonic waves or the like. ((E), (e)
)).

これにより、電極形Ｉｆｉ、ｅＩ域Ａ１の金属リード２
１ａと半導体チップ２２のパッド電極２２ａとを銅線や
金線等２３により弛ませて配線することができる。なお
、気密封止型のＩＣでは銅線２３の強度処理の後、又は
同時に、該銅線２３上から絶縁フィルム２４に接着剤２
７を滴下する。これにより、銅線２３を絶縁フィルム２
４に偏着することができる。（同図（Ｆ）、　　（ｆ）
）。As a result, the metal lead 2 of electrode type Ifi and eI area A1
1a and the pad electrode 22a of the semiconductor chip 22 can be interconnected with a loose copper wire, gold wire, or the like 23. In the case of a hermetically sealed IC, the adhesive 2 is applied to the insulating film 24 from above the copper wire 23 after the strength treatment of the copper wire 23 or at the same time.
Drip 7. This allows the copper wire 23 to be connected to the insulating film 2.
It can be biased to 4. (Same figure (F), (f)
).

このようにして、本発明の第１の方法によれば、半導体
チップ２２を搭載した領域以外のチップ搭載可能領域Ａ
２から電極形＄、領領域１に至る領域に絶縁フィルム２
４を形成している。In this way, according to the first method of the present invention, the chip mounting area A other than the area where the semiconductor chip 22 is mounted
Insulating film 2 in the area from 2 to electrode shape 1 to area 1
4 is formed.

このため、特定用途のＩＣの製造要求があった場合であ
っても、リードフレーム２１やパッケージサイズの設計
変更をすることなく、既存のリードフレーム、例えば、
最大サイズを規定したリードフレーム２１を使用して、
そのチップ搭載可能領域Ａ２に設計サイズよりも小さい
半導体チップ２２を取り付けることができる。これによ
って、配線間の絶縁特性が優れた信頼性の良い半導体装
置を製造することが可能となる。Therefore, even if there is a request to manufacture an IC for a specific purpose, there is no need to change the design of the lead frame 21 or package size.
Using a lead frame 21 with a specified maximum size,
A semiconductor chip 22 smaller than the designed size can be attached to the chip mounting area A2. This makes it possible to manufacture a highly reliable semiconductor device with excellent insulation properties between wirings.

これにより、総合的な開発工程数の低減化及び生産コス
トの低廉化を図ることが可能となる。This makes it possible to reduce the overall number of development steps and reduce production costs.

（ｉｉ）第２の実施例の説明 第４図は、本発明の第２の実施例に係る半導体装置の構
成国を示している。(ii) Description of Second Embodiment FIG. 4 shows the constituent countries of the semiconductor device according to the second embodiment of the present invention.

図において、第１の実施例と異なるのは第２の実施例で
は、既存のリードフレーム２１のチップ搭載可能領域Ａ
２に設計サイズの半導体チンブ３２を取り付けた場合を
示している。In the figure, the difference from the first embodiment is that the second embodiment has a chip mounting area A of the existing lead frame 21.
2 shows a case where a semiconductor chip 32 of the designed size is attached.

この場合も、半導体チップ３２を搭載したリードフレー
ム２１から金属リード２１ａに至る領域に絶縁フィルム
３４が設けられている。In this case as well, an insulating film 34 is provided in a region extending from the lead frame 21 on which the semiconductor chip 32 is mounted to the metal leads 21a.

ここで、第１の実施例と同じ符号のものは同じ機能を有
するため説明を省略する。また、第２の実施例に係る形
成工程についても、第１の実施例の形成工程と同様であ
るため説明を省略する。Here, components with the same reference numerals as those in the first embodiment have the same functions, and therefore their explanation will be omitted. Further, the formation process according to the second example is also the same as the formation process of the first example, so the explanation will be omitted.

なお、ボンディング距離が短くなるため、銅線３３等と
絶縁フィルム３４との接触点数が１回程度にされる点が
異なっている。The difference is that since the bonding distance is shortened, the number of points of contact between the copper wire 33 and the like and the insulating film 34 is reduced to about one.

これにより、第１の装置と同様にワイヤーボンディング
工程後におけるパンケージ処理の際に、絶縁フィルム３
４がストッパーとなって、銅線３３が導電性を有するス
テージ部２１ｂに接触することがない。As a result, similar to the first device, the insulating film 3
4 serves as a stopper to prevent the copper wire 33 from coming into contact with the conductive stage portion 21b.

また、！１１３３が絶縁フィルム３４上で適当な強度を
持って配線されるため、特に気密封止型のＩＣにおいて
、該ＩＣが振動等を受けた場合であっても、隣接する銅
線３３同士の接触を極力抑制することができる。Also,! 1133 is wired with appropriate strength on the insulating film 34, so even if the IC is subjected to vibration etc., especially in a hermetically sealed IC, adjacent copper wires 33 will not come into contact with each other. It can be suppressed as much as possible.

これにより、銅線３３の配線間隔を所定の幅に維持する
ことができ、当該半導体装置の信頼度の向上と、その生
産歩留りの向上とを図ることが可能となる。Thereby, the wiring interval between the copper wires 33 can be maintained at a predetermined width, and it is possible to improve the reliability of the semiconductor device and the production yield thereof.

なお、本発明の各実施例ではモールドパッケージ型の半
導体装置について述べたがセラミックパッケージ型の半
導体装置等についても応用することができる。In each embodiment of the present invention, a mold package type semiconductor device has been described, but the present invention can also be applied to a ceramic package type semiconductor device.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明によれば、半導体チップを搭
載したリードフレームから金属リードに至る領域に絶縁
フィルムが設けられ、銅線や金線等が該絶縁フィルム上
で適当な強度を持って配線されている。As explained above, according to the present invention, an insulating film is provided in the area from the lead frame on which the semiconductor chip is mounted to the metal leads, and copper wires, gold wires, etc. are wired with appropriate strength on the insulating film. has been done.

このため、樹脂封止型のＩＣにおいて上方向から応力生
じた場合であっても、銅線等がチップ搭載可能領域に電
気的に接触することがない。Therefore, even if stress is generated from above in a resin-sealed IC, copper wires and the like will not come into electrical contact with the chip mounting area.

また、気密封止型のＩＣにおいて、該ＩＣが振動等を受
けた際に、横方向からの応力が生した場合であっても、
銅線や金線等の配線形状を維持することができる。この
ことで、チップサイズに応じてリードフレームやパッケ
ージを選択する必要が無くなる。Furthermore, in a hermetically sealed IC, even if lateral stress is generated when the IC is subjected to vibration etc.
The wiring shape of copper wires, gold wires, etc. can be maintained. This eliminates the need to select a lead frame or package depending on the chip size.

これにより、当該半導体装置の信頼度の向上を図ること
、総合的な開発工程数の低減化及び生産コストの低廉化
を図ることが可能となる。This makes it possible to improve the reliability of the semiconductor device, reduce the overall number of development steps, and reduce production costs.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は、本発明に係る半導体装置の原理図、第２図は
、本発明の第１の実施例に係る半導体装置の構成図、 第３図は、本発明の第１の実施例に係る半導体装置の形
成工程図、 第４図は、本発明の第２の実施例に係る半導体装置の構
成図、 第５図は、従来例に係る半導体装置の構成図、第６図は
、従来例に係る問題点を説明する半導体装置の構成図で
ある。 （符号の説明） １１・・・導電性の基板、 １１ａ・・・配線電極、 １２・・・半導体チップ、 １２ａ・・・引出電極、 １３・・・導電体、 １４・・・絶縁性の基板、 Ａ１・・・電極形成領域、 Ａ２・・・チップ搭載可能領域。FIG. 1 is a principle diagram of a semiconductor device according to the present invention, FIG. 2 is a block diagram of a semiconductor device according to a first embodiment of the present invention, and FIG. 3 is a diagram of the structure of a semiconductor device according to a first embodiment of the present invention. FIG. 4 is a configuration diagram of a semiconductor device according to a second embodiment of the present invention, FIG. 5 is a configuration diagram of a semiconductor device according to a conventional example, and FIG. 6 is a configuration diagram of a semiconductor device according to a conventional example. FIG. 2 is a configuration diagram of a semiconductor device illustrating problems related to an example. (Explanation of symbols) 11... Conductive substrate, 11a... Wiring electrode, 12... Semiconductor chip, 12a... Leading electrode, 13... Conductor, 14... Insulating substrate , A1...electrode formation area, A2...chip mounting area.

Claims (2)

【特許請求の範囲】[Claims] （１）導電性の基板（１１）に搭載された半導体チップ
（１２）の引出電極（１２ａ）と前記導電性の基板（１
１）から分離された配線電極（１１ａ）とが導電体（１
３）により接続された半導体装置であって、 前記導電性の基板（１１）から配線電極（１１ａ）に至
る領域に絶縁性の基板（１４）が設けられ、前記導電体
（１３）が、予め、絶縁性の基板（１４）上で適当な強
度を持って配線されていることを特徴とする半導体装置
。(1) The lead electrode (12a) of the semiconductor chip (12) mounted on the conductive substrate (11) and the conductive substrate (11)
The wiring electrode (11a) separated from the conductor (1)
3), wherein an insulating substrate (14) is provided in a region extending from the conductive substrate (11) to the wiring electrode (11a), and the conductor (13) is connected in advance to the wiring electrode (11a). A semiconductor device characterized in that wiring is formed on an insulating substrate (14) with appropriate strength. （２）導電性の基板（１１）を開口して配線電極（１１
ａ）となる電極形成領域（Ａ１）と半導体チップ（１２
）を搭載するチップ搭載可能領域（Ａ２）とを形成する
工程と、 前記チップ搭載可能領域（Ａ２）に半導体チップ（１２
）を搭載する工程と、 前記半導体チップ（１２）を搭載した領域以外のチップ
搭載可能領域（Ａ２）から電極形成領域（Ａ１）に至る
領域に絶縁性の基板（１４）を形成する工程と、 前記電極形成領域（Ａ１）の配線電極（１１ａ）と前記
半導体チップの引出電極（１２ａ）とを導電体（１３）
により弛ませて配線する工程とを有することを特徴とす
る半導体装置の製造方法。(2) Open the conductive substrate (11) and open the wiring electrode (11).
a) The electrode formation area (A1) and the semiconductor chip (12
) for mounting a semiconductor chip (12) in the chip mounting area (A2).
), and a step of forming an insulating substrate (14) in an area extending from the chip mounting area (A2) to the electrode formation area (A1) other than the area where the semiconductor chip (12) is mounted; The wiring electrode (11a) of the electrode formation area (A1) and the lead electrode (12a) of the semiconductor chip are connected to a conductor (13).
1. A method for manufacturing a semiconductor device, comprising the step of loosening the wiring by the following steps.
JP2064872A 1990-03-15 1990-03-15 Semiconductor device and manufacture thereof Pending JPH03265148A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2064872A JPH03265148A (en) 1990-03-15 1990-03-15 Semiconductor device and manufacture thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2064872A JPH03265148A (en) 1990-03-15 1990-03-15 Semiconductor device and manufacture thereof

Publications (1)

Publication Number Publication Date
JPH03265148A true JPH03265148A (en) 1991-11-26

Family

ID=13270659

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2064872A Pending JPH03265148A (en) 1990-03-15 1990-03-15 Semiconductor device and manufacture thereof

Country Status (1)

Country Link
JP (1) JPH03265148A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1017099A2 (en) * 1998-12-31 2000-07-05 Texas Instruments Incorporated Improvements in or relating to semiconductor devices
JP2003086621A (en) * 2001-09-10 2003-03-20 Rohm Co Ltd Semiconductor device and manufacturing method therefor
US6759597B1 (en) * 1998-02-02 2004-07-06 International Business Machines Corporation Wire bonding to dual metal covered pad surfaces

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6759597B1 (en) * 1998-02-02 2004-07-06 International Business Machines Corporation Wire bonding to dual metal covered pad surfaces
EP1017099A2 (en) * 1998-12-31 2000-07-05 Texas Instruments Incorporated Improvements in or relating to semiconductor devices
EP1017099A3 (en) * 1998-12-31 2002-10-23 Texas Instruments Incorporated Improvements in or relating to semiconductor devices
JP2003086621A (en) * 2001-09-10 2003-03-20 Rohm Co Ltd Semiconductor device and manufacturing method therefor
JP4629284B2 (en) * 2001-09-10 2011-02-09 ローム株式会社 Semiconductor device and manufacturing method thereof

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