JP2000077595A - Lead frame and semiconductor integrated circuit device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a general-purpose semiconductor integrated circuit device by modifying the signal arrangement freely with a re-routing pattern produced through the patterning of a lead frame. SOLUTION: This lead frame 100 has one or a plurality of re-routing pattern 1 for electrically connecting a semiconductor integrated circuit chip with an inner lead, provided at a die pad part for mounting a semiconductor integrated circuit chip, an outer lead part, an inner lead 2 part, and a part between the die pad part and the inner lead 2 part.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device mounted and incorporated in an electronic device and having a signal arrangement internally, and a lead frame used therefor.

[0002]

2. Description of the Related Art FIG. 7 shows a schematic pattern of a general conventional lead frame 200. The lead frame 200 is made of an alloy, and is patterned by chemically etching or punching a metal plate. The lead frame 200 includes a die pad 4 on which a semiconductor integrated circuit (hereinafter referred to as “IC”) chip is mounted, a support bar 5 formed to hold the die pad 4 on the frame 10 of the lead frame 200, and an electrode pad of the IC chip. And an inner lead 2 joined by a thin metal wire such as a gold wire (hereinafter referred to as a “wire”), an outer lead 3 connected to the inner lead 2 and serving as an external joining terminal, and the like.

FIG. 8 shows a conventional lead frame 200.
The IC chip 50 is fixedly mounted on the die pad 4 with a die attach material, and the electrode pad 9 of the IC chip 50 is connected to the inner lead 2 having at least the joint part silver-plated by the wire 6. Is shown.

As described above, the electrode pads 9 for wire bonding bonding provided on the periphery of the IC chip 50 are
Each inner lead is connected to a predetermined inner lead formed on the lead frame by a wire, and each inner lead is connected to each outer lead formed on the lead frame by a pattern. R10, L1 to L10) 30 is the IC chip 5
Signal arrangement (R1 to R10, L1 to L10) of the electrode pads 9 for wire bonding bonding provided in the peripheral portion of 0
It is the same as 20. When the signal arrangement in the outer lead is changed (the signal arrangement 35 in FIG. 9 after the change),
The signal arrangement of the electrode pads 9 of the C chip is shown in FIG.
5 or wire bonding such that the wires 6 intersect as seen from above as shown in FIG.

[0005] Further, as shown in FIG. 11, changing the signal arrangement by extending some of the inner leads and bypassing the other inner leads is disclosed in Japanese Utility Model Registration No. 2566273. I have.

Further, in a semiconductor integrated circuit device having a structure in which an IC chip is mounted on both sides of a die pad provided on a lead frame for mounting the IC chip, an IC chip mounted on one side of the die pad and another side are provided. When the IC chip mounted on the side is electrically interconnected inside the semiconductor integrated circuit device, that is, when connecting a common electric signal to the same inner lead, either one of the IC chips or both Changing the arrangement of the electrode pads of the IC chip may be mentioned.

[0007]

As described above, in order to change the signal arrangement of the outer lead portion, the signal arrangement of the electrode pads of the IC chip is changed, or wire bonding such that thin metal wires intersect is selected. Will do. In the former case, the redesign of the IC chip, the remanufacture of photomasks for manufacturing, and the time and cost associated therewith arise.

In the latter case, since the wires must not come into contact with each other, a portion where the height of the wires is higher is required, and it is difficult to perform thin molding and sealing.

In the method of extending some of the inner leads and bypassing the other inner leads, the area where the signal arrangement is exchanged increases as the number of bypassed inner leads increases, so that the length of the wire is further increased. Become
A large force is applied during molding and sealing, which increases the possibility of deformation or cutting.

When an IC chip is mounted on both sides of a die pad using an existing IC chip, a common signal of an upper chip and a lower chip is required to assemble a smaller semiconductor integrated circuit device. Although it is desired to reduce the number of outer leads by wire bonding with the same inner lead, thin metal wires may intersect or wire bonding may not be possible due to layout.

[0011]

According to the present invention, there is provided a lead frame according to the present invention, comprising: a portion serving as a die pad for mounting a semiconductor integrated circuit chip; a portion serving as an outer lead;
One or a plurality of relays provided for electrically connecting the semiconductor integrated circuit chip and the inner lead between a portion serving as an inner lead and a portion serving as the die pad and a portion serving as the inner lead. It has a conductor.

According to a second aspect of the present invention, there is provided an integrated circuit device having a relay conductor electrically insulated from the inner lead and the die pad at least in a region between the inner lead and the die pad. The relay conductor is fixed to the inner lead and the die pad by an insulator, and the semiconductor integrated circuit chip mounted on the die pad is electrically connected directly or via the relay conductor. It is characterized by being connected to the inner lead.

According to a third aspect of the present invention, in the integrated circuit device of the present invention, a semiconductor integrated circuit chip is mounted on each of the front and back surfaces of the die pad.
3. A semiconductor integrated circuit device according to (1).

Further, in the integrated circuit device according to the present invention, the die pad is divided into a plurality of regions, and the relay conductor is connected to one inner lead across a region between the divided regions of the die pad. 3. The semiconductor device according to claim 2, wherein the relay conductor is formed on the other inner lead row side facing from the row side, and the relay conductor is electrically insulated from the semiconductor integrated circuit chip. 4. Item 4. A semiconductor integrated circuit device according to item 3.

[0015]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described in detail based on embodiments.

FIG. 1 shows a lead frame 100 according to the present invention.
3 shows a schematic pattern. FIG. 1 shows a rewiring pattern 1 serving as a relay conductor and a part of an inner lead 2 for holding the rewiring pattern 1 and FIG. Die pad 4
A polyimide film 7 attached so as to straddle a part of is attached. Like inner lead 2,
Silver plating is applied to at least a region to be joined by a wire on the rewiring pattern 1.

The structure of FIG. 1 is formed according to the sequence shown in FIG. First, patterning is performed by a method of manufacturing a conventional lead frame 200 such as chemical etching or punching with a mold (FIG. 3A). At this time, the rewiring pattern 1 described above is connected to a support bar 5 formed so as to hold the die pad 4 on the frame 10 of the lead frame 100.

Next, a thermoplastic polyimide film 7 punched into an appropriate size is attached so as to straddle the rewiring pattern 1, the inner lead 2, and the die pad 4 (FIG. 3B, a method of attaching the polyimide film). Is
This is the same as a generally known lead-on-chip lead frame manufacturing method).

Next, the holding portion 8 is punched out with a die so that each of the rewiring patterns 1 is electrically independent (FIG. 3).
(C)). Thus, a plurality of electrically independent rewiring patterns 1 are formed between the inner lead 2 and the die pad 4. Note that the polyimide film only needs to be able to be fixed so that the polyimide film itself does not move while keeping the rewiring pattern electrically independent.It is not necessary to attach the polyimide film so as to straddle the inner leads and the die pad. Other pattern portions formed in the region to be formed may be used.

FIG. 2 shows that in the lead frame 100 of FIG. 1 formed in the above-described order, a semiconductor integrated circuit (hereinafter referred to as “IC”) chip 50 is mounted on the die pad 4 (a die attach material is placed on the die pad). This shows a state in which the electrode pads 9 formed on the IC chip 50 and the inner leads 2 are connected by wires 6.

The signal arrangement 35 of the outer lead 3 shown in FIG. 3 is the same as that shown in FIG. 9 (change of the signal arrangement of the electrode pads of the IC chip) and FIG. The result is the same as wire bonding.

With the lead frame 100 shown in FIG. 1, the signal arrangement in the outer lead portion desired by the user can be obtained without changing the signal arrangement of the electrode pads 9 on the IC chip 50. IC on both sides of die pad
When mounting the chip 50, the lead frame of the present invention is effective. When the first IC chip is mounted on the front surface of the die pad and the second IC chip is mounted on the rear surface of the die pad, common signals of the first chip and the second chip are connected to the same inner lead. Want to reduce the number of outer leads. Therefore, the conventional lead frame 200
Is used, at least one of the IC chips needs to be as shown in FIG. 9 or FIG.

The lead frame 10 of the present invention shown in FIG.
0, the first IC chip 60 is mounted on the front surface of the die pad 4 and the second IC chip 70 is mounted on the back surface thereof as shown in the top view of FIG. 4A and the bottom view of FIG. The wires can be connected without crossing the wires, and the common signal of the first chip 60 and the second chip 70 can be electrically connected to the same outer lead. In FIG. 4, since the signal arrangement of the first IC chip 60 is matched with the signal arrangement of the second IC chip 70, only a part of the electrode pads of the first IC chip 60 is connected to the rewiring pattern by wire connection. However, the lead frame may be patterned so that wires can be connected to the rewiring pattern from both the electrode pads of the first IC chip 60 and the electrode pads of the second IC chip 70.

After the state shown in FIG. 4, the entire structure is sealed with a resin, exterior plating is performed, unnecessary portions are punched out, and outer leads are bent at predetermined positions to complete a semiconductor integrated circuit device (FIG. 5). ). Further, when the signals are exchanged in the opposite direction, the die pad 4 may be divided as shown in FIG. 6 and the lead frame 200 may be patterned so that the rewiring pattern passes through the gap. In this case,
An insulator such as a polyimide film is bonded by thermocompression bonding so as to cover the die pad portion and the rewiring portion dividing the die pad, so that the IC chip does not directly contact the rewiring pattern of the split portion of the die pad 4 after die bonding. .

In the above-described structure in which an IC chip is mounted on both sides of the die pad, the two ICs are provided via the die pad.
Even if the IC chip does not operate when the bulk potential of the chip becomes equal, at least one of the IC chips may be mounted on the die pad via an insulator such as a polyimide film.

[0026]

As described in detail above, the signal arrangement can be freely changed by the rewiring pattern produced by patterning the lead frame using the present invention, and the versatility of the semiconductor integrated circuit device is improved. Can be increased.

Further, a plurality of ICs may be provided in a semiconductor integrated circuit device.
When a chip is incorporated, a common signal can be easily connected to the same outer lead, which can contribute to a reduction in the number of outer leads and a reduction in the size of the semiconductor integrated circuit device (reduction in mounting area).

According to the fourth aspect, when the signals are exchanged in the opposite direction, the degree of freedom of the signal exchange is increased, which can further contribute to the miniaturization of the semiconductor integrated circuit device.

[Brief description of the drawings]

FIG. 1 is a plan view of a lead frame according to a first embodiment of the present invention.

FIG. 2 is a diagram showing a state in which an IC chip is die-bonded and wire-bonded using the lead frame according to the first embodiment of the present invention.

FIG. 3 is a manufacturing process diagram of the lead frame according to the first embodiment of the present invention.

FIG. 4A is a top view of a state in which an IC chip is die-bonded and wire-bonded to both sides of a die pad using the lead frame according to the first embodiment of the present invention, and FIG. It is.

FIG. 5A is a plan view of a semiconductor integrated circuit device after resin sealing using the lead frame according to the first embodiment of the present invention, and FIG. 5B is a sectional view of the same.

FIG. 6 is a diagram illustrating a state in which an IC chip is die-bonded and wire-bonded to both surfaces of a die pad using the lead frame according to the second embodiment of the present invention.

FIG. 7 is a plan view of a first conventional lead frame.

FIG. 8 shows an example of an IC using a first conventional lead frame.
It is a figure showing the state where a chip was die-bonded and wire-bonded.

FIG. 9 shows a first conventional lead frame using a first lead frame;
FIG. 7 is a diagram showing an example of a change in the signal arrangement.

FIG. 10 is a diagram showing a second signal arrangement modification example using a first conventional lead frame.

FIG. 11 is a diagram showing a third signal arrangement modification example using a second conventional lead frame.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Rewiring pattern 2 Inner lead 3 Outer lead 4 Die pad 5 Support bar 6 Wire 7 Polyimide film 8 Holding part 9 Electrode pad 10 Frame part 20 Representing signal arrangement of IC chip electrode pad 30 Representing outer lead signal arrangement 35 Outer Shows the signal arrangement after changing the leads 50, 60, 70 IC chip 80 Sealing resin 100 Lead frame 200 Conventional lead frame

 ────────────────────────────────────────────────── ─── Continuing from the front page (72) Katsunobu Mori Inventor F-term 5F067 AA18 AB02 BA03 BB08 BB10 BB15 BD05 BE09 CB08 CC03 CC08 CD01 CD06 DA11 in 22-22 Nagaikecho, Abeno-ku, Osaka-shi, Osaka DA16 DC13 DC17 DF02 DF06 DF09 DF11

Claims (4)

[Claims] 1. A semiconductor integrated circuit device comprising: a portion serving as a die pad on which a semiconductor integrated circuit chip is mounted; a portion serving as an outer lead; a portion serving as an inner lead; and a portion between the portion serving as a die pad and the portion serving as the inner lead. A lead frame comprising one or a plurality of relay conductors provided for electrically connecting a circuit chip and the inner leads. 2. The method according to claim 1, wherein the inner lead and the die pad have a relay conductor electrically insulated at least in a region between the inner lead and the die pad, and the relay conductor is formed by an insulator. A semiconductor fixed to an inner lead and a die pad, and wherein the semiconductor integrated circuit chip mounted on the die pad is directly or electrically connected to the inner lead via the relay conductor. Integrated circuit device. 3. The method according to claim 1, wherein each of the front and back surfaces of the die pad includes:
3. The semiconductor integrated circuit device according to claim 2, wherein a semiconductor integrated circuit chip is mounted. 4. The die pad is divided into a plurality of areas, and the relay conductor is formed on one inner lead row side facing another inner lead row side across the area between the divided areas of the die pad. 4. The semiconductor integrated circuit device according to claim 2, wherein said relay conductor is electrically insulated from said semiconductor integrated circuit chip.