JPH03261153A - Package for semiconductor device - Google Patents
Package for semiconductor deviceInfo
- Publication number
- JPH03261153A JPH03261153A JP2059308A JP5930890A JPH03261153A JP H03261153 A JPH03261153 A JP H03261153A JP 2059308 A JP2059308 A JP 2059308A JP 5930890 A JP5930890 A JP 5930890A JP H03261153 A JPH03261153 A JP H03261153A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor device
- resin
- tape
- metal film
- film layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 40
- 239000002184 metal Substances 0.000 claims abstract description 19
- 229910052751 metal Inorganic materials 0.000 claims abstract description 19
- 239000011347 resin Substances 0.000 abstract description 29
- 229920005989 resin Polymers 0.000 abstract description 29
- 238000007789 sealing Methods 0.000 abstract description 9
- 239000000853 adhesive Substances 0.000 abstract description 3
- 230000001070 adhesive effect Effects 0.000 abstract description 3
- 229910001111 Fine metal Inorganic materials 0.000 abstract 1
- 230000000694 effects Effects 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- XEEYBQQBJWHFJM-UHFFFAOYSA-N Iron Chemical compound [Fe] XEEYBQQBJWHFJM-UHFFFAOYSA-N 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 238000005452 bending Methods 0.000 description 1
- 238000005219 brazing Methods 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 229910052742 iron Inorganic materials 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 239000009719 polyimide resin Substances 0.000 description 1
- 238000004080 punching Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
Landscapes
- Wire Bonding (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は、半導体装置用パッケージの構造に関するも
のである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to the structure of a package for a semiconductor device.
第５図は従来の半導体装置を実装したパッケ−ジの一実
施例を示した断面図である０図において、１は半導体装
置、２はリードフレームのダイスパッド部であり、半導
体装置１をロー材４にて接合している。５は金属細線で
あり、半導体装置１上の電極部とリードフレームのリー
ド部３を電気的に接合している。６は封止用樹脂であり
、上記半導体装置１を保護する役割を果している。FIG. 5 is a sectional view showing an example of a conventional package mounted with a semiconductor device. In FIG. It is joined with material 4. Reference numeral 5 denotes a thin metal wire, which electrically connects the electrode section on the semiconductor device 1 and the lead section 3 of the lead frame. A sealing resin 6 serves to protect the semiconductor device 1 .
次に、上記半導体装置用パッケージの組立動作について
説明する。まず半導体装置１をリードフレームのダイス
パッド部２にロー材４にて接合する。Next, the assembly operation of the semiconductor device package will be explained. First, the semiconductor device 1 is bonded to the die pad portion 2 of a lead frame using a brazing material 4.
そして、半導体装置ｌの電極部とリードフレームのリー
ド部３とを金属細線５により電気的に接合する。さらに
、半導体装置１を外部から保護する等の目的で、封止用
樹脂６により封止を行う。なお、上記リードフレームの
ダイスパッド部２．リード部３は鉄・銅系の材料が使わ
れており、一般にパンチング及びエツチングによりパタ
ーンが作成されている。Then, the electrode portion of the semiconductor device 1 and the lead portion 3 of the lead frame are electrically connected using the thin metal wire 5. Furthermore, for the purpose of protecting the semiconductor device 1 from the outside, etc., sealing is performed with a sealing resin 6. It should be noted that the die pad portion 2 of the above lead frame. The lead portion 3 is made of iron/copper material, and the pattern is generally created by punching and etching.
従来の半導体装置用パッケージは上記のような槽底であ
り、リードフレームのリード本数が多くなるに従い、リ
ードフレームを製作しても、リード先端が変形しやすく
、実使用において使用しにくい等の問題点が発生してい
た。Conventional packages for semiconductor devices have a bath bottom as described above, and as the number of leads in a lead frame increases, even if a lead frame is manufactured, the lead tips tend to deform, making it difficult to use in actual use. points were occurring.
この発明は上記のような問題点を解消するためになされ
たものであり、リード本数が多くなっても、リード先端
の位置精度を高く保持することができる半導体装置用パ
ッケージを得ることを目的とする。This invention was made to solve the above-mentioned problems, and its purpose is to obtain a package for a semiconductor device that can maintain high positional accuracy of the lead tips even when the number of leads increases. do.
この発明に係る半導体装置用パッケージは、テープ状の
絶縁樹脂の一面に金属膜層の配線パターンを形成させ、
さらに上記テープ状樹脂の一部を半導体装置の一面と接
合させ、半導体装置の電極とテープ状樹脂上の配線パタ
ーンとを金属細線にて接合させるようにしたものである
。A package for a semiconductor device according to the present invention has a wiring pattern of a metal film layer formed on one surface of a tape-shaped insulating resin,
Furthermore, a part of the tape-shaped resin is bonded to one surface of the semiconductor device, and the electrodes of the semiconductor device and the wiring pattern on the tape-shaped resin are bonded using thin metal wires.
この発明の半導体装置用パッケージによれば、テープ状
絶縁樹脂の一面に金属膜層をパターニングするため、位
置精度の高いリードポストを設けることができ、さらに
上記テープ状絶縁樹脂と半導体装置の一面とを接合する
ことにより、より生産性の高い半導体装置の組立てが可
能となる。According to the semiconductor device package of the present invention, since the metal film layer is patterned on one surface of the tape-shaped insulating resin, lead posts with high positional accuracy can be provided, and furthermore, the tape-shaped insulating resin and one surface of the semiconductor device can be provided with lead posts with high positional accuracy. By joining, it becomes possible to assemble semiconductor devices with higher productivity.
以下、この発明の一実施例を図について説明する。第１
図はこの発明の一実施例による半導体装置用パッケージ
を示す斜視図、第２図は上記半導体装置用パッケージを
封止した状態を示す断面図である６図において、１は半
導体装置、７は電気的絶縁性を有する材料からなるテー
プ状樹脂であり、上記半導体装置１の一面と接着材等で
接合されている。さらに、８はテープ状樹脂７の一面に
パターニングされた金属膜層であり、金属細線５によっ
て半導体装置１上に形成された電極と電気的に接続され
ている。６は半導体装置保護のための封止用樹脂である
。An embodiment of the present invention will be described below with reference to the drawings. 1st
6 is a perspective view showing a semiconductor device package according to an embodiment of the present invention, and FIG. 2 is a sectional view showing the semiconductor device package in a sealed state. In FIG. It is a tape-shaped resin made of a material having electrically insulating properties, and is bonded to one surface of the semiconductor device 1 with an adhesive or the like. Furthermore, 8 is a metal film layer patterned on one surface of the tape-shaped resin 7, and is electrically connected to an electrode formed on the semiconductor device 1 by a thin metal wire 5. 6 is a sealing resin for protecting the semiconductor device.
次に、本実施例の組立動作について説明する。まず半導
体装１１の一生面とテープ状樹脂７とを接着材等により
接合し、更に、金属膜ｉ１５により、半導体装置１の電
極部とテープ状樹脂７の一面にバターニングされた金属
膜層８とを電気的に接続する。そして、最後に半導体装
置１の保護の目的で封止用樹脂６等により全体を封止す
る。Next, the assembly operation of this embodiment will be explained. First, the whole surface of the semiconductor device 11 and the tape-shaped resin 7 are bonded together using an adhesive or the like, and then a metal film layer 8 patterned on the electrode portion of the semiconductor device 1 and one surface of the tape-shaped resin 7 is formed using a metal film i15. electrically connect the Finally, for the purpose of protecting the semiconductor device 1, the entire semiconductor device 1 is sealed with a sealing resin 6 or the like.
なお、第２図において、半導体装置１の一面とテープ状
樹脂７との接続は、中心部を一本で接続した構造になっ
ているが、接続部の形状・本数共にこの通りでなくても
同様の効果がある。In FIG. 2, the connection between one surface of the semiconductor device 1 and the tape-shaped resin 7 is such that the center portion is connected by one wire, but the shape and number of the connecting portions may not be as shown. It has a similar effect.
また、封止用樹脂６より外側にあるテープ状樹脂７及び
金属膜層８は、第３図に示すように一体であっても、第
４図に示すように個々に分離されている状態であっても
良く、さらに外部の部分を曲げ加工して使用しても、曲
げ加工なしで使用しても良い。Further, even if the tape-shaped resin 7 and the metal film layer 8 located outside the sealing resin 6 are integrated as shown in FIG. 3, they may be separated into individual parts as shown in FIG. The external portion may be bent, or may be used without bending.
また、テープ状樹脂７は例えばポリイミド系の樹脂が望
ましいが、特に電気的に不導体であれば指定はしない０
．ｔた金属膜層８もメツキを施していてもいなくても良
い。The tape-shaped resin 7 is preferably made of polyimide resin, for example, but it is not specified as long as it is electrically nonconductive.
．． The metal film layer 8 may or may not be plated.
以上のように、この発明によればテープ状絶縁樹脂の一
面に金属膜層をバターニングするため、位置精度の高い
リードポストを設けることができ、さらに上記テープ状
樹脂と半導体装置の一面とを接合することにより、より
生産性の高い半導体装置の組立てができる効果がある。As described above, according to the present invention, since the metal film layer is patterned on one surface of the tape-shaped insulating resin, lead posts with high positional accuracy can be provided, and furthermore, the tape-shaped resin and one surface of the semiconductor device can be provided. Bonding has the effect of allowing semiconductor devices to be assembled with higher productivity.
第１図はこの発明の一実施例による半導体装置用パッケ
ージを示す斜視図、第２図は上記半導体装置用パッケー
ジを封止した状態を示す断面図、第３図、第４図は封止
用樹脂外部でのテープ状樹脂の形状を示す斜視図、第５
図は従来の半導体装置用パッケージを示す断面図である
。
図中、１は半導体装置、５は金属細線、６は封止用樹脂
、７はテープ状樹脂、８は金属膜層である。
なお、図中同一符号は同−又は相当部分を示す。FIG. 1 is a perspective view showing a semiconductor device package according to an embodiment of the present invention, FIG. 2 is a sectional view showing the semiconductor device package in a sealed state, and FIGS. 3 and 4 are for sealing. A fifth perspective view showing the shape of the tape-shaped resin outside the resin.
The figure is a sectional view showing a conventional package for a semiconductor device. In the figure, 1 is a semiconductor device, 5 is a thin metal wire, 6 is a sealing resin, 7 is a tape-shaped resin, and 8 is a metal film layer. Note that the same reference numerals in the figures indicate the same or equivalent parts.
Claims (1)
成されたテープ状絶縁板を備え、上記半導体装置の一面
と上記テープ状絶縁板の一部とを接合させ、上記金属膜
層の配線パターンと上記半導体装置の電極とを金属細線
により接続したことを特徴とする半導体装置用パッケー
ジ。A semiconductor device and a tape-shaped insulating plate on which a wiring pattern of a metal film layer is formed, one surface of the semiconductor device and a part of the tape-shaped insulating plate are joined, and the wiring pattern of the metal film layer is formed. A package for a semiconductor device, characterized in that the electrode of the semiconductor device is connected to the electrode of the semiconductor device by a thin metal wire.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2059308A JPH03261153A (en) | 1990-03-09 | 1990-03-09 | Package for semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2059308A JPH03261153A (en) | 1990-03-09 | 1990-03-09 | Package for semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH03261153A true JPH03261153A (en) | 1991-11-21 |
Family
ID=13109617
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2059308A Pending JPH03261153A (en) | 1990-03-09 | 1990-03-09 | Package for semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH03261153A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5347429A (en) * | 1990-11-14 | 1994-09-13 | Hitachi, Ltd. | Plastic-molded-type semiconductor device |
| US5446313A (en) * | 1992-05-25 | 1995-08-29 | Hitachi, Ltd. | Thin type semiconductor device and module structure using the device |
| US5473514A (en) * | 1990-12-20 | 1995-12-05 | Kabushiki Kaisha Toshiba | Semiconductor device having an interconnecting circuit board |
| JPH08330491A (en) * | 1995-05-27 | 1996-12-13 | Nec Corp | Semiconductor device |
-
1990
- 1990-03-09 JP JP2059308A patent/JPH03261153A/en active Pending
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5347429A (en) * | 1990-11-14 | 1994-09-13 | Hitachi, Ltd. | Plastic-molded-type semiconductor device |
| US5473514A (en) * | 1990-12-20 | 1995-12-05 | Kabushiki Kaisha Toshiba | Semiconductor device having an interconnecting circuit board |
| US5613295A (en) * | 1990-12-20 | 1997-03-25 | Kabushiki Kaisha Toshiba | Semiconductor device having an interconnecting circuit board and method for manufacturing same |
| US5646830A (en) * | 1990-12-20 | 1997-07-08 | Kabushiki Kaisha Toshiba | Semiconductor device having an interconnecting circuit board |
| US5715147A (en) * | 1990-12-20 | 1998-02-03 | Kabushiki Kaisha Toshiba | Semiconductor device having an interconnecting circuit board |
| US5446313A (en) * | 1992-05-25 | 1995-08-29 | Hitachi, Ltd. | Thin type semiconductor device and module structure using the device |
| US5723903A (en) * | 1992-05-25 | 1998-03-03 | Hitachi, Ltd. | Thin type semiconductor device, module structure using the device and method of mounting the device on board |
| US5895969A (en) * | 1992-05-25 | 1999-04-20 | Hitachi, Ltd. And Hitachi Vlsi Engineering Corp. | Thin type semiconductor device, module structure using the device and method of mounting the device on board |
| JPH08330491A (en) * | 1995-05-27 | 1996-12-13 | Nec Corp | Semiconductor device |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6225146B1 (en) | Lead frame, method of manufacturing lead frame, semiconductor device and method of manufacturing semiconductor device | |
| JP3205235B2 (en) | Lead frame, resin-encapsulated semiconductor device, method of manufacturing the same, and mold for manufacturing semiconductor device used in the manufacturing method | |
| JP3383081B2 (en) | Electronic component manufactured using anodic bonding and method of manufacturing electronic component | |
| EP0349549A1 (en) | Support assembly for integrated circuits | |
| JP2569939B2 (en) | Resin-sealed semiconductor device | |
| JPH04280462A (en) | Lead frame and semiconductor device using this lead frame | |
| JPH03177060A (en) | Lead frame for semiconductor device | |
| JPS62232948A (en) | Lead frame | |
| JPH0777228B2 (en) | Tape carrier | |
| JP2569400B2 (en) | Method for manufacturing resin-encapsulated semiconductor device | |
| JPH03261153A (en) | Package for semiconductor device | |
| JPS61183936A (en) | Semiconductor device | |
| JPH01132142A (en) | Package structure of semiconductor device | |
| JP3174238B2 (en) | Semiconductor device and method of manufacturing the same | |
| JP2602834B2 (en) | Semiconductor device | |
| JPS62260343A (en) | Semiconductor device | |
| JPH0366150A (en) | Semiconductor integrated circuit device | |
| JPH1140728A (en) | Lead frame and electronic component using the same, and manufacture thereof | |
| JP3665609B2 (en) | Semiconductor device and semiconductor device unit having a plurality of semiconductor devices mounted thereon | |
| JP2635722B2 (en) | Lead frame and manufacturing method thereof | |
| JP2000077595A (en) | Lead frame and semiconductor integrated circuit device | |
| JPH07249708A (en) | Semiconductor device and its mounting structure | |
| JP2536439B2 (en) | Lead frame for semiconductor device and resin-sealed semiconductor device using the same | |
| JP4240699B2 (en) | Lead material | |
| JPH031551A (en) | Resin-sealed semiconductor device |