JPH03177060A - Lead frame for semiconductor device - Google Patents
Lead frame for semiconductor deviceInfo
- Publication number
- JPH03177060A JPH03177060A JP31623189A JP31623189A JPH03177060A JP H03177060 A JPH03177060 A JP H03177060A JP 31623189 A JP31623189 A JP 31623189A JP 31623189 A JP31623189 A JP 31623189A JP H03177060 A JPH03177060 A JP H03177060A
- Authority
- JP
- Japan
- Prior art keywords
- die pad
- semiconductor element
- lead frame
- protrusion
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 45
- 229920005989 resin Polymers 0.000 claims abstract description 18
- 239000011347 resin Substances 0.000 claims abstract description 18
- 230000003014 reinforcing effect Effects 0.000 claims abstract description 11
- 238000000465 moulding Methods 0.000 claims description 7
- 238000000034 method Methods 0.000 abstract description 11
- 238000005452 bending Methods 0.000 abstract description 8
- 239000000853 adhesive Substances 0.000 description 3
- 230000001070 adhesive effect Effects 0.000 description 3
- 239000003822 epoxy resin Substances 0.000 description 3
- 229920000647 polyepoxide Polymers 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000009429 electrical wiring Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 229910000679 solder Inorganic materials 0.000 description 2
- 229910000881 Cu alloy Inorganic materials 0.000 description 1
- 229910000640 Fe alloy Inorganic materials 0.000 description 1
- 239000012141 concentrate Substances 0.000 description 1
- 238000005336 cracking Methods 0.000 description 1
- 238000006073 displacement reaction Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 238000004080 punching Methods 0.000 description 1
Abstract
Description
【発明の詳細な説明】
（産業上の利用分野）
この発明は、半導体装置のパッケージ、特にトランジス
タのパッケージの半導体装置用リードフレームに関する
ものである。DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a lead frame for a semiconductor device package, particularly a transistor package.
半導体装置のパッケージの多くは、電気的配線及び半導
体素子の搭載のためのリードフレーム。Most semiconductor device packages include lead frames for mounting electrical wiring and semiconductor elements.
電気的配線のためのボンディングワイヤ及び半導体素子
やボンディングワイヤの保護のためのモールド樹脂から
なっている。It consists of bonding wires for electrical wiring and molding resin for protecting semiconductor elements and bonding wires.
リードフレームの材料は銅合金または鉄合金が主であり
、プレス打ち抜き加工もしくはエツチング加工を施して
製造され、ボンディングワイヤには直径２５μｍ程度の
金線、モールド樹脂にはエポキシ樹脂が使用されること
が多い。The main material of the lead frame is copper alloy or iron alloy, and it is manufactured by press punching or etching. Gold wire with a diameter of about 25 μm is used for the bonding wire, and epoxy resin is used for the molding resin. many.
第４図（ａ）及び（ｂ）は、従来のトランジスタのパッ
ケージの平面図及びＢ−Ｂ線断面図であり、この図はリ
ードフレーム１の表面のモールド樹脂４を取除いた場合
の平面図である。１は３本のリードフレームであり、ボ
ンディングワイヤ３により接続されている。４はモール
ド樹脂であり、３本のリードフレーム１と半導体素子２
がモールド樹脂４内に固定されている。リードフレーム
１において、５はダイパッド、６はインナーリード、７
はアウターリードである。FIGS. 4(a) and 4(b) are a plan view and a sectional view taken along the line B-B of a conventional transistor package, and this figure is a plan view when the molding resin 4 on the surface of the lead frame 1 is removed. It is. Reference numeral 1 indicates three lead frames, which are connected by bonding wires 3. 4 is a molding resin, which includes three lead frames 1 and a semiconductor element 2.
is fixed in the mold resin 4. In the lead frame 1, 5 is a die pad, 6 is an inner lead, and 7 is a die pad.
is the outer lead.
また、３木のリードフレーム１の内、真中の１本はダイ
パッド５を兼ねており、半導体素子２はダイパッド５の
表面に接着剤１３により接着されている。ダイパッド部
５はインナーリード６やアウターリード７の幅より若干
広くなっている。半導体素子２にはベース１４とエミッ
タ１５の２つの電極があり、それぞれ両側のリードフレ
ーム１ヘボンディングワイヤ３により接続され、コレク
タ１６はダイパッド５との接着側にあり、導電性の接着
剤またははんだを介してリードフレーム１へ接続されて
いる。Further, among the three lead frames 1, the middle one also serves as a die pad 5, and the semiconductor element 2 is bonded to the surface of the die pad 5 with an adhesive 13. The die pad portion 5 is slightly wider than the inner leads 6 and outer leads 7. The semiconductor element 2 has two electrodes, a base 14 and an emitter 15, which are connected to the lead frame 1 on both sides by bonding wires 3, and the collector 16 is on the adhesive side with the die pad 5, and is connected to the lead frame 1 on both sides using a conductive adhesive or solder. It is connected to the lead frame 1 via.
第５図（ａ）、（ｂ）、（ｃ）、（ｄ）は半導体装置の
組立工程図を示す。半導体装置の組立工程は、まずリー
ドフレーム１のダイパッド５に半導体素子２をはんだま
たはエポキシ樹脂等で接着し、半導体素子２のヘース１
４とエミッタ１５の２つの電極とインナーリード６をボ
ンディングワイヤ３で配線し、次にエポキシ樹脂等でモ
ールド４を成形し、最後にアウターリード７をｌ１１１
げて完成している。FIGS. 5(a), (b), (c), and (d) show assembly process diagrams of the semiconductor device. In the assembly process of the semiconductor device, first, the semiconductor element 2 is bonded to the die pad 5 of the lead frame 1 with solder or epoxy resin, and the base 1 of the semiconductor element 2 is bonded to the die pad 5 of the lead frame 1.
4 and the emitter 15 and the inner lead 6 are wired with the bonding wire 3, then a mold 4 is formed with epoxy resin, etc., and finally the outer lead 7 is wired with the l111.
completed.
従来の半導体装置、特にトランジスタの場合は、ダイパ
ッド５か１方向たけて支えられている上、アウターリー
ト７とつながっているため、アウターリード７を外側へ
引っ張る力に対して抵抗部の対抗力が小さかった。従っ
て、アウターリード７を曲げる工程において、ダイパッ
ド５か外側に引っ張られ、その応力を半導体素子２が受
けるため、例えば第６図に示すように、半導体素子２に
クラック１２が入るという問題があった。In the case of conventional semiconductor devices, especially transistors, the die pad 5 is supported vertically in one direction and is connected to the outer lead 7, so that the force that pulls the outer lead 7 outward is counterforced by the resistive part. It was small. Therefore, in the process of bending the outer lead 7, the die pad 5 is pulled outward and the semiconductor element 2 receives this stress, resulting in the problem that a crack 12 occurs in the semiconductor element 2, as shown in FIG. 6, for example. .
この発明は、このような従来の問題点を解決するために
なされたもので、アウターリード曲げ工程において、半
導体素子２にクラックの発生しない、イ３頼性の高い半
導体装置用リードフレームを提供することを目的として
いる。This invention was made to solve these conventional problems, and provides a highly reliable lead frame for a semiconductor device that does not cause cracks in the semiconductor element 2 during the outer lead bending process. The purpose is to
（：１ｍを解決するための手段）
この発明は、半導体素子を固着するダイパッド部に補強
固定部を連設し所望のモールド樹脂に固定してなること
を特徴とする半導体装置用リードフレームに係わり、上
記目的を解決しようとするものである。(Means for solving the problem of 1 m) The present invention relates to a lead frame for a semiconductor device, which is characterized in that a reinforcing fixing part is connected to a die pad part to which a semiconductor element is fixed, and the reinforcing fixing part is fixed to a desired molding resin. , which attempts to solve the above objectives.
この発明による半導体装置用リードフレームは、半導体
素子を固着するダイパッド部に補強固定部を設けたこと
により、ダイパッドがモールド樹脂によってより完全に
固定される。このようなリードフレームを用いれば、ア
ウターリード曲げ工程においてアウターリート方向へ強
く引っ張られてもダイパッドの位置ずれ及び半導体素子
に対する応力の集中が最小限に抑えられ、半導体素子に
クラックか入る可能性は非常に低くなる。In the lead frame for a semiconductor device according to the present invention, the reinforcing fixing portion is provided in the die pad portion to which the semiconductor element is fixed, so that the die pad is more completely fixed by the molding resin. If such a lead frame is used, even if the outer lead is strongly pulled in the direction of the outer lead during the outer lead bending process, the displacement of the die pad and the concentration of stress on the semiconductor element can be minimized, and the possibility of cracks in the semiconductor element is minimized. becomes very low.
第１図は本発明に係わる半導体装置用リードフレームの
１実施例を示す平面図であり、この図はリードフレーム
１の表面のモールド樹脂４を取除いた場合の平面図であ
る。８は補強固定部に相当する突起であり、この突起８
は、ダイパッド部５のモールド樹脂４内の先端部に連設
している。そして、突起８はダイパッド部５と同一厚さ
を有し、グイバット部５の横方向の幅より長い横幅Ｌ１
の長方形状ａを備え、この長方形状ａの横幅Ｌ１より短
い幅２の接続部９によりダイパッド部５と接続している
。FIG. 1 is a plan view showing one embodiment of a lead frame for a semiconductor device according to the present invention, and this figure is a plan view when the mold resin 4 on the surface of the lead frame 1 is removed. 8 is a protrusion corresponding to the reinforcing fixing part, and this protrusion 8
is connected to the tip of the die pad portion 5 inside the mold resin 4. The protrusion 8 has the same thickness as the die pad part 5, and has a width L1 longer than the width in the lateral direction of the guibat part 5.
It has a rectangular shape a, and is connected to the die pad portion 5 by a connecting portion 9 having a width 2 shorter than the width L1 of the rectangular shape a.
なお、上述の突起以外の他の構成は従来のパッケージと
同一であり、従来例と同一または相当する構成には同一
符号を付してその説明を省く。Note that the other configurations other than the above-mentioned protrusions are the same as the conventional package, and the same reference numerals are given to the same or corresponding configurations as in the conventional example, and the explanation thereof will be omitted.
上述の構成になるので、半導体装置のアウタ−リー１７
を曲げる工程においてダイパッド５は外側へ引っ張られ
る応力を受けるが、本実施例による半導体装置では、ダ
イパッド５に突起８を設けたため、ダイパッド５が応力
を受けても突起８が十分対抗してモールド樹脂４で食い
止められるので、応力が半導体素子２に集中することは
なくなり半導体素子２にクラックの入る可能性が著しく
低下している。With the above configuration, the outer layer 17 of the semiconductor device
In the process of bending the die pad 5, the die pad 5 is subjected to stress that is pulled outward. However, in the semiconductor device according to this embodiment, the protrusion 8 is provided on the die pad 5, so that even if the die pad 5 is subjected to stress, the protrusion 8 sufficiently counters the mold resin. 4, stress is no longer concentrated on the semiconductor element 2, and the possibility of cracks occurring in the semiconductor element 2 is significantly reduced.
第２図は本発明の他の実施例を示す平面図であり、ダイ
パッド５とインナーリード６との間に補強固定部に相当
する突起１０を設けている。突起１０は、ダイパッド部
５と同一厚さを有し、ダイパッド部５の横方向の幅より
長い幅Ｌ２で両側に突き出した長方形状すであり、ダイ
パッド部５に連設している。その働きは第１図の実施例
と全く同様である。FIG. 2 is a plan view showing another embodiment of the present invention, in which a protrusion 10 corresponding to a reinforcing fixing portion is provided between the die pad 5 and the inner lead 6. The protrusion 10 has the same thickness as the die pad portion 5 and has a rectangular shape protruding from both sides with a width L2 longer than the width of the die pad portion 5 in the lateral direction, and is connected to the die pad portion 5. Its operation is exactly the same as the embodiment shown in FIG.
第３図も本発明の他の実施例を示す平面図であり、補強
固定部に相当するアンカーホール１１をダイパッド５の
先端部及びダイパッド５とインナーリード６との間に設
けている。アンカーホール１１の長さはダイパッド５の
厚さと同一であり、ダイパッド５の横方向の幅より短い
直径を有し、ダイパッド５内に設けられている。FIG. 3 is also a plan view showing another embodiment of the present invention, in which an anchor hole 11 corresponding to a reinforcing fixing portion is provided at the tip of the die pad 5 and between the die pad 5 and the inner lead 6. The length of the anchor hole 11 is the same as the thickness of the die pad 5, and the anchor hole 11 has a diameter shorter than the width of the die pad 5 in the lateral direction, and is provided in the die pad 5.
上述の構成になるのでアンカーホール１１はその中に充
填されたモールド樹脂４て食い止められ、ダイパッド５
が動いて半導体素子２に応力が集中して半導体素子２に
クラックが入るといった不都合を著しく減少させること
ができた。With the above configuration, the anchor hole 11 is stopped by the mold resin 4 filled therein, and the die pad 5
This makes it possible to significantly reduce the inconvenience that the semiconductor element 2 moves and stress concentrates on the semiconductor element 2, causing cracks in the semiconductor element 2.
なお、突起８，１０の形状及び大きさは第１図及び第２
図の実施例に限ったものではなく、ダイパッド５かアウ
ターリート７方向へ動くのを姑げるような形状であれば
良い。また、アンカーホール１１の形状、大きさ及び個
数も、箪３図の実施例に限ったものではなく、突起８．
１０と同様の働きをするものであれば良い。The shapes and sizes of the protrusions 8 and 10 are as shown in Figures 1 and 2.
The shape is not limited to the illustrated embodiment, and any shape may be used as long as it prevents movement toward the die pad 5 or the outer reel 7. Further, the shape, size, and number of the anchor holes 11 are not limited to the embodiment shown in FIG.
Any material that functions similarly to 10 may be used.
以上説明したように、この発明によれば、半導体装置用
リードフレームの半導体素子を固着するダイパッド部に
補強固定部を設けたことにより、アウターリード曲げ工
程において半導体素子にクラックが入らないという効果
がある。As explained above, according to the present invention, by providing the reinforcing fixing part in the die pad part of the lead frame for a semiconductor device to which the semiconductor element is fixed, it is possible to prevent the semiconductor element from cracking during the outer lead bending process. be.
第１図は本発明による半導体装置用リードフレームの１
実施例を示すモールド樹脂を取除いた場合の平面図、第
２図及び第３図は本発明の他の異なる２つの実施例を示
すモールド樹脂を取除いた場合の平面図、第４図（ａ）
及び（ｂ）は従来のトランジスタのパッケージのリード
フレームを示す平面図及びＢ−Ｂ線断面図、第５図（ａ
）。
（ｂ）、（Ｃ）、（ｄ）は従来の半導体装置の組立工程
図、第６図はアウターリード曲げ工程における半導体素
子のクラック発生を示す断面図である。
１はリードフレーム、２は半導体素子、３はボンディン
グワイヤ、４はモールド樹脂、５はダイパッド、６はイ
ンナーリード、７はアウターリート、８及び！０は突起
、９は接続部、１１はアンカーホール、１４はベース、
１５はエミッタである。なお、Ｌｌ及びＬ２は突起の横
幅、児は接続部の横幅、ａ及びｂは突起の長方形状であ
る。
なお。
各図中間
符号は同
または相当部分を
示す。FIG. 1 shows one of the lead frames for semiconductor devices according to the present invention.
FIGS. 2 and 3 are plan views showing an embodiment with the mold resin removed, and FIG. 4 is a plan view showing two other different embodiments of the present invention with the mold resin removed. a)
and (b) is a plan view and a sectional view taken along the line B-B of the lead frame of a conventional transistor package, and FIG.
). (b), (C), and (d) are assembly process diagrams of a conventional semiconductor device, and FIG. 6 is a cross-sectional view showing the occurrence of cracks in a semiconductor element during the outer lead bending process. 1 is a lead frame, 2 is a semiconductor element, 3 is a bonding wire, 4 is a mold resin, 5 is a die pad, 6 is an inner lead, 7 is an outer lead, 8 and! 0 is a projection, 9 is a connection part, 11 is an anchor hole, 14 is a base,
15 is an emitter. Note that L1 and L2 are the widths of the protrusions, L1 is the width of the connecting portion, and a and b are the rectangular shapes of the protrusions. In addition. The symbols in the middle of each figure indicate the same or corresponding parts.
Claims (1)
設し所望のモールド樹脂に固定してなることを特徴とす
る半導体装置用リードフレーム。A lead frame for a semiconductor device, characterized in that a reinforcing fixing part is provided in series with a die pad part to which a semiconductor element is fixed, and the reinforcing fixing part is fixed to a desired molding resin.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP31623189A JPH03177060A (en) | 1989-12-05 | 1989-12-05 | Lead frame for semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP31623189A JPH03177060A (en) | 1989-12-05 | 1989-12-05 | Lead frame for semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH03177060A true JPH03177060A (en) | 1991-08-01 |
Family
ID=18074772
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP31623189A Pending JPH03177060A (en) | 1989-12-05 | 1989-12-05 | Lead frame for semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH03177060A (en) |
Cited By (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8154111B2 (en) | 1999-12-16 | 2012-04-10 | Amkor Technology, Inc. | Near chip size semiconductor package |
| US8691632B1 (en) | 2002-11-08 | 2014-04-08 | Amkor Technology, Inc. | Wafer level package and fabrication method |
| US8866278B1 (en) | 2011-10-10 | 2014-10-21 | Amkor Technology, Inc. | Semiconductor device with increased I/O configuration |
| US8900995B1 (en) | 2010-10-05 | 2014-12-02 | Amkor Technology, Inc. | Semiconductor device and manufacturing method thereof |
| US8937381B1 (en) | 2009-12-03 | 2015-01-20 | Amkor Technology, Inc. | Thin stackable package and method |
| US8981572B1 (en) | 2011-11-29 | 2015-03-17 | Amkor Technology, Inc. | Conductive pad on protruding through electrode semiconductor device |
| US9048298B1 (en) | 2012-03-29 | 2015-06-02 | Amkor Technology, Inc. | Backside warpage control structure and fabrication method |
| US9082833B1 (en) | 2011-01-06 | 2015-07-14 | Amkor Technology, Inc. | Through via recessed reveal structure and method |
| US9129943B1 (en) | 2012-03-29 | 2015-09-08 | Amkor Technology, Inc. | Embedded component package and fabrication method |
| US9159672B1 (en) | 2010-08-02 | 2015-10-13 | Amkor Technology, Inc. | Through via connected backside embedded circuit features structure and method |
| US9324614B1 (en) | 2010-04-06 | 2016-04-26 | Amkor Technology, Inc. | Through via nub reveal method and structure |
| US9631481B1 (en) | 2011-01-27 | 2017-04-25 | Amkor Technology, Inc. | Semiconductor device including leadframe with a combination of leads and lands and method |
| US9673122B2 (en) | 2014-05-02 | 2017-06-06 | Amkor Technology, Inc. | Micro lead frame structure having reinforcing portions and method |
| US9691734B1 (en) | 2009-12-07 | 2017-06-27 | Amkor Technology, Inc. | Method of forming a plurality of electronic component packages |
| US9704725B1 (en) | 2012-03-06 | 2017-07-11 | Amkor Technology, Inc. | Semiconductor device with leadframe configured to facilitate reduced burr formation |
-
1989
- 1989-12-05 JP JP31623189A patent/JPH03177060A/en active Pending
Cited By (28)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8154111B2 (en) | 1999-12-16 | 2012-04-10 | Amkor Technology, Inc. | Near chip size semiconductor package |
| US9054117B1 (en) | 2002-11-08 | 2015-06-09 | Amkor Technology, Inc. | Wafer level package and fabrication method |
| US8691632B1 (en) | 2002-11-08 | 2014-04-08 | Amkor Technology, Inc. | Wafer level package and fabrication method |
| US9871015B1 (en) | 2002-11-08 | 2018-01-16 | Amkor Technology, Inc. | Wafer level package and fabrication method |
| US9406645B1 (en) | 2002-11-08 | 2016-08-02 | Amkor Technology, Inc. | Wafer level package and fabrication method |
| US8952522B1 (en) | 2002-11-08 | 2015-02-10 | Amkor Technology, Inc. | Wafer level package and fabrication method |
| US10665567B1 (en) | 2002-11-08 | 2020-05-26 | Amkor Technology, Inc. | Wafer level package and fabrication method |
| US8937381B1 (en) | 2009-12-03 | 2015-01-20 | Amkor Technology, Inc. | Thin stackable package and method |
| US10546833B2 (en) | 2009-12-07 | 2020-01-28 | Amkor Technology, Inc. | Method of forming a plurality of electronic component packages |
| US9691734B1 (en) | 2009-12-07 | 2017-06-27 | Amkor Technology, Inc. | Method of forming a plurality of electronic component packages |
| US9324614B1 (en) | 2010-04-06 | 2016-04-26 | Amkor Technology, Inc. | Through via nub reveal method and structure |
| US9159672B1 (en) | 2010-08-02 | 2015-10-13 | Amkor Technology, Inc. | Through via connected backside embedded circuit features structure and method |
| US8900995B1 (en) | 2010-10-05 | 2014-12-02 | Amkor Technology, Inc. | Semiconductor device and manufacturing method thereof |
| US9082833B1 (en) | 2011-01-06 | 2015-07-14 | Amkor Technology, Inc. | Through via recessed reveal structure and method |
| US9978695B1 (en) | 2011-01-27 | 2018-05-22 | Amkor Technology, Inc. | Semiconductor device including leadframe with a combination of leads and lands and method |
| US9631481B1 (en) | 2011-01-27 | 2017-04-25 | Amkor Technology, Inc. | Semiconductor device including leadframe with a combination of leads and lands and method |
| US8866278B1 (en) | 2011-10-10 | 2014-10-21 | Amkor Technology, Inc. | Semiconductor device with increased I/O configuration |
| US9431323B1 (en) | 2011-11-29 | 2016-08-30 | Amkor Technology, Inc. | Conductive pad on protruding through electrode |
| US9947623B1 (en) | 2011-11-29 | 2018-04-17 | Amkor Technology, Inc. | Semiconductor device comprising a conductive pad on a protruding-through electrode |
| US10410967B1 (en) | 2011-11-29 | 2019-09-10 | Amkor Technology, Inc. | Electronic device comprising a conductive pad on a protruding-through electrode |
| US8981572B1 (en) | 2011-11-29 | 2015-03-17 | Amkor Technology, Inc. | Conductive pad on protruding through electrode semiconductor device |
| US11043458B2 (en) | 2011-11-29 | 2021-06-22 | Amkor Technology Singapore Holding Pte. Ltd. | Method of manufacturing an electronic device comprising a conductive pad on a protruding-through electrode |
| US9704725B1 (en) | 2012-03-06 | 2017-07-11 | Amkor Technology, Inc. | Semiconductor device with leadframe configured to facilitate reduced burr formation |
| US10090228B1 (en) | 2012-03-06 | 2018-10-02 | Amkor Technology, Inc. | Semiconductor device with leadframe configured to facilitate reduced burr formation |
| US9129943B1 (en) | 2012-03-29 | 2015-09-08 | Amkor Technology, Inc. | Embedded component package and fabrication method |
| US10014240B1 (en) | 2012-03-29 | 2018-07-03 | Amkor Technology, Inc. | Embedded component package and fabrication method |
| US9048298B1 (en) | 2012-03-29 | 2015-06-02 | Amkor Technology, Inc. | Backside warpage control structure and fabrication method |
| US9673122B2 (en) | 2014-05-02 | 2017-06-06 | Amkor Technology, Inc. | Micro lead frame structure having reinforcing portions and method |
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