JPS62226649A - Hybrid semiconductor device - Google Patents
Hybrid semiconductor deviceInfo
- Publication number
- JPS62226649A JPS62226649A JP61069948A JP6994886A JPS62226649A JP S62226649 A JPS62226649 A JP S62226649A JP 61069948 A JP61069948 A JP 61069948A JP 6994886 A JP6994886 A JP 6994886A JP S62226649 A JPS62226649 A JP S62226649A
- Authority
- JP
- Japan
- Prior art keywords
- bed
- semiconductor element
- parts
- bonded
- chips
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 60
- 239000011347 resin Substances 0.000 claims description 5
- 229920005989 resin Polymers 0.000 claims description 5
- 238000007789 sealing Methods 0.000 claims description 4
- 239000002184 metal Substances 0.000 claims description 3
- 229910052751 metal Inorganic materials 0.000 claims description 3
- 239000000470 constituent Substances 0.000 claims description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 abstract description 8
- 239000011889 copper foil Substances 0.000 abstract description 8
- 229920001721 polyimide Polymers 0.000 abstract description 5
- 239000009719 polyimide resin Substances 0.000 abstract description 5
- 239000000853 adhesive Substances 0.000 abstract description 4
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 abstract description 3
- 229910052709 silver Inorganic materials 0.000 abstract description 3
- 239000004332 silver Substances 0.000 abstract description 3
- 229920001187 thermosetting polymer Polymers 0.000 abstract description 2
- 229910052737 gold Inorganic materials 0.000 abstract 1
- 229910052759 nickel Inorganic materials 0.000 abstract 1
- 239000000758 substrate Substances 0.000 description 9
- 239000011521 glass Substances 0.000 description 4
- 238000000034 method Methods 0.000 description 4
- 230000001070 adhesive effect Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 239000003822 epoxy resin Substances 0.000 description 3
- 229920000647 polyepoxide Polymers 0.000 description 3
- 238000009413 insulation Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000007747 plating Methods 0.000 description 2
- 238000003825 pressing Methods 0.000 description 2
- 238000005452 bending Methods 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49503—Lead-frames or other flat leads characterised by the die pad
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Abstract
Description
【発明の詳細な説明】
［発明の目的］
（産業上の利用分野）
本発明はハイブリッド型半導体装置に関し、特に、モノ
リシック型半導体装置用のリードフレームを用いて樹脂
封止された構造を有するハイブリッド型半導体装置の改
良に係る。[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) The present invention relates to a hybrid semiconductor device, and in particular, to a hybrid semiconductor device having a resin-sealed structure using a lead frame for a monolithic semiconductor device. Relates to improvement of type semiconductor devices.
（従来の技術）
この種の従来のハイブリッド型半導体装置につき、第４
図〜第６図を参照して説明する。(Prior art) Regarding this type of conventional hybrid semiconductor device, the fourth
This will be explained with reference to FIGS.
第４図はその組立てに用いられるリードフレームの要部
を示す斜視図である。同図において、１はベッド部であ
る。、該ベッド部はタイバー２．２を介して図示しない
リードフレームの外枠に連結されている。また、ベッド
部１の周囲には、一端部がこれを取囲むようにして外部
リード３・・・が配置され、これら外部リードの他端部
は前記図示しないフレーム外枠に連結されている。上記
のように、このリードフレームはモノリシック型の半導
体装置に用いられているのと同じものであり、導電性金
属板をプレス工程または蝕刻工程によって製造されたも
のである。FIG. 4 is a perspective view showing the main parts of the lead frame used for the assembly. In the figure, 1 is a bed section. , the bed portion is connected to the outer frame of a lead frame (not shown) via tie bars 2.2. Further, external leads 3 are arranged around the bed portion 1 so that one end thereof surrounds it, and the other end of these external leads is connected to the frame outer frame (not shown). As mentioned above, this lead frame is the same as that used in monolithic semiconductor devices, and is manufactured by pressing or etching a conductive metal plate.
上記リードフレームを用いてハイブリッド型半導体￥Ｒ
Ｉを製造するには、第５図に示１ようにベッド部１の表
面を絶縁膜４で被覆する。該絶縁膜４には、半導体素子
チップをマウントすべき位置に夫々の半導体素子チップ
より少し大きい開孔部が複数形成され、この開孔部でベ
ッド部表面を露出させて素子マウント部が形成されてい
る。これら素子マ・クン１一部には、夫々対応する半導
体素子チップ１０１〜１０３を銀ペーストによりダイボ
ンディングする。更に、絶縁膜４上には銅箔パターン５
・・・が形成されており、前記半導体素子チップ１０１
〜１０３をマウントした後に所定のワイヤボンディング
６・・・を施こす。Hybrid semiconductor using the above lead frame
To manufacture I, the surface of the bed portion 1 is coated with an insulating film 4 as shown in FIG. A plurality of openings slightly larger than each semiconductor element chip are formed in the insulating film 4 at positions where the semiconductor element chips are to be mounted, and the surface of the bed part is exposed through the openings to form an element mounting part. ing. Corresponding semiconductor element chips 101 to 103 are die-bonded to some of these element elements 1 using silver paste. Furthermore, a copper foil pattern 5 is formed on the insulating film 4.
... is formed, and the semiconductor element chip 101
After mounting ~103, predetermined wire bonding 6... is performed.
上記の組立てが終了した後、エボキス樹脂のトランスフ
ァーモールド等により所定領域を封止する樹脂層７を形
成することにより、第６図に示す構造をもった自動実装
可能なハイブリッド型半導体装置が製造される。なお、
第６図は樹脂封止した状態において、これを第５図Ｖｌ
−Ｖｌ線に沿った断面で示す図である。After the above assembly is completed, a resin layer 7 that seals a predetermined area is formed using an epoxy resin transfer mold, etc., thereby producing an automatically mountable hybrid semiconductor device having the structure shown in FIG. Ru. In addition,
Figure 6 shows this in a resin-sealed state.
It is a diagram shown in a cross section along the -Vl line.
（発明が解決しようとする問題点）
上記のように、従来のハイブリッド型半導体装置つでは
、単一のベッド部１上に複数の半導体素子チップ１０１
〜１０３を直接マウントしている。そのため、ＩＣチッ
プ１０１がベッド部１からアース電極を取出す構造であ
る場合、他の半導体素子チップ１０２．１０３として、
例えばＬＥＤやダイオード等のように同じくチップの裏
面から電極を取出す基板電極構造のものを搭載すること
はできない。このため、従来のハイブリッド型半導体装
置には一緒に搭載可能な半導体チップの種類に大きな制
限を受ける問題がある。(Problems to be Solved by the Invention) As described above, in a conventional hybrid semiconductor device, a plurality of semiconductor element chips 101 are placed on a single bed portion 1.
~103 is mounted directly. Therefore, if the IC chip 101 has a structure in which the ground electrode is taken out from the bed part 1, as other semiconductor element chips 102 and 103,
For example, it is not possible to mount devices such as LEDs and diodes that have a substrate electrode structure in which the electrodes are taken out from the back side of the chip. For this reason, conventional hybrid semiconductor devices have the problem of being severely restricted in the types of semiconductor chips that can be mounted together.
そこで、本発明は現在の構造を大きく変えることなく、
どのような種類からなるチップの組合せでも搭載可能な
ハイブリッド型半導体装置を課題とする。Therefore, the present invention does not significantly change the current structure,
The objective is to develop a hybrid semiconductor device that can be equipped with any combination of chips of any type.
［発明の構成］
（問題点を解決するための手段）
上記の課題を達成するために、本発明では従来のハイブ
リッド型半導体装置におけるベッド部を相互に絶縁され
た複数の部分に分割し、チップ裏面から電極を取出す基
板電極構造をもった半導体素子チップは、前記ベッド部
の夫々賃なる分割部分にダイボンディングすることとし
た。[Structure of the Invention] (Means for Solving the Problems) In order to achieve the above-mentioned problems, the present invention divides the bed portion of a conventional hybrid semiconductor device into a plurality of mutually insulated parts, and Semiconductor element chips having a substrate electrode structure in which electrodes are taken out from the back surface are die-bonded to respective divided portions of the bed portion.
即ち、本発明によるハイブリッド型半導体装置は、導電
性金属板からなるベッド部と、該ベッド部の表面を被覆
する絶縁シートと、該絶縁シートを選択的に除去するこ
とにより前記ベッド部表面を露出させて形成された複数
の素子マウント部と、これら素子マウント部に夫々ダイ
ボンディングされた半導体素子チップと、前記絶縁シー
トの表面に形成された導電性パターンと、前記ベッド部
の周囲を不連続状態で囲む外部リードと、全体として所
期の回路が構成され且つ該回路の端子が前記外部リード
に取出されるように、前記半導体素子チップ表面に形成
されているポンディングパッド、前記導電性パターン及
び前記外部リードの間を接続するボンディングワイヤと
、前記外部リードの非ボンディング端が外部に延出され
るように上記構成部分の全部を封止する樹脂層とを具備
だハイブリッド型半導体装置において、前記ベッド部を
相互に絶縁された複数部分に分割し、前記半導体素子チ
ップのうちその裏面からベッド部を通して電極を取出す
ものについては、前記ベッド部の異なる分割部分に設け
た前記素子マウント部にダイボンディングされているこ
とを特徴とするものである。That is, the hybrid semiconductor device according to the present invention includes a bed portion made of a conductive metal plate, an insulating sheet covering the surface of the bed portion, and a surface of the bed portion exposed by selectively removing the insulating sheet. A discontinuous state is formed around the plurality of element mount parts, the semiconductor element chips die-bonded to these element mount parts, the conductive pattern formed on the surface of the insulating sheet, and the bed part. an external lead surrounded by a bonding pad formed on the surface of the semiconductor element chip, the conductive pattern and In the hybrid semiconductor device comprising a bonding wire connecting between the external leads and a resin layer sealing all of the constituent parts so that the non-bonding ends of the external leads extend outside, the bed In the case where the semiconductor element chip is divided into a plurality of mutually insulated parts and electrodes are taken out from the back side of the semiconductor element chip through the bed part, die bonding is performed to the element mount parts provided in different divided parts of the bed part. It is characterized by the fact that
本発明においては、前記導電性パターンの上にも、チッ
プ裏面から電極を取出す基板電極構造をもった他の半導
体素子チップをマウントシてもよい。In the present invention, another semiconductor element chip having a substrate electrode structure in which electrodes are taken out from the back surface of the chip may be mounted on the conductive pattern as well.
（作用）
上記のように、本発明のハイブリッド型半導体装置では
、チップ裏面から電極を取出す構造の半導体素子チップ
は、夫々ベッド部の相互に絶縁されている異なった分割
部分にダイボンディングされているから、これらの半導
体素子チップについて夫々基板電挽構造を採用しても他
の半導体素子チップに何等の影響も生じない。(Function) As described above, in the hybrid semiconductor device of the present invention, the semiconductor element chips having a structure in which the electrodes are taken out from the back side of the chips are die-bonded to different mutually insulated divided portions of the bed portion. Therefore, even if the substrate electrically ground structure is adopted for each of these semiconductor element chips, there will be no effect on other semiconductor element chips.
従って、従来のように搭載できる半導体素子チップの種
類が制限されることはなくなる。Therefore, the types of semiconductor element chips that can be mounted are no longer limited as in the past.
（実施例〉
以下、本発明の一実施例になるハイブリッド型半導体装
置につぎ、その製造工程に沿って説明するく第１図〜第
３図）。(Example) Hereinafter, a hybrid semiconductor device according to an example of the present invention will be described along with its manufacturing process (FIGS. 1 to 3).
この実施例では、第１図に示すリードフレームを用いる
。同図に示すように、このリードフレームはベッド部１
が二つの部分１１．１２に分割分離され、この分割部分
は夫々タイバー２ｒ 、 ２２を介して図示しないフレ
ーム外枠に連結されている。３・・・は外部リードで、
これは第４図の従来のリードフレームにおけると同じで
ある。In this embodiment, a lead frame shown in FIG. 1 is used. As shown in the figure, this lead frame has a bed section 1.
is divided into two parts 11 and 12, and these divided parts are connected to an outer frame (not shown) via tie bars 2r and 22, respectively. 3... is an external lead,
This is the same as in the conventional lead frame shown in FIG.
一方、ポリイミド樹脂フィルム、或いはガラスエポキシ
樹脂やガラスポリイミド樹脂のプリプレグフィルム等か
らなる絶縁１１４の表面に銅箔を被着する。その被着方
法は適用材質により相違し、ポリイミド樹脂フィルムの
場合には接着剤によるが、ガラスポリイミド樹脂やガラ
スエポキシ樹脂のプリプレグフルムの場合には、それ自
身が保有する接着機能を利用して被着する。続いて、こ
の銅箔に写真蝕刻を施すことにより所望の配列をもつ銅
箔パターン５を形成し、更にＮｉメッキ、ＡＩＪメッキ
をこの順序で行なう。次いで、絶縁膜４にプレス工程を
施し、各半導体素子チップのマウント部に対応した位置
に複数の開孔部を形成する。On the other hand, copper foil is applied to the surface of the insulation 114 made of polyimide resin film, glass epoxy resin, glass polyimide resin prepreg film, or the like. The method of adhesion differs depending on the material to which it is applied; in the case of polyimide resin film, an adhesive is used, but in the case of prepreg film made of glass polyimide resin or glass epoxy resin, it is applied using its own adhesive function. wear. Subsequently, this copper foil is photo-etched to form a copper foil pattern 5 having a desired arrangement, and further Ni plating and AIJ plating are performed in this order. Next, the insulating film 4 is subjected to a pressing process to form a plurality of openings at positions corresponding to the mounting parts of each semiconductor element chip.
上記のように加工された絶縁［１４を、第１図のリード
フレームにおけるベッド部１１．１２の表面に熱硬化性
接着剤を介して積層接着し、その開孔部に露出したベッ
ド部表面に各半導体素子チップ１０１〜１０３を銀ペー
ストでダイボンディングする。その後、必要なワイヤボ
ンディングを行なって第２図の状態を得る。図中６はボ
ンディングワイヤで、これらボンディングワイヤ６・・
・を介した接続により、初期の回路が構成されている。The insulation [14 processed as described above is laminated and bonded to the surface of the bed portions 11 and 12 in the lead frame shown in FIG. 1 via a thermosetting adhesive, and Each semiconductor element chip 101 to 103 is die-bonded using silver paste. Thereafter, necessary wire bonding is performed to obtain the state shown in FIG. In the figure, 6 is a bonding wire, and these bonding wires 6...
The initial circuit was constructed by connections via .
その後、従来例の場合と同じようにして樹脂封止を行な
い、リードカッティング及びリードベンディングを施し
て第３図に示すハイブリッド型半導体装置を得る。同図
は第２図ｍ−■線に対応した位置での断面図であり、図
中７は封止樹脂層である。Thereafter, resin sealing is performed in the same manner as in the conventional example, and lead cutting and lead bending are performed to obtain the hybrid semiconductor device shown in FIG. This figure is a sectional view taken at a position corresponding to the line m--■ in FIG. 2, and 7 in the figure is a sealing resin layer.
上記実施例のハイブリッド型半導体装置において、半導
体素子チップ１０１．１０３は分割ベッド部１２上にダ
イボンディングされ、半導体素子チップ１０２は分割ベ
ッド部１１にグイボネイングされている。従って、半導
体素子デツプ１０１が基板電極構造のＩＣチップで、半
導体素子チップ１０２が基板電極構造のダイオードであ
ったとしても、両者−がダイボンディングされている分
割ベッド部が相互に絶縁されているから両画は相互に干
渉せず、何等問題を生じることなく共存し得る。In the hybrid semiconductor device of the above embodiment, the semiconductor element chips 101 and 103 are die-bonded onto the divided bed section 12, and the semiconductor element chip 102 is bonded onto the divided bed section 11. Therefore, even if the semiconductor element depth 101 is an IC chip with a substrate electrode structure and the semiconductor element chip 102 is a diode with a substrate electrode structure, the divided bed portions to which both are die-bonded are insulated from each other. Both images do not interfere with each other and can coexist without causing any problems.
なお上記の場合、半導体素子チップ１０３はＩＧチップ
１０１と同一の分割ベッド部１２にマウントされている
ため、基板電極構造のものを用いることはできない。し
かし、半導体素子チップ１０３用に独立したを銅箔パタ
ーン５を形成し、その上にマウントするようにすれば、
チップ１０３にもＬＥＤチップのような基板電極構造の
ものを用いることかできる。Note that in the above case, since the semiconductor element chip 103 is mounted on the same divided bed portion 12 as the IG chip 101, a substrate electrode structure cannot be used. However, if a separate copper foil pattern 5 is formed for the semiconductor element chip 103 and mounted on it,
The chip 103 may also have a substrate electrode structure such as an LED chip.
［発明の効果］
以上詳述したように、本発明のハイブリッド型半導体装
置によれば、ＬＥＤやディスクリ−１−型トランジスタ
のようにチップ裏面から電極を取出す構造の素子を、同
様の基板置市構造をもったＩＣチップと一緒に組込むこ
とができるので、従来のハイブリッド型半導体装置に比
べて大幅に製品範囲を広げることができる等、顕著な効
果が得られるものである。[Effects of the Invention] As described in detail above, according to the hybrid semiconductor device of the present invention, elements such as LEDs and discrete 1-type transistors, whose electrodes are taken out from the back surface of the chip, can be mounted on a similar substrate. Since it can be incorporated together with an IC chip having an integrated circuit structure, the product range can be greatly expanded compared to conventional hybrid semiconductor devices, and other remarkable effects can be obtained.
第１図〜第３図は本発明の一実施例になるハイブリッド
型半導体装置をその組立て工程に冶って示す説明図、第
４図〜第６図は従来のハイブリッド型半導体装置をその
組立て工程に沿って示す説明図である。1 to 3 are explanatory diagrams showing the assembly process of a hybrid semiconductor device according to an embodiment of the present invention, and FIGS. 4 to 6 are explanatory diagrams showing the assembly process of a conventional hybrid semiconductor device. FIG.
Claims (2)
表面を被覆する絶縁シートと、該絶縁シートを選択的に
除去することにより前記ベッド部表面を露出させて形成
された複数の素子マウント部と、これら素子マウント部
に夫々ダイボンデイングされた半導体素子チップと、前
記絶縁シートの表面に形成された導電性パターンと、前
記ベツド部の周囲を不連続状態で囲む外部リードと、全
体として所期の回路が構成され且つ該回路の端子が前記
外部リードに取出されるように、前記半導体素子チップ
表面に形成されているボンディングパッド、前記導電性
パターン及び前記外部リードの間を接続するボンディン
グワイヤと、前記外部リードの非ボンディング端が外部
に延出されるように上記構成部分の全部を封止する樹脂
層とを具備たハイブリッド型半導体装置において、前記
ベッド部を相互に絶縁された複数部分に分割し、前記半
導体素子チツプのうちその裏面からベッド部を通して電
極を取出すものについては、前記ベッド部の異なる分割
部分に設けた前記素子マウント部にダイボンデイングさ
れていることを特徴とするハイブリッド型半導体装置。(1) A bed portion made of a conductive metal plate, an insulating sheet covering the surface of the bed portion, and a plurality of elements formed by selectively removing the insulating sheet to expose the surface of the bed portion. A mount part, semiconductor element chips die-bonded to each of these element mount parts, a conductive pattern formed on the surface of the insulating sheet, an external lead discontinuously surrounding the bed part, and as a whole. bonding for connecting between a bonding pad formed on the surface of the semiconductor element chip, the conductive pattern, and the external lead so that a desired circuit is configured and a terminal of the circuit is taken out to the external lead; In a hybrid semiconductor device comprising a wire and a resin layer sealing all of the constituent parts so that the non-bonding ends of the external leads extend outside, the bed part is a plurality of mutually insulated parts. A hybrid type characterized in that the semiconductor element chip is divided into two parts, and the electrodes are taken out from the back side of the semiconductor element chip through the bed part, and the semiconductor element chip is die-bonded to the element mount parts provided in different divided parts of the bed part. Semiconductor equipment.
導体回路部品を、前記導電性パターン上にマウントした
ことを特徴とする特許請求の範囲第（１）項記載のハイ
ブリッド型半導体装置。(2) The hybrid semiconductor device according to claim (1), wherein a semiconductor element chip or a semiconductor circuit component from which electrodes are taken out from the back surface is mounted on the conductive pattern.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61069948A JPS62226649A (en) | 1986-03-28 | 1986-03-28 | Hybrid semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61069948A JPS62226649A (en) | 1986-03-28 | 1986-03-28 | Hybrid semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62226649A true JPS62226649A (en) | 1987-10-05 |
Family
ID=13417386
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61069948A Pending JPS62226649A (en) | 1986-03-28 | 1986-03-28 | Hybrid semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62226649A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0338867A (en) * | 1989-07-05 | 1991-02-19 | Nec Corp | Hybrid integrated circuit device |
| JPH03163858A (en) * | 1989-08-25 | 1991-07-15 | Toshiba Corp | Resin-sealed semiconductor device |
| US6347230B2 (en) | 1995-07-25 | 2002-02-12 | Ace K Computer Co., Ltd. | Position display system of mobile terminal |
| JP2009253153A (en) * | 2008-04-09 | 2009-10-29 | Asmo Co Ltd | Resin seal type semiconductor device |
-
1986
- 1986-03-28 JP JP61069948A patent/JPS62226649A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0338867A (en) * | 1989-07-05 | 1991-02-19 | Nec Corp | Hybrid integrated circuit device |
| JPH03163858A (en) * | 1989-08-25 | 1991-07-15 | Toshiba Corp | Resin-sealed semiconductor device |
| US6347230B2 (en) | 1995-07-25 | 2002-02-12 | Ace K Computer Co., Ltd. | Position display system of mobile terminal |
| US6349211B2 (en) | 1995-07-25 | 2002-02-19 | Ace K Computer Co., Ltd. | Position display system of mobile terminal |
| JP2009253153A (en) * | 2008-04-09 | 2009-10-29 | Asmo Co Ltd | Resin seal type semiconductor device |
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