JPS58178544A - Lead frame - Google Patents

Lead frame

Info

Publication number
JPS58178544A
JPS58178544A JP6147682A JP6147682A JPS58178544A JP S58178544 A JPS58178544 A JP S58178544A JP 6147682 A JP6147682 A JP 6147682A JP 6147682 A JP6147682 A JP 6147682A JP S58178544 A JPS58178544 A JP S58178544A
Authority
JP
Japan
Prior art keywords
flexible insulating
insulating plate
wirings
plate
lead frame
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP6147682A
Other languages
Japanese (ja)
Other versions
JPH0517709B2 (en
Inventor
Sekiya Marutsuka
丸塚 碩也
Ryosuke Hosobane
細羽 良弼
Eiichi Tsunashima
瑛一 綱島
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electronics Corp
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electronics Corp, Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electronics Corp
Priority to JP6147682A priority Critical patent/JPS58178544A/en
Publication of JPS58178544A publication Critical patent/JPS58178544A/en
Publication of JPH0517709B2 publication Critical patent/JPH0517709B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495Lead-frames or other flat leads
    • H01L23/49517Additional leads
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE:To obtain a lead frame which can be mounted in a high density by forming with conductive foils when forming circuit element placing parts, mutual wirings and external lead wirings on both front and back surfaces of a flexible insulating plate, opening through holes capable of flowing sealing resin at the plate, and mutually connecting the foils through the holes. CONSTITUTION:A desired mask pattern is formed by a photoetching method in a dual in-line type lead frame by employing as a flexible insulating plate 10 to make a substrate a polyimide film, bonding conductive foils on front and back surfaces. In other words, semiconductor chip plating parts 1, 2, 3, internal mutual wirings 4, 5, external lead wirings 6, 7 and frame 16 are formed on the front and back surfaces of the plate 10. Then, through holes 8, 9 capable of flowing sealing resin are opened at the prescribed positions of the foils of the plate 10, and necessary mutual wirings are formed of fine metal wires. In this manner, an integrated circuit may be contained in a sole sealed enclosure, thereby improving the integration.

Description

【発明の詳細な説明】 本発明は可撓性絶縁板上に導電箔体を配設した構造のリ
ードフレームに関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a lead frame having a structure in which a conductive foil is disposed on a flexible insulating plate.

半導体装置用のリードフレームは、通常、金属板を打ち
抜き加工して一体形成したものが実用されている。この
種のリードフレームでは、複数個の半導体チップを各独
立に載置する場合、同載置部を外部導出線から浮かせた
状態で設けることが困難であるため、これを支持する余
分な外部導出線を必要とし、形状が大きくな・)たり、
あるいは独立の半導体チップや回路要素の内蔵に限度が
あるという難点を有する。
2. Description of the Related Art Lead frames for semiconductor devices are generally formed by punching a metal plate into one piece. With this type of lead frame, when multiple semiconductor chips are mounted independently, it is difficult to set up the mounting part in a state that is lifted from the external lead-out wire, so an extra external lead-out wire is required to support it. Requires lines and the shape is large.)
Another problem is that there is a limit to how many independent semiconductor chips or circuit elements can be incorporated.

一方、半導体集積回路の実装に際し、可撓性絶縁板上に
配設した多数の金属箔リードの先端を半導体チップの所
定の接続部にボンディングする方式が用いられることも
、いわゆるフィルムキャリア方式として、広く知られて
いる。しかるに、かかるフィルムキャリア方式では、フ
ィンガリードと称される前記金属箔リードと半導体チッ
プ−トの多数のポンディングパッド部とを一度のボンデ
ィング工程で形成し得る利点はあるが、複数個の半導体
チップを独立に塔載したり、あるいは、半導体チップと
他の回路要素を複合して塔載する混成集積回路の場合に
は、半導体チップ側、回路要素側のそれぞれの接続部に
バンプ(突起電極)と呼ばれる個有の加工を施こす必要
があり、従来からの組立技術であるダイボンディング、
ワイヤボンディングの技術との融合性に難点がある。
On the other hand, when mounting semiconductor integrated circuits, a method is used in which the tips of a large number of metal foil leads arranged on a flexible insulating board are bonded to predetermined connection parts of the semiconductor chip, also known as the so-called film carrier method. widely known. However, although this film carrier method has the advantage that the metal foil leads called finger leads and a large number of bonding pad portions of a semiconductor chip can be formed in a single bonding process, In the case of a hybrid integrated circuit in which a semiconductor chip and other circuit elements are mounted independently or in combination with a semiconductor chip and other circuit elements, bumps (protruding electrodes) are placed at the connection points on the semiconductor chip side and the circuit element side. It is necessary to perform a unique processing called die bonding, which is a traditional assembly technology.
There is a problem with compatibility with wire bonding technology.

本発明は、従来の金属板リードフレームあるいはフィル
ムキャリア方式にみられた上述の問題点を一挙に解消す
るものである。すなわち、本発明は可撓性絶縁板上に1
回路要素体の載置部、相q配線部および外部導出線要部
を導電箔体で形成したリードフレームを提供するもので
ある。
The present invention solves all of the above-mentioned problems found in conventional metal plate lead frame or film carrier systems. That is, in the present invention, one
The present invention provides a lead frame in which a mounting part for a circuit element body, a phase and q wiring part, and a main part of an external lead-out line are formed of a conductive foil body.

次に図面を用いて本発明の詳細な説明する。Next, the present invention will be explained in detail using the drawings.

第1図は本発明の一実施例で、デュアルインライン(D
IL)型リードフレームの平面図である。
FIG. 1 shows an embodiment of the present invention, in which dual in-line (D
FIG. 3 is a plan view of an IL) type lead frame.

同図において、1,2.3は、たとえば半導体チップ、
あるいは受動回路素子よりなる回路要素体の載置部、4
,6は内部の相互配線部、6.7は外部導出線部、小孔
8,9はスルーホール、1゜は可撓性絶縁板、11.1
2.13は可撓性絶縁板10に設けられた開孔部であり
、さらに、14.16は組立工程で使用する送り孔、1
6は枠部である。可撓性絶縁板1oは、たとえばポリイ
ミドフィルムが好適に用いられ、この可撓性絶縁板1o
上に導電箔体として銅箔を張り付けて層板になし、この
銅箔部を所望のマスクパターンに写真食刻技法で加工し
、回路要素体の載置部1.2゜β、相互配線部4.6、
外部導出線部6.7および枠部16を残置させたリード
フレーム構体を形成する。かかる導電箔体は可撓性絶縁
板1oの両面に設けられ、これら両面の導電箔体間が1
q路構成上の必要性に応じて、スルーホール8.9を通
じて導電接続される。なお、外部導出線部6.7は強度
維持と外部接続を良好にするために可撓性絶縁板10を
はさむ両面に設けられ、互いにスルーホール9で導電結
合される。このリードフレームを用いて集積回路を構成
するには、先ず、回路要素体の載置部1,2.3にそれ
ぞれ所定の集゛積回路半導体チップ、抵抗、コンデンサ
等の受動回路素子を選定して載置し、これら各回路要素
体の−各電極部を各外部導出m6.7の力先端部および
所定の相互配線部4.5にそれぞれ周知のワイヤボンデ
ィング技術で金属細線接続する。唾だ、集積回路構成に
抵抗、コンデンサなどの受動回路要素が載置部の個数を
こえて必要であれば、これらの回路要素を、外部導出線
部6.7、相互配線部4.6のいずれかを選択して、は
んだ付けで接続し、各配線部間の接続を要する場合には
金属細線によるワイヤボンディングを行なって充当する
こともできる。相互配線部4.5は、可撓性絶縁板1o
に張り付けられているから、外部導出線部6゜7とは分
離されて、いわゆる浮遊状態で配設されており、混成集
積回路構成の内部結線に有用であり、回路要素の高密度
実装が可能であるのみならず、ワイヤボンディングの際
の中継配線部として用いることにより、金属細線接続の
交錯化を避けることが可能になる。つぎに、集積回路構
成の結線を完了したものは樹脂封止成型により外囲体を
形成するが、このとき、可撓性絶縁板1oに開孔11.
12を設けたことにより、樹脂がこれらの開孔部に流入
して、同可撓性絶縁板1oの両面を包み込む。この結果
、樹脂封止外囲体が集積回路部を確実に内封するととも
に、可撓性絶縁板1゜の両面を覆う際の結合性もよくな
り、外囲体の強度も向上する。なお、樹脂対Iト外囲体
の封止側面は可撓性絶縁板1oの開孔11,12の中央
部を結ぶ鎖線の位置、いわゆる樹脂モールドライン(第
1図中の鎖線)17に配される。
In the figure, 1, 2.3 are, for example, semiconductor chips,
Or a mounting part for a circuit element body consisting of a passive circuit element, 4
, 6 is an internal interconnection part, 6.7 is an external lead-out wire part, small holes 8 and 9 are through holes, 1° is a flexible insulating plate, 11.1
2.13 is an opening provided in the flexible insulating plate 10, and 14.16 is a feed hole used in the assembly process;
6 is a frame portion. For example, a polyimide film is suitably used for the flexible insulating plate 1o.
Copper foil is pasted on top as a conductive foil to form a layered plate, and this copper foil is processed into a desired mask pattern using a photo-etching technique. 4.6,
A lead frame structure is formed in which the external lead wire portion 6.7 and the frame portion 16 remain. Such conductive foil bodies are provided on both sides of the flexible insulating plate 1o, and the distance between the conductive foil bodies on both sides is 1.
Conductive connections are made through through-holes 8.9, depending on the requirements of the q-way configuration. Note that the external lead wire portions 6.7 are provided on both sides sandwiching the flexible insulating plate 10 in order to maintain strength and improve external connection, and are conductively coupled to each other through the through hole 9. To construct an integrated circuit using this lead frame, first select passive circuit elements such as a predetermined integrated circuit semiconductor chip, a resistor, and a capacitor for each of the mounting parts 1, 2, and 3 of the circuit element body. The electrodes of each of these circuit elements are connected to the force tip of each external lead-out m6.7 and a predetermined interconnection part 4.5 using thin metal wires using a well-known wire bonding technique. If the integrated circuit configuration requires passive circuit elements such as resistors and capacitors in excess of the number of mounting parts, these circuit elements can be placed in the external wiring part 6.7 and interconnection part 4.6. Either one can be selected and connected by soldering, and if connection between each wiring part is required, wire bonding using thin metal wires can also be used. The mutual wiring section 4.5 is a flexible insulating plate 1o.
Since it is attached to the external lead wire section 6゜7, it is placed in a so-called floating state, which is useful for internal wiring of a hybrid integrated circuit configuration, and enables high-density mounting of circuit elements. Not only this, but also by using it as a relay wiring part during wire bonding, it is possible to avoid intermingling of thin metal wire connections. Next, after completing the wiring connections of the integrated circuit configuration, an outer envelope is formed by resin sealing molding. At this time, the openings 11.
12, the resin flows into these openings and wraps both sides of the flexible insulating plate 1o. As a result, the resin-sealed envelope reliably encapsulates the integrated circuit portion, and also improves the bonding properties when covering both sides of the flexible insulating plate 1°, and improves the strength of the envelope. The sealing side surface of the outer envelope of the resin pair I is placed at the position of the chain line connecting the centers of the openings 11 and 12 of the flexible insulating plate 1o, the so-called resin mold line (dashed line in FIG. 1) 17. be done.

第1図のリードフレームは、実際の集積回路組立工程で
は、第2図に示されるように、多数個を連結した形状で
使用され、また、これを半導体チップや回路要素の載置
工程、ワイヤボンディング工程ならびに樹脂対f1一工
程における自動送り装置に適合させるために、送り孔1
4.15が利用される。そして、最終工程で、枠部16
が切り離されて、第3図に示すような半導体集積回路チ
ップを含むDIL型混成集積回路単体として完成される
。第3図示のDIL型混成集積回路装置は、゛それの外
部導出線部6.7を用いて、応用機器に直接はんだ付け
するか、あるいはコネクタ類で連結して使用することが
できる。とくに、第3図でもわかるように、外部導出線
部6.7はその樹脂外囲体18の側で、拡幅部が可撓性
絶縁板1oによって一体的に張り合わせられているから
、その外側先端をコネクタ類に挿し込む作業にも十分に
耐える機械的強度を有している。
The lead frame shown in Figure 1 is used in the actual integrated circuit assembly process in the form of a large number of connected pieces, as shown in Figure 2. In order to adapt to the bonding process and the automatic feeding device in the resin pair f1 process, the feed hole 1
4.15 is used. Then, in the final process, the frame portion 16
is separated to complete a single DIL type hybrid integrated circuit including a semiconductor integrated circuit chip as shown in FIG. The DIL type hybrid integrated circuit device shown in FIG. 3 can be used by directly soldering it to applied equipment using its external lead wire portion 6.7, or by connecting it with connectors. In particular, as can be seen in FIG. 3, the widened portion of the external lead wire portion 6.7 is integrally bonded to the resin envelope 18 side by the flexible insulating plate 1o, so that the outer tip of the external lead wire portion 6.7 is It has sufficient mechanical strength to withstand the work of inserting it into connectors.

本発明は、第1図〜第3図の実施例で示したDIL型集
積回路装置に限らず、7ングルインライン(SIL)型
、フラットパッケージ型の集積回路装置に対しても適用
可能であり、さらには任意の外囲体形状および外部導出
線部形状のものにも適用され、実質上、可撓性絶縁板−
ヒに、回路要素体の載置部、相互配線部および外部導出
線要部を導電箔体で形成して構成されたものである。本
発明のリードフレームには、導電箔体が可撓性絶縁板の
両面上にあって、互いにスルーホールで導電接続された
もの、可撓性絶縁板上に導電箔体よりなる回路要素体の
載置部を複数に有するもの、可撓性絶縁板の一部に成型
用樹脂の流通可能な開孔を有するものが、それぞれ、実
施態様として例示される。
The present invention is applicable not only to the DIL type integrated circuit device shown in the embodiments of FIGS. 1 to 3, but also to 7-in-line (SIL) type and flat package type integrated circuit devices. Furthermore, it can be applied to any shape of the outer envelope and the shape of the external lead-out wire, and is essentially a flexible insulating plate.
Furthermore, the mounting portion for the circuit element body, the mutual wiring portion, and the main portions of the external lead-out lines are formed of conductive foil. The lead frame of the present invention includes one in which conductive foil bodies are on both sides of a flexible insulating plate and conductively connected to each other through through holes, and a circuit element body made of conductive foil bodies on a flexible insulating plate. Examples of embodiments include one having a plurality of placing parts and one having an opening in a part of the flexible insulating plate through which molding resin can flow.

本発明によれば、可撓性絶縁板上に導電箔体で々る回路
要素体の載置部、相互配線部および外部導出線部を有す
るから、集積回路要素としての半導体チップ、各種の受
動回路要素をそれぞれ内部結線して、単一封止外囲体内
に収納でき、高密度実装を達成することができる。加え
て、本発明によれば、ダイボンディング、ワイヤボンデ
ィングなどの組立技術や、トランスフプモールド樹脂成
型封止も可能であり、従来からの集積回路構成に用いら
れる慣用技術との融合性にもすぐれたリードフレームが
実現されるので、本発明のリードフレームの工業的価値
は大きいものである。
According to the present invention, since the flexible insulating plate has a mounting part for a circuit element body made of conductive foil, an interconnection part, and an external lead-out line part, semiconductor chips as integrated circuit elements, various passive Each circuit element can be internally wired and housed within a single encapsulated envelope to achieve high density packaging. In addition, according to the present invention, assembly techniques such as die bonding and wire bonding, as well as transfer mold resin molding and sealing are also possible, and it has excellent compatibility with conventional techniques used in conventional integrated circuit configurations. Therefore, the lead frame of the present invention has great industrial value.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の実施例のリードフレームの平面斡拡大
図、第2図は本発明の実施例に係るリードフレームの連
結体を示す図、第3図は本発明の実施例による集積回路
装置実装体の斜視図である。 1.2.3・・・・・・回路要素体の載置部、4.6・
・・・・・相互配線部、6.7・・・・・・外部導出線
部、8.9・・・・・スルーホール、10・・・・・・
可撓性絶m板、11゜12.13・・・・・・開孔部、
14.15・・・・・・送り孔、16・・・・・・枠部
、17・・・・・・樹脂封止側面、18・・・・・・樹
脂外囲体。 代理人の氏名 弁理士 中 尾 敏 男 ほか1名第1
図 第2図
FIG. 1 is an enlarged plan view of a lead frame according to an embodiment of the present invention, FIG. 2 is a diagram showing a connected body of lead frames according to an embodiment of the present invention, and FIG. 3 is an integrated circuit according to an embodiment of the present invention. FIG. 3 is a perspective view of the device mounting body. 1.2.3... Placement section for circuit element body, 4.6.
...... Mutual wiring section, 6.7... External lead-out line section, 8.9... Through hole, 10...
Flexible absolute plate, 11° 12.13... Opening part,
14.15... Feed hole, 16... Frame, 17... Resin sealed side surface, 18... Resin envelope. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 1
Figure 2

Claims (1)

【特許請求の範囲】 (1)可撓性絶縁板上に、回路要素体の載置部、相互配
線部および外部導出線要部p′導電箔体で形成されてい
ることを特徴とするリードフレーム。 し)導電箔体が可撓性絶縁板の両面上に形成されており
、前記導電箔体が互いにスルーホールで導電接続されて
いることを特徴とする特許請求の範囲第1項に記載のリ
ードフレーム。 図 回路要素体の載置部を複数有することを特徴とする
特許請求の範囲第1項に記載の1ノードフレーム。 (4)可撓性絶縁板に封止用樹脂の流通可能な開孔を有
することを特徴とする特許請求の範囲第1項に記載のリ
ードフレーム。
[Scope of Claims] (1) A lead characterized in that it is formed of a circuit element mounting part, an interconnecting wiring part, and an external lead-out line main part p' conductive foil body on a flexible insulating plate. flame. (b) A lead according to claim 1, wherein conductive foil bodies are formed on both sides of the flexible insulating plate, and the conductive foil bodies are electrically connected to each other through through holes. flame. The one-node frame according to claim 1, characterized in that it has a plurality of mounting parts for circuit element bodies. (4) The lead frame according to claim 1, wherein the flexible insulating plate has an opening through which a sealing resin can flow.
JP6147682A 1982-04-12 1982-04-12 Lead frame Granted JPS58178544A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6147682A JPS58178544A (en) 1982-04-12 1982-04-12 Lead frame

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6147682A JPS58178544A (en) 1982-04-12 1982-04-12 Lead frame

Publications (2)

Publication Number Publication Date
JPS58178544A true JPS58178544A (en) 1983-10-19
JPH0517709B2 JPH0517709B2 (en) 1993-03-09

Family

ID=13172148

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6147682A Granted JPS58178544A (en) 1982-04-12 1982-04-12 Lead frame

Country Status (1)

Country Link
JP (1) JPS58178544A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4721994A (en) * 1985-06-25 1988-01-26 Toray Silicone Co., Ltd. Lead frame for semiconductor devices
US5075760A (en) * 1988-01-18 1991-12-24 Texas Instruments Incorporated Semiconductor device package assembly employing flexible tape
US5084753A (en) * 1989-01-23 1992-01-28 Analog Devices, Inc. Packaging for multiple chips on a single leadframe
JPH0514516Y2 (en) * 1988-10-28 1993-04-19
US6897092B2 (en) 1999-09-03 2005-05-24 Micron Technology, Inc. Method of supporting a substrate film

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5343475A (en) * 1976-10-01 1978-04-19 Seiko Epson Corp Flexible tape structure for gang bonding
JPS54161270A (en) * 1978-06-09 1979-12-20 Nec Corp Lead frame for integrated-circuit device
JPS5585051A (en) * 1978-12-22 1980-06-26 Hitachi Ltd Preparation of multilayer wiring structure
JPS5678255U (en) * 1979-11-07 1981-06-25
JPS5788752A (en) * 1980-11-25 1982-06-02 Hitachi Ltd Lead frame and semiconductor device prepared by using the same

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5343475A (en) * 1976-10-01 1978-04-19 Seiko Epson Corp Flexible tape structure for gang bonding
JPS54161270A (en) * 1978-06-09 1979-12-20 Nec Corp Lead frame for integrated-circuit device
JPS5585051A (en) * 1978-12-22 1980-06-26 Hitachi Ltd Preparation of multilayer wiring structure
JPS5678255U (en) * 1979-11-07 1981-06-25
JPS5788752A (en) * 1980-11-25 1982-06-02 Hitachi Ltd Lead frame and semiconductor device prepared by using the same

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4721994A (en) * 1985-06-25 1988-01-26 Toray Silicone Co., Ltd. Lead frame for semiconductor devices
US5075760A (en) * 1988-01-18 1991-12-24 Texas Instruments Incorporated Semiconductor device package assembly employing flexible tape
JPH0514516Y2 (en) * 1988-10-28 1993-04-19
US5084753A (en) * 1989-01-23 1992-01-28 Analog Devices, Inc. Packaging for multiple chips on a single leadframe
US6897092B2 (en) 1999-09-03 2005-05-24 Micron Technology, Inc. Method of supporting a substrate film
US6975021B1 (en) * 1999-09-03 2005-12-13 Micron Technology, Inc. Carrier for substrate film

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