JPH0637234A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH0637234A JPH0637234A JP4211018A JP21101892A JPH0637234A JP H0637234 A JPH0637234 A JP H0637234A JP 4211018 A JP4211018 A JP 4211018A JP 21101892 A JP21101892 A JP 21101892A JP H0637234 A JPH0637234 A JP H0637234A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor
- semiconductor element
- wiring
- insulating tape
- package
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】この発明は半導体装置に関し、特
に実装基板上での半導体素子の高密度実装化と実装基板
の小型化及びシステムの高速化を図ったものに関するも
のである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a semiconductor device having a high-density mounting of semiconductor elements on a mounting substrate, miniaturization of the mounting substrate, and speeding up of a system.
【０００２】[0002]
【従来の技術】図１４は従来の半導体装置（以下、半導
体パッケージ）の構成を示す透視平面図であり、図１５
は上記半導体パッケージを樹脂封止した後の断面図であ
り、各図に示すように、１２は半導体パッケージを示
し、１は型抜き形成された導電性シート材料のアイラン
ド部５上に配置された半導体素子であり、その縁部に多
数の電極２を有する。４は半導体素子１の周辺に配置さ
れ、例えば金線などのワイヤ３によって上記半導体素子
１の電極２に接続されるリード、６はタブ吊りリードで
あり、上記シート材料を打ち抜いて形成されたアイラン
ド部５を支持している。また７は樹脂１０で封止される
部分である樹脂封止本体を示し、その内部にリード４の
一部，ワイヤ３，アイランド部５，タブ吊りリード６，
及び半導体素子１を樹脂１０で封止している。2. Description of the Related Art FIG. 14 is a perspective plan view showing the structure of a conventional semiconductor device (hereinafter, semiconductor package).
FIG. 3 is a cross-sectional view of the semiconductor package after resin-sealing. As shown in the drawings, reference numeral 12 denotes a semiconductor package, and 1 is arranged on the island portion 5 of the die-cut conductive sheet material. It is a semiconductor element and has a large number of electrodes 2 on its edge. 4 is a lead arranged around the semiconductor element 1 and connected to the electrode 2 of the semiconductor element 1 by a wire 3 such as a gold wire, and 6 is a tab suspension lead, which is an island formed by punching out the sheet material. It supports part 5. Reference numeral 7 denotes a resin-sealed body which is a portion sealed with a resin 10, inside of which a part of the lead 4, the wire 3, the island portion 5, the tab suspension lead 6,
Also, the semiconductor element 1 is sealed with the resin 10.
【０００３】以上のように構成された半導体パッケージ
１２において、半導体素子１の周辺に設けられた電極２
とリード４とがワイヤ３を介して接続され、リード４と
半導体素子１との導通がなされている。In the semiconductor package 12 constructed as above, the electrodes 2 provided around the semiconductor element 1 are provided.
And the lead 4 are connected via the wire 3, and the lead 4 and the semiconductor element 1 are electrically connected.
【０００４】また、このようにして構成された半導体パ
ッケージ１２は、図１６に示すように、それぞれ機能の
異なる半導体パッケージ１２ａ，１２ｂ，１２ｃが、基
板１１上に別々に実装され、ぞれぞれが配線８を介して
相互に接続されてシステムを構築している。As shown in FIG. 16, the semiconductor package 12 thus constructed has the semiconductor packages 12a, 12b and 12c having different functions respectively mounted on the substrate 11 separately. Are connected to each other via wiring 8 to construct a system.
【０００５】[0005]
【発明が解決しようとする課題】従来の半導体装置は以
上のように構成されているので、システムを構築するの
に機能の異なる半導体パッケージを個々に基板上に実装
するため、基板の大きさが半導体パッケージの大きさに
制約されて小型化が難しく、しかも個々の半導体パッケ
ージのレイアウトの都合上、各半導体パッケージ間を接
続する配線を短くすることに限界があり、動作の高速化
が難しいという問題点があった。Since the conventional semiconductor device is constructed as described above, the size of the substrate is reduced because the semiconductor packages having different functions are individually mounted on the substrate to construct the system. The problem is that it is difficult to reduce the size due to the size of the semiconductor package, and because of the layout of the individual semiconductor packages, there is a limit to how short the wiring that connects each semiconductor package can be, making it difficult to operate at high speed. There was a point.
【０００６】この発明は上記のような問題点を解消する
ためになされたもので、システムを構築する際の実装基
板のサイズを小さくできるとともに、各半導体パッケー
ジ間を配線を用いることなく接続して、高密度実装及び
高速動作可能な半導体装置を得ることを目的とする。The present invention has been made in order to solve the above problems, and it is possible to reduce the size of a mounting board when constructing a system, and to connect each semiconductor package without using wiring. , A semiconductor device capable of high-density mounting and high-speed operation is obtained.
【０００７】[0007]
【課題を解決するための手段】この発明にかかる半導体
装置は、１つの半導体パッケージ内に機能の異なる半導
体素子を複数個設け、各素子間を電気的に接続するよう
にしたものである。A semiconductor device according to the present invention is one in which a plurality of semiconductor elements having different functions are provided in one semiconductor package and each element is electrically connected.
【０００８】[0008]
【作用】この発明においては、機能の異なる半導体素子
を１つの半導体パッケージに収納することにより、従
来、実装基板上に個別に配置されていた機能の異なる半
導体パッケージを削除することができ、実装基板の小型
化を図ることができ、しかも高密度実装が可能となる。According to the present invention, by storing semiconductor elements having different functions in one semiconductor package, the semiconductor packages having different functions which have been individually arranged on the mounting board in the related art can be eliminated. Can be miniaturized, and high-density mounting can be achieved.
【０００９】また従来、実装基板上で各半導体パッケー
ジ間を接続していた配線も削除することができるので、
システムの高速化ができる。Further, since the wiring that has conventionally connected between the semiconductor packages on the mounting substrate can be deleted,
The system speed can be increased.
【００１０】[0010]
【実施例】以下、本発明の実施例を図について説明す
る。 実施例１．図１は本発明の第１の実施例による半導体装
置（半導体パッケージ）の平面図、図２は樹脂封止後の
半導体装置の側面透視図を示し、それぞれ図１４及び図
１５と同一符号は同一または相当部分を示し、９は絶縁
テープであり、その上面には半導体素子１とは機能の異
なる半導体素子１ａが搭載されている。また８ａは上記
絶縁テープ９上に形成された配線であり、ワイヤ３ａを
用いて上記半導体素子１ａの電極２ａと接続されるとと
もに、ワイヤ３ｂによってリード４と接続されており、
このようにして半導体素子１と半導体素子１ａとの電気
的な導通が行われている。また１４は上記配線８ａの端
部に形成された電極である。なお、以下の説明におい
て、パッケージ上面とは半導体素子１が配置されている
側の面を指すものとする。Embodiments of the present invention will be described below with reference to the drawings. Example 1. FIG. 1 is a plan view of a semiconductor device (semiconductor package) according to a first embodiment of the present invention, and FIG. 2 is a side perspective view of the semiconductor device after resin encapsulation. Or, a considerable portion is shown, 9 is an insulating tape, and a semiconductor element 1a having a different function from the semiconductor element 1 is mounted on the upper surface thereof. Reference numeral 8a is a wiring formed on the insulating tape 9, which is connected to the electrode 2a of the semiconductor element 1a by using the wire 3a and is connected to the lead 4 by the wire 3b.
In this way, the semiconductor element 1 and the semiconductor element 1a are electrically connected. Reference numeral 14 is an electrode formed at the end of the wiring 8a. In the following description, the package upper surface means the surface on the side where the semiconductor element 1 is arranged.
【００１１】次に上記各半導体素子の接続関係について
詳細に説明する。従来と同様にアイランド部５上に半導
体素子１が搭載され、該半導体素子１の電極２と上記半
導体素子１周辺に配置されたリード４とがワイヤ３を介
して接続されている。そしてリード４のパッケージ上面
側には絶縁テープ９を介して、上記半導体素子１とは機
能の異なる半導体素子１ａが搭載され、この半導体素子
１ａの電極２ａと、上記半導体素子１と接続するリード
４とが配線８ａ及びワイヤ３ａを介して接続され、この
ようにして両半導体素子１，１ａ間の電気的な導通を行
っている。さらに必要に応じて上記リード４のうち、上
記半導体素子１とは接続していない所謂ＮＣピン１３と
上記半導体素子１ａとを配線８ａ及びワイヤ３ｃを介し
て接続され、これにより半導体素子１ａとパッケージ外
部とが導通する構成となっている。なお上記絶縁テープ
９はワイヤボンド時に位置を固定するために、リード４
上に接着材（図示せず）を用いて固定されている。Next, the connection relationship of the above semiconductor elements will be described in detail. The semiconductor element 1 is mounted on the island portion 5 as in the conventional case, and the electrode 2 of the semiconductor element 1 and the lead 4 arranged around the semiconductor element 1 are connected via the wire 3. A semiconductor element 1a having a function different from that of the semiconductor element 1 is mounted on the upper surface side of the package of the lead 4 via an insulating tape 9, and an electrode 2a of the semiconductor element 1a and a lead 4 connected to the semiconductor element 1 are connected. Are connected to each other via the wiring 8a and the wire 3a, thus electrically connecting the semiconductor elements 1 and 1a. Further, if necessary, a so-called NC pin 13 which is not connected to the semiconductor element 1 of the lead 4 and the semiconductor element 1a are connected via a wiring 8a and a wire 3c, whereby the semiconductor element 1a and the package are connected. It is configured to be electrically connected to the outside. The insulating tape 9 is fixed to the lead 4 in order to fix the position during wire bonding.
It is fixed using an adhesive (not shown) on the top.
【００１２】このように本実施例によれば、半導体素子
１周辺に配置されたリード４の、半導体パッケージ１２
の上面側に、半導体素子１ａを搭載する絶縁テープ９を
配置し、該絶縁テープ９に形成された配線８ａを用いて
ワイヤ３ｂを介して半導体素子１と接続をとるようにし
たから、１つの半導体パッケージ１２内に機能の異なる
２つの半導体素子１，１ａを収納することができ、従来
のように機能の異なる半導体素子を１つのパッケージ単
位として実装する場合に比べ、実装される半導体パッケ
ージ数を削減することができ、実装基板の小型化が可能
となり、しかも高密度実装を行うことができる。また同
一パッケージ内で機能の異なる半導体素子間が電気的に
接続されているため、従来、実装基板上でパッケージ間
を導通させていた配線を削除することかでき、システム
の高速化が可能となる。As described above, according to this embodiment, the semiconductor package 12 of the leads 4 arranged around the semiconductor element 1 is formed.
The insulating tape 9 for mounting the semiconductor element 1a is arranged on the upper surface side of the above, and the wiring 8a formed on the insulating tape 9 is used to connect to the semiconductor element 1 through the wire 3b. Two semiconductor elements 1 and 1a having different functions can be housed in the semiconductor package 12, and the number of semiconductor packages to be mounted can be reduced as compared with the conventional case where semiconductor elements having different functions are mounted as one package unit. The number can be reduced, the mounting board can be downsized, and high-density mounting can be performed. Further, since the semiconductor elements having different functions are electrically connected in the same package, it is possible to eliminate the wiring that has conventionally been conducted between the packages on the mounting board, and the system speed can be increased. .
【００１３】実施例２．次に本発明の第２の実施例によ
る半導体パッケージを図３ないし図５を用いて説明す
る。この実施例では、上記第１の実施例と同様にパッケ
ージ１２表面に絶縁テープ９を介して半導体素子１ａを
搭載するとともに、パッケージ１２裏面にも絶縁テープ
を介して機能の異なる半導体素子を搭載するようにした
ものである。Example 2. Next, a semiconductor package according to a second embodiment of the present invention will be described with reference to FIGS. In this embodiment, as in the first embodiment, the semiconductor element 1a is mounted on the front surface of the package 12 via the insulating tape 9, and the semiconductor elements having different functions are also mounted on the rear surface of the package 12 via the insulating tape. It was done like this.
【００１４】図において、９１は上記パッケージ１２裏
面側に配置された絶縁テープであり、該絶縁テープ９１
の表面には図５に示すように、半導体素子１ｂが搭載さ
れ、絶縁テープ９１表面に形成された配線８ｂとバンプ
電極（図示せず）によって直接接続されている。また上
記該絶縁テープ９１には、その上下面を貫通する貫通電
極２１が形成され、絶縁テープ９１の表面側では配線８
ｂと接続されている。そして上記絶縁テープ９上に配置
された半導体素子１ａとは貫通電極２１を介してワイヤ
３ｄを用いて電気的に接続されている。In the figure, reference numeral 91 is an insulating tape arranged on the back side of the package 12, and the insulating tape 91 is provided.
As shown in FIG. 5, the semiconductor element 1b is mounted on the surface of the wiring, and is directly connected to the wiring 8b formed on the surface of the insulating tape 91 by a bump electrode (not shown). Further, the insulating tape 91 is formed with through electrodes 21 penetrating the upper and lower surfaces thereof, and the wiring 8 is formed on the surface side of the insulating tape 91.
It is connected to b. The semiconductor element 1a arranged on the insulating tape 9 is electrically connected to the semiconductor element 1a via the through electrode 21 by using the wire 3d.
【００１５】このようにパッケージ１２の両面におい
て、機能の異なる半導体素子１ａ，１ｂを搭載すること
で、上記第１の実施例に比べてさらに集積度の向上及び
実装基板の縮小化を図ることができる。なお、絶縁テー
プ９１上に搭載される半導体素子１ｂと配線８ｂとをバ
ンプ電極（図示せず）を用いて接続したが、これは、ワ
イヤボンド時にパッケージ両面に対して作業を行うのを
避けるためであり、容易にパッケージ両面にワイヤボン
ドを施すことができる場合には、パッケージ１２表面側
の半導体素子１ａと同様に、ワイヤを用いて接続するよ
うにしてよい。By mounting the semiconductor elements 1a and 1b having different functions on both surfaces of the package 12 in this manner, the degree of integration and the size of the mounting board can be further reduced as compared with the first embodiment. it can. The semiconductor element 1b mounted on the insulating tape 91 and the wiring 8b were connected using bump electrodes (not shown), but this is to avoid working on both sides of the package during wire bonding. In the case where wire bonding can be easily performed on both surfaces of the package, the wires may be used for connection as in the case of the semiconductor element 1a on the front surface side of the package 12.
【００１６】実施例３．次に本発明の第３の実施例によ
る半導体パッケージを図６及び図７を用いて説明する。
この実施例では、上記第１の実施例と同様にパッケージ
１２表面に絶縁テープ９を介して半導体素子１ａを搭載
するとともに、さらにパッケージ１２表面に絶縁テープ
を介して半導体素子を搭載し、これら絶縁テープを介し
て搭載された半導体素子間を、その表面に配線が形成さ
れた絶縁テープを介して接続するようにしたものであ
る。Embodiment 3. Next, a semiconductor package according to the third embodiment of the present invention will be described with reference to FIGS.
In this embodiment, similarly to the first embodiment, the semiconductor element 1a is mounted on the surface of the package 12 via the insulating tape 9, and the semiconductor element is further mounted on the surface of the package 12 via the insulating tape. The semiconductor elements mounted via the tape are connected via an insulating tape having wiring formed on the surface thereof.
【００１７】図において、９２はパッケージ１２表面に
絶縁テープ９と対角線上に位置するように設けられた絶
縁テープであり、その上には半導体素子１，１ａとは異
なる機能を有する半導体素子１ｃが搭載されており、絶
縁テープ９２上に形成された配線８ｃを用い、ワイヤ３
ｂを介して半導体素子１が接続されたリード４と接続さ
れるとともに、ワイヤ３ａ，３ｃを介してＮＣピン１３
と接続されている。また半導体素子１ａと半導体素子１
ｃとは、中継用絶縁テープ９３上に形成された配線８ｄ
を用いて、ワイヤ３ｅを介して相互的に接続されてい
る。In the figure, reference numeral 92 is an insulating tape provided on the surface of the package 12 so as to be positioned diagonally with the insulating tape 9, on which a semiconductor element 1c having a function different from that of the semiconductor elements 1 and 1a is provided. The wiring 3 is mounted and uses the wiring 8c formed on the insulating tape 92.
is connected to the lead 4 to which the semiconductor element 1 is connected via b, and the NC pin 13 is connected via the wires 3a and 3c.
Connected with. Further, the semiconductor element 1a and the semiconductor element 1
c is the wiring 8d formed on the relay insulating tape 93.
Are mutually connected via a wire 3e.
【００１８】このようにすることで、上記第２の実施例
と同様に半導体素子の集積度の向上及び実装基板の縮小
化を図ることができ、また半導体素子１と半導体素子１
ａ又は１ｂ間において、信号の入出力関係上、半導体素
子１に対する半導体素子１ａ又は１ｂの配置位置に制限
があるような場合でも、離れて配置された半導体素子１
ａ，１ｃ間の電気的接続を行うことができる。By doing so, it is possible to improve the degree of integration of the semiconductor elements and reduce the size of the mounting substrate as in the case of the second embodiment, and the semiconductor elements 1 and 1
Even when the arrangement position of the semiconductor element 1a or 1b with respect to the semiconductor element 1 is limited between a and 1b due to the signal input / output relationship, the semiconductor elements 1 arranged apart from each other.
Electrical connection between a and 1c can be established.
【００１９】実施例４．次に本発明の第４の実施例によ
る半導体パッケージを図８ないし図１３を用いて説明す
る。この実施例では、上記各実施例において、絶縁テー
プ上に搭載される半導体素子と、上記絶縁テープ上に形
成された配線とをバンプ電極を用いて接続するようにし
たものである。Example 4. Next, a semiconductor package according to a fourth embodiment of the present invention will be described with reference to FIGS. In this embodiment, in each of the above-described embodiments, the semiconductor element mounted on the insulating tape and the wiring formed on the insulating tape are connected by using bump electrodes.
【００２０】図８及び図９に示すように、絶縁テープ９
上の配線８ａと半導体素子１ａとはバンプ電極（図示せ
ず）を用いて接続されており、このようにすることで、
半導体素子１ａと配線８ａ間を接続するワイヤを削除す
ることができ、絶縁テープ９の面積の縮小化を図ること
ができ、またワイヤボンド工程を少なくすることができ
る。As shown in FIGS. 8 and 9, the insulating tape 9
The upper wiring 8a and the semiconductor element 1a are connected by using bump electrodes (not shown), and by doing so,
The wire connecting the semiconductor element 1a and the wiring 8a can be eliminated, the area of the insulating tape 9 can be reduced, and the wire bonding process can be reduced.
【００２１】また第２及び第３の実施例においても、ぞ
れぞれ図１０，１１、及び図１２，１３に示すように、
各半導体素子と絶縁テープに形成された配線とをバンプ
電極を用いて接続するようにしてもよく、上記実施例と
同様の効果を奏する。Also in the second and third embodiments, as shown in FIGS. 10 and 11 and FIGS. 12 and 13, respectively,
The respective semiconductor elements and the wiring formed on the insulating tape may be connected by using bump electrodes, and the same effect as that of the above-described embodiment is obtained.
【００２２】なお、上記第２ないし第４の実施例におい
て、半導体パッケージ１２表面及び裏面に配置される、
半導体素子１とは機能の異なる半導体素子の数は上記説
明した個数に限られるものではなく、さらに多くの数の
半導体素子を配置するようにしてもよい。In the second to fourth embodiments, the semiconductor package 12 is arranged on the front and back surfaces,
The number of semiconductor elements having different functions from the semiconductor element 1 is not limited to the number described above, and a larger number of semiconductor elements may be arranged.
【００２３】[0023]
【発明の効果】以上のように、この発明に係る半導体装
置によれば、リード上に、配線及び電極を備えた絶縁テ
ープを貼りつけることにより、機能の異なる複数の半導
体素子を１つの半導体パッケージ内に収納でき、実装基
板上の半導体パッケージ数を削除でき、システムを構築
した際の装置の小型化及び実装密度の向上を図ることが
でき、また半導体素子間の配線長を短くすることができ
るので、システム動作の高速化を図ることができる効果
がある。As described above, according to the semiconductor device of the present invention, a plurality of semiconductor elements having different functions are integrated into one semiconductor package by attaching an insulating tape having wiring and electrodes on the leads. It can be housed inside, the number of semiconductor packages on the mounting board can be eliminated, the device can be downsized when the system is constructed, the mounting density can be improved, and the wiring length between semiconductor elements can be shortened. Therefore, there is an effect that the system operation can be speeded up.
【図１】本発明の第１の実施例による半導体装置の平面
図。FIG. 1 is a plan view of a semiconductor device according to a first embodiment of the present invention.
【図２】上記実施例の側面透視図。FIG. 2 is a side perspective view of the above embodiment.
【図３】本発明の第２の実施例による半導体装置の平面
図。FIG. 3 is a plan view of a semiconductor device according to a second embodiment of the present invention.
【図４】上記実施例の側面透視図。FIG. 4 is a side perspective view of the above embodiment.
【図５】上記実施例の裏面図。FIG. 5 is a rear view of the above embodiment.
【図６】本発明の第３の実施例による半導体装置の平面
図。FIG. 6 is a plan view of a semiconductor device according to a third embodiment of the present invention.
【図７】上記実施例の側面透視図。FIG. 7 is a side perspective view of the above embodiment.
【図８】上記第１の実施例において半導体素子と配線と
をバンプ電極を用いて接続したものを、本発明の第４の
実施例として説明するための半導体装置の平面図。FIG. 8 is a plan view of a semiconductor device for explaining, as a fourth embodiment of the present invention, what is obtained by connecting a semiconductor element and a wiring by using a bump electrode in the first embodiment.
【図９】図８の側面透視図。9 is a side perspective view of FIG. 8. FIG.
【図１０】上記第２の実施例において半導体素子と配線
とをバンプ電極を用いて接続したものを、本発明の第４
の実施例として説明するための半導体装置の平面図。FIG. 10 shows a fourth embodiment of the present invention in which the semiconductor element and the wiring are connected using a bump electrode in the second embodiment.
FIG. 3 is a plan view of a semiconductor device for explaining the embodiment of FIG.
【図１１】図１０の側面透視図。11 is a side perspective view of FIG.
【図１２】上記第３の実施例において半導体素子と配線
とをバンプ電極を用いて接続したものを、本発明の第４
の実施例として説明するための半導体装置の平面図。FIG. 12 shows a fourth embodiment of the present invention in which the semiconductor element and the wiring are connected using a bump electrode in the third embodiment.
FIG. 3 is a plan view of a semiconductor device for explaining the embodiment of FIG.
【図１３】図１２の側面透視図。13 is a side perspective view of FIG.
【図１４】従来の半導体装置の透視平面図。FIG. 14 is a perspective plan view of a conventional semiconductor device.
【図１５】従来の半導体装置の側面断面図。FIG. 15 is a side sectional view of a conventional semiconductor device.
【図１６】従来の半導体装置を搭載した実装基板の平面
図。FIG. 16 is a plan view of a mounting board on which a conventional semiconductor device is mounted.
１ 半導体素子 １ａ 半導体素子 １ｂ 半導体素子 １ｃ 半導体素子 ２ 電極 ２ａ 電極 ３ ワイヤ ４ リード ５ アイランド部 ６ タブ吊りリード ７ 樹脂封止部本体 ８ 配線 ９ 絶縁テープ ９１ 絶縁テープ ９２ 絶縁テープ ９３ 中継用絶縁テープ １０ 樹脂 １１ 実装基板 １２ 半導体パッケージ １３ ＮＣピン １４ 電極 1 Semiconductor Element 1a Semiconductor Element 1b Semiconductor Element 1c Semiconductor Element 2 Electrode 2a Electrode 3 Wire 4 Lead 5 Island Part 6 Tab Hanging Lead 7 Resin Sealing Part Main Body 8 Wiring 9 Insulation Tape 91 Insulation Tape 92 Insulation Tape 93 Relay Insulation Tape 10 Resin 11 Mounting board 12 Semiconductor package 13 NC pin 14 Electrode
───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.5 識別記号 庁内整理番号 ＦＩ 技術表示箇所 Ｈ０１Ｌ 25/18 ─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. 5 Identification code Internal reference number FI Technical indication H01L 25/18
Claims (4)
し、該半導体素子周辺に配置されたリード端子と上記半
導体素子とをワイヤにより接続し、全体を樹脂封止して
なる半導体装置において、 上記リード端子上に、絶縁フィルムを介して上記半導体
素子とは機能の異なる半導体素子を配置し、これを上記
半導体素子と電気的に接続した状態で全体を樹脂封止し
たことを特徴とする半導体装置。1. A semiconductor device in which a semiconductor element is mounted on a lead frame, a lead terminal arranged in the periphery of the semiconductor element and the semiconductor element are connected by a wire, and the whole is resin-sealed. A semiconductor device in which a semiconductor element having a function different from that of the semiconductor element is arranged on a terminal via an insulating film, and the whole is resin-sealed in a state of being electrically connected to the semiconductor element.
にそれぞれ設けられていることを特徴とする半導体装
置。2. The semiconductor device according to claim 1, wherein the semiconductor elements having the different functions are provided on both surfaces of the lead terminal, respectively.
数個配置し、 上記リード端子に対して同一面側に配置された機能の異
なる半導体素子間を、その表面に配線が形成された中継
用絶縁テープを介して電気的に接続したことを特徴とす
る半導体装置。3. The semiconductor device according to claim 1, wherein a plurality of semiconductor elements having different functions are arranged on the lead terminal, and semiconductor elements having different functions arranged on the same surface side with respect to the lead terminal. Is electrically connected via a relay insulating tape having wiring formed on the surface thereof.
能の異なる半導体素子とバンプ電極を用いて接続されて
いることを特徴とする半導体装置。4. The semiconductor device according to claim 1, wherein wiring is formed on the insulating tape, and the wiring is connected to semiconductor elements having different functions by using bump electrodes. .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4211018A JPH0637234A (en) | 1992-07-14 | 1992-07-14 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4211018A JPH0637234A (en) | 1992-07-14 | 1992-07-14 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0637234A true JPH0637234A (en) | 1994-02-10 |
Family
ID=16598990
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4211018A Pending JPH0637234A (en) | 1992-07-14 | 1992-07-14 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0637234A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007035853A (en) * | 2005-07-26 | 2007-02-08 | Renesas Technology Corp | Method of manufacturing semiconductor device |
| JP2014063966A (en) * | 2012-09-24 | 2014-04-10 | Renesas Electronics Corp | Semiconductor device |
-
1992
- 1992-07-14 JP JP4211018A patent/JPH0637234A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007035853A (en) * | 2005-07-26 | 2007-02-08 | Renesas Technology Corp | Method of manufacturing semiconductor device |
| JP4679991B2 (en) * | 2005-07-26 | 2011-05-11 | ルネサスエレクトロニクス株式会社 | Semiconductor device |
| JP2014063966A (en) * | 2012-09-24 | 2014-04-10 | Renesas Electronics Corp | Semiconductor device |
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