JPS5930538Y2 - semiconductor equipment - Google Patents
semiconductor equipmentInfo
- Publication number
- JPS5930538Y2 JPS5930538Y2 JP757079U JP757079U JPS5930538Y2 JP S5930538 Y2 JPS5930538 Y2 JP S5930538Y2 JP 757079 U JP757079 U JP 757079U JP 757079 U JP757079 U JP 757079U JP S5930538 Y2 JPS5930538 Y2 JP S5930538Y2
- Authority
- JP
- Japan
- Prior art keywords
- metallized
- lead
- wire
- grounded
- tip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
Landscapes
- Wire Bonding (AREA)
Description
【考案の詳細な説明】
本考案は、セラミック製容器を用いた半導体装置の構造
に関するものである。[Detailed Description of the Invention] The present invention relates to the structure of a semiconductor device using a ceramic container.
従来この種の半導体装置用容器（以下パッケージと呼ぶ
）は、半導体素子（以下チップと呼ぶ）をパッケージの
チップ固着部（以下アイランド部と呼ぶ）に接着し、金
属細線で結線（以上ボンディングと呼ぶ）を行ってから
キャップ封止した構造であり、この容器はチップの特性
を最大限に発揮させる為にアイランドと特定のメタライ
ズリードとキャップ取付枠（以下シールリングと呼ぶ）
との三者を電気的導通状態（以下グランドと呼ぶ）にし
ておくことが望ましい。Conventionally, this type of container for semiconductor devices (hereinafter referred to as a package) is made by bonding a semiconductor element (hereinafter referred to as a chip) to a chip fixing part (hereinafter referred to as an island part) of the package, and connecting it with a thin metal wire (hereinafter referred to as bonding). ) and then sealed with a cap, and this container is made with an island, specific metallized leads, and a cap mounting frame (hereinafter referred to as a seal ring) in order to maximize the characteristics of the chip.
It is desirable to keep these three parties in electrical continuity (hereinafter referred to as ground).
このため従来はグランドしたい特定のメタライズリード
の隣りにメタライズリードとほぼ同寸法のグランド用メ
タライズリードを設け、特定メタライズリードとグラン
ド用メタライズリードとを金属細線でボンディングする
。For this reason, conventionally, a metallized lead for grounding having approximately the same size as the metallized lead is provided next to a specific metallized lead to be grounded, and the specific metallized lead and the metallized lead for grounding are bonded with a thin metal wire.
しかしながらこのボンディングの際、金属細線がメタラ
イズリードとグランド用メタライズリードとを直角に横
切る方向にボンディングされるので、チップ電極とメタ
ライズリードとを先にボンディングした金属細線にボン
ダーのツールが接触し変形もしくは切断する恐れがある
。However, during this bonding, the metal wire is bonded in a direction perpendicular to the metallized lead and the ground metallized lead, so the bonder's tool may come into contact with the metal wire that was previously bonded to the chip electrode and the metallized lead, resulting in deformation or deformation. There is a risk of amputation.
又、従来技術による他の方法は、メタライズリードの先
端部にアイランドを囲むようにグランド用メタライズを
設け、この両者をボンディングするものであるが、この
方法はグランドリード部以外はグランド用メタライズと
金属細線が接触する恐れとメタライズリードの長さが確
保できなくなる欠点があった。Another method according to the prior art is to provide ground metallization at the tip of the metallized lead so as to surround the island, and bond the two together; There was a risk that the thin wires would come into contact with each other, and the length of the metallized lead could not be ensured.
次に従来の半導体装置用容器について図面を用いて説明
する。Next, a conventional container for semiconductor devices will be described with reference to the drawings.
第１図はその平面図を示す。FIG. 1 shows its plan view.
セラミック基板の中央にアイランド部１を設は一段高い
位置のその周辺から放射状に複数のメタライズリード２
がセラミック基板の中間層を通って外部リード４に接続
されている。An island part 1 is provided in the center of the ceramic substrate, and a plurality of metallized leads 2 are arranged radially from its periphery at a higher position.
is connected to the external lead 4 through the intermediate layer of the ceramic substrate.
又、グランドしたいメタライズリードの近くにグランド
用メタライズリード３を数本設け、該メタライズリード
３とアイランド１とは電気的に導通されている。Further, several grounding metallized leads 3 are provided near the metallized lead to be grounded, and the metallized leads 3 and the island 1 are electrically connected.
このようなパッケージのアイランドにチップ５を固着し
た後に金又はアルミワイヤー６によりメタライズリード
２とチップ電極とを結線し、次にグランドしたいメタラ
イズリード２とグランド用メタライズリード３とを同じ
く金又はアルミワイヤーにより結線する。After fixing the chip 5 to the island of such a package, connect the metallized lead 2 and the chip electrode with a gold or aluminum wire 6, and then connect the metallized lead 2 to be grounded and the metalized lead 3 for grounding with the same gold or aluminum wire. Connect the wires by
この場合ワイヤーボンダーのツールがメタライズリード
２を横切る方向に動くので正規のボンディング線に接触
しワイヤーを変形又は切断する恐れがあり非常にボンデ
ィング作業が難しく、品質、歩留りが悪いものであった
。In this case, since the wire bonder tool moves in a direction across the metallized lead 2, it may come into contact with the regular bonding wire and deform or cut the wire, making the bonding work extremely difficult and resulting in poor quality and yield.
次に第２図は他の従来の技術の平面図を示す。Next, FIG. 2 shows a plan view of another conventional technique.
セラミック基板の中央にアイランド１を設けその一段高
い位置の周囲にアイランド１を囲むようにグランド用メ
タライズ７が印刷されアイランド１とシールリング８が
スルホール又は側面メタライズによって導通されている
。An island 1 is provided in the center of the ceramic substrate, and a grounding metallization 7 is printed around the island 1 at a higher position, and the island 1 and the seal ring 8 are electrically connected by through holes or side metallization.
このグランド用メタライズ７の近傍からメタライズリー
ド２が放射状に伸びセラミックの中間層を通って外部リ
ード４に接続されている。Metallized leads 2 extend radially from the vicinity of this grounding metallized layer 7 and are connected to external leads 4 through the ceramic intermediate layer.
このようなパッケージのアイランド１にチップ５の接着
しチップ電極とメタライズリードをワイヤーボンディン
グし更にグランドしたいリードとグランド用メタライズ
７とをワイヤーボンディングすると任意のリードをグラ
ンドすることができるが、パッケージのアイランド径が
小さくなり更にワイヤーボンディングするメタライズリ
ード長が短かくなる。Any lead can be grounded by adhering the chip 5 to the island 1 of such a package, wire-bonding the chip electrode and metallized lead, and then wire-bonding the lead to be grounded to the grounding metallized lead 7. As the diameter becomes smaller, the length of the metallized lead for wire bonding becomes shorter.
又、ワイヤーボンディングした場合、個々のメタライズ
リード２とチップ電極間のワイヤーがグランド用メタラ
イズリード７に接着する恐れがありボンディング作業が
難しくなる欠点があった。Further, when wire bonding is performed, there is a possibility that the wire between each metallized lead 2 and the chip electrode may adhere to the grounding metallized lead 7, making the bonding work difficult.
本考案は上述した欠点を除去し、品質を安定させて、し
かもワイヤーポンチ゛イング作業が確実に行うことがで
きる汎用性のあるパッケージを有する半導体装置を提供
することを目的とする。SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device having a versatile package that eliminates the above-mentioned drawbacks, has stable quality, and can be reliably wire punched.
本考案の特徴は、半導体素子を搭載せるアイランド部と
、該アイランド部より一段高い位置に該アイランド部の
各周辺に向ってそれぞれ複数のメタライズリードが延在
する半導体装置において、グランドしたいメタライズリ
ードを除く複数のメタライズリードは前記一段高い位置
において長方形の平面形状をなし他の部分と同じ巾をな
す先端部近傍において前記半導体素子のチップ電極とそ
れぞれワイヤーポンチ゛イングにより接続されており、
該グランドしたいメタライズリードの平面形状は他のメ
タライズリードと平行に延在する第１の部分と該第１の
部分の先端部近傍において一方の側方向もしくは両方の
側方向に該第１の部分の延在方向とは直角にのびる第２
の部分とを有し、グランド用メタライズが該第１の部分
と並行に延在しかつ該第２の部分と向い合うごとく設け
られ、前記半導体素子の所定のチップ電極と該グランド
したいメタライズリードの第１の部分の先端部近傍とワ
イヤーボンディングされており、がっ該グランドしたい
メタライズリードの第２の部分と該グランド用メタライ
ズの先端部近傍とがワイヤーポンチ゛イングされている
半導体装置にある。The feature of the present invention is that in a semiconductor device having an island portion on which a semiconductor element is mounted and a plurality of metallized leads extending toward each periphery of the island portion at a position higher than the island portion, the metallized lead to be grounded is connected to the island portion. The plurality of metallized leads other than the metallized leads have a rectangular planar shape at the one step higher position and are connected to the chip electrodes of the semiconductor element by wire punching near the tip portions having the same width as the other parts,
The planar shape of the metallized lead to be grounded includes a first part extending parallel to other metallized leads, and a first part extending in one or both lateral directions near the tip of the first part. The second part extends perpendicularly to the extending direction.
A ground metallization is provided so as to extend parallel to the first part and face the second part, and a ground metallization is provided between a predetermined chip electrode of the semiconductor element and the metallization lead to be grounded. The first part is wire-bonded to the vicinity of the tip thereof, and the second part of the metallized lead to be grounded and the vicinity of the tip of the grounding metallized lead are wire-punched.
以下本考案の実施例を図面を用いて説明する。Embodiments of the present invention will be described below with reference to the drawings.
第３図は平面図を示す。FIG. 3 shows a plan view.
セラミック基板の中央にアイランド部２１を設は一段高
い位置のその周囲から複数のメタライズリード２２とグ
ランドしたいメタライズリード２９がグランド用メタラ
イズリード２３の近傍にＬ字状又はＴ字状に配置されて
いる。An island part 21 is provided in the center of the ceramic substrate, and a plurality of metallized leads 22 and a metallized lead 29 to be grounded are arranged in an L-shape or T-shape near the metallized lead 23 for grounding from around the island part 21 at a higher position. .
このパッケージのアイランド部２１にチップ２５を固着
しチップ電極とメタライズリード２２を金又はアルミワ
イヤー６によりワイヤーボンディングし、更にグランド
したいメタライズリード２９とグランド用メタライズリ
ード２３をワイヤーボンディングする。A chip 25 is fixed to the island portion 21 of this package, and the chip electrode and the metallized lead 22 are wire-bonded using gold or aluminum wire 6, and further, the metallized lead 29 to be grounded and the metalized lead 23 for grounding are wire-bonded.
このようなボンディング方法であるとチップ電極とメタ
ライズリード、メタライズリードとグランド用メタライ
ズリードとにワイヤーボンディングする方向が同じ方向
であるのでボンディング、ツールでワイヤーを変形した
り切断する事もなくなり、更に作業性が良くなり品質も
安定する。With this bonding method, the wire bonding is done in the same direction between the chip electrode and the metallized lead, and between the metallized lead and the ground metallized lead, so there is no need to deform or cut the wire with bonding or tools, making the work even easier. The properties are improved and the quality is stable.
又パッケージの種類は一種類に減るので製造及び管理が
し易くなる。Also, since the number of types of packages is reduced to one, manufacturing and management become easier.
第１図および第２図はそれぞれ従来の半導体装置に用い
られる容器およびそこに搭載された半導体素子を示す平
面図で、第３図は本考案の一実施例の半導体装置に用い
られる容器およびそこに搭載された半導体素子を示す平
面図である。
尚、図において、１，２１・・・・・・アイランド部、
２゜２２・・・・・・メタライズリード、３．２３・・
・・・・グランド用メタライズ、４，２４・・・・・・
外部リード、５．２５・・・・・・半導体素子、６，２
６・・・・・・金又はアルミワイヤー、７・・曲グラン
ド用メタライズ、８・・・・・・シールリング、２９・
・曲グランドしたいメタライズリードである。1 and 2 are plan views showing a container used in a conventional semiconductor device and a semiconductor element mounted therein, respectively, and FIG. 3 is a plan view showing a container used in a semiconductor device according to an embodiment of the present invention and its FIG. In addition, in the figure, 1, 21... island part,
2゜22...Metalized lead, 3.23...
...Ground metallization, 4,24...
External lead, 5.25...Semiconductor element, 6,2
6... Gold or aluminum wire, 7... Metallized for curved gland, 8... Seal ring, 29...
・It is a metalized lead that you want to make the song grand.
Claims (1)
より一段高い位置に該アイランド部の各周辺に向ってそ
れぞれ複数のメタライズリードが延在する半導体装置に
おいて、グランドしたいメタライズリードを除く複数の
メタライズリードは前記一段高い位置において長方形の
平面形状をなし他の部分と同じ巾をなす先端部近傍にお
いて前記半導体素子のチップ電極とそれぞれワイヤーボ
ンディングにより接続されており、該グランドしたいメ
タライズリードの平面形状はメタライズリードと平行に
延在する第１の部分と該第１の部分の先端部近傍におい
て一方の側方向もしくは両方の側方向に該第１の部分の
延在方向とは直角にのびる第２の部分とを有し、グラン
ド用メタライズが該第１の部分と並行に延在しかつ該第
２の部分と向い合うごとく設けられ、前記半導体素子の
所定のチップ電極と該グランドしたいメタライズリード
の第１の部分の先端部近傍とワイヤーボンディングされ
ており、かつ該グランドしたいメタライズリードの第２
の部分と該グランド用メタライズの先端部近傍とがワイ
ヤーボンディングされていることを特徴とする半導体装
置。In a semiconductor device having an island portion on which a semiconductor element is mounted and a plurality of metallized leads extending toward each periphery of the island portion at a position higher than the island portion, the plurality of metallized leads other than the metallized lead to be grounded are The planar shape of the metallized lead to be grounded is connected to the chip electrode of the semiconductor element by wire bonding near the tip which has a rectangular planar shape at the higher position and has the same width as the other parts, and the planar shape of the metallized lead to be grounded is the same as that of the metallized lead. a first portion extending parallel to the first portion; and a second portion extending perpendicularly to the extending direction of the first portion in one or both lateral directions near the tip of the first portion. A grounding metallization is provided so as to extend parallel to the first part and facing the second part, and a predetermined chip electrode of the semiconductor element and the first metallization lead to be grounded are provided. The second part of the metallized lead that is wire-bonded to the vicinity of the tip of the part and that you want to ground.
A semiconductor device characterized in that a portion near the tip of the ground metallization is wire-bonded.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP757079U JPS5930538Y2 (en) | 1979-01-23 | 1979-01-23 | semiconductor equipment |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP757079U JPS5930538Y2 (en) | 1979-01-23 | 1979-01-23 | semiconductor equipment |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS55108745U JPS55108745U (en) | 1980-07-30 |
| JPS5930538Y2 true JPS5930538Y2 (en) | 1984-08-31 |
Family
ID=28815473
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP757079U Expired JPS5930538Y2 (en) | 1979-01-23 | 1979-01-23 | semiconductor equipment |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5930538Y2 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60154646A (en) * | 1984-01-25 | 1985-08-14 | Hitachi Micro Comput Eng Ltd | Semiconductor device |
| KR940006585B1 (en) * | 1985-02-28 | 1994-07-22 | 소니 가부시키가이샤 | Semicondocteur circuit device |
-
1979
- 1979-01-23 JP JP757079U patent/JPS5930538Y2/en not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| JPS55108745U (en) | 1980-07-30 |
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