JPS62296528A - Resin-sealed semiconductor device - Google Patents

Resin-sealed semiconductor device

Info

Publication number
JPS62296528A
JPS62296528A JP14082186A JP14082186A JPS62296528A JP S62296528 A JPS62296528 A JP S62296528A JP 14082186 A JP14082186 A JP 14082186A JP 14082186 A JP14082186 A JP 14082186A JP S62296528 A JPS62296528 A JP S62296528A
Authority
JP
Japan
Prior art keywords
chip
resin
lead frame
electrodes
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14082186A
Other languages
Japanese (ja)
Inventor
Itaru Maeda
前田　志
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electronics Corp filed Critical Matsushita Electronics Corp
Priority to JP14082186A priority Critical patent/JPS62296528A/en
Publication of JPS62296528A publication Critical patent/JPS62296528A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item

Landscapes

  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE:To improve the bondability of a lead frame to a resin by extending inner leads onto a semiconductor chip, and interposing a thin insulating layer between the chips. CONSTITUTION:Electrodes 3 collected to the center of a chip 3 placed on a chip placing tab 1 are so sealed with resin 6 as to be electrically connected with inner leads 8 and fine metal wirings 5 arrived at the top of the chip through the chip 2 and an insulating thin layer 7. The layer 7 is bonded in advance to a lead frame, and bonded to the chip 2 by a bonding resin before electrically connected with the electrodes 3 on the chip on the tab lead 1. The layer 7 is so formed in space at the center as to connect the electrodes 3 with the lead frame. Thus, the bonding strength of the lead frame with the resin can be enhanced.

Description

【発明の詳細な説明】 ３、発明の詳細な説明 産業上の利用分野 本発明は樹脂封止型半導体装置に係り、特に内部リード
フレームの構造に関するものである。Detailed Description of the Invention 3. Detailed Description of the Invention Field of Industrial Application The present invention relates to a resin-sealed semiconductor device, and particularly to the structure of an internal lead frame.

従来の技術 従来の樹脂封止型半導体装置のリードフレーム構造につ
いて第３図、第４図の平面図、断面図を用いて説明する
。各図において従来の樹脂封止型半導体装置の構造は、
チップ搭載タブ１に搭載したチップ２に設けられた電極
３がリードフレーム４と金属細線５により電気的に接続
された形で樹脂６により封止されている。2. Description of the Related Art The lead frame structure of a conventional resin-sealed semiconductor device will be described with reference to the plan view and cross-sectional view of FIGS. 3 and 4. In each figure, the structure of a conventional resin-sealed semiconductor device is as follows.
An electrode 3 provided on a chip 2 mounted on a chip mounting tab 1 is electrically connected to a lead frame 4 by a thin metal wire 5 and sealed with a resin 6.

リードフレームはパッケージ上面からみてチップと重な
らない構造となっている。The lead frame has a structure that does not overlap the chip when viewed from the top of the package.

発明が解決しようとする問題点 高集積化によるチップ大型化が進む昨今では、標準パッ
ケージへ組み込む場合、パッケージの外形寸法を変更で
きないため、チップと外囲部表面との距離が短かくなり
、それにともないリードフレームの樹脂固定される面積
が減少し、樹脂とリードフレームとの接着強度が減少す
ることから、樹脂とリードフレームとの界面にすきまが
でき、そこからの水分の浸入によりチップの信頼性を著
しく低下させる問題が発生することがある。Problems that the invention aims to solve These days, as chips become larger due to higher integration, when incorporating them into a standard package, the external dimensions of the package cannot be changed. As a result, the area of the lead frame that is fixed with the resin decreases, and the adhesive strength between the resin and the lead frame decreases, creating a gap at the interface between the resin and the lead frame, which causes moisture to enter and reduce the reliability of the chip. Problems may occur that significantly reduce the

本発明は、かかる点に鑑みてなされたもので、チップの
大型化により問題となるリードフレームと樹脂との接着
強度減少に起因する信頼性の低下を防止することを目的
としている。The present invention has been made in view of this problem, and aims to prevent a decrease in reliability due to a decrease in adhesive strength between a lead frame and a resin, which becomes a problem as chips become larger.

問題点を解決するための手段 本発明は、上記問題点を解決するため、内部リードを半
導体チップ面上まで延長し、かつ、前記半導体チップと
の間に絶縁性薄層体を介在させて外囲樹脂封止したもの
である。Means for Solving the Problems In order to solve the above problems, the present invention extends the internal leads to the surface of the semiconductor chip, and interposes an insulating thin layer between them and the semiconductor chip. It is sealed with resin.

作用 本発明により、チップの大型化にともなうリードフレー
ムと樹脂との接着面積を増加さゼることかでき、リード
フレームと樹脂との接着強度を高めることができる。Effects According to the present invention, it is possible to increase the bonding area between the lead frame and the resin as chips become larger, and it is possible to increase the bonding strength between the lead frame and the resin.

実施例 次に本発明を実施例により説明する。Example Next, the present invention will be explained by examples.

第１図は樹脂封止型半導体装置の内部平面図、第２図は
その断面図である。FIG. 1 is an internal plan view of a resin-sealed semiconductor device, and FIG. 2 is a sectional view thereof.

チップ搭載タブ１に搭載したチップ２の中央部に集設さ
れた電極３がチップと絶縁性薄層体７、（たとえば、ポ
リイミドフィルム）をはさんで、チップ」二部にまで達
した内部リード８と金属細線５により電気的に接続され
た形で、樹脂６により封止された構造となっている。The electrodes 3 concentrated in the center of the chip 2 mounted on the chip mounting tab 1 sandwich the chip and an insulating thin layer 7 (for example, a polyimide film), and form internal leads that reach the second part of the chip. 8 and is electrically connected by a thin metal wire 5, and is sealed with resin 6.

ここで絶縁性薄層体７は、あらかじめリードフレームと
接着しておき、タブリード１上のチップ上電極と電気的
に接続する工程の前に、接着性樹脂等を用いてチップと
接着させておいである。この絶縁性薄層体７は、チップ
上電極とリードフレームの接続が可能なように中央部が
あいた構造になっている。Here, the insulating thin layer 7 is bonded to the lead frame in advance, and is bonded to the chip using an adhesive resin or the like before the process of electrically connecting it to the electrode on the chip on the tab lead 1. be. This insulating thin layer body 7 has a structure with an opening in the center so that the electrodes on the chip can be connected to the lead frame.

このような構造にすることによりり一トフレームと樹脂
との接着強度を高めることができチップの大型化にとも
ない従来の樹脂封止型半導体装置で起こっていた、信頼
性の低下を防止するこ占ができた。This structure increases the adhesive strength between the frame and the resin, and prevents the decrease in reliability that occurs with conventional resin-sealed semiconductor devices as chips become larger. I was able to fortune tell.

なお、実施例では、チップ上電極がチップ中央部に集設
されたものを使用したが、これは内部リードフレームを
最も長く延長した場合の構造であり、特に限定されるも
のでなく、リードフレームと樹脂との接着強度を考慮し
任意にチップ上電極位置を決めれば良い。In addition, in the example, a structure in which the on-chip electrodes were concentrated at the center of the chip was used, but this is the structure when the internal lead frame is extended to the longest length, and is not particularly limited. The positions of the electrodes on the chip may be arbitrarily determined by considering the adhesive strength between the electrode and the resin.

また、本発明は、チップの大型化に際し、とりわけ有効
であるが、内部リードを有するあらゆる樹脂封止型半導
体装置に対し適用が可能である。Furthermore, although the present invention is particularly effective when increasing the size of a chip, it can be applied to any resin-sealed semiconductor device having internal leads.

発明の効果 以上述べたように、本発明の樹脂封１に型半導体装置は
リードフレームの構造を変えることにより、チップの大
型化にともない問題となっていた樹脂とリードフレーム
の接着強度を高めることにより信頼性を大幅に向上させ
ることができた。Effects of the Invention As described above, the resin-sealed type semiconductor device of the present invention improves the adhesive strength between the resin and the lead frame, which has been a problem as chips become larger, by changing the structure of the lead frame. We were able to significantly improve reliability.

【図面の簡単な説明】[Brief explanation of drawings]

第１図、第２図は本発明の実施例の平面図、断面図、第
３図、第４図は従来装置の概要を示す平面図、断面図で
ある。 １・・・・・・チップ搭載タブ、２・・・・・・チップ
、３・・・・・・　電極、４・・・・・・　リードフレ
ーム、５・・・・・・　金属細線、６・・・・・・樹脂
、７・・・・・・絶縁性薄層体。 代理人の氏名　弁理士　中尾敏男　ばか１名第１図 第２図 １２、り６７− 第３図 第４図 ５７ど　　６ ＼　　　　＼　　　＼　　　　　　　　　　　　　　　
　　。1 and 2 are a plan view and a sectional view of an embodiment of the present invention, and FIGS. 3 and 4 are a plan view and a sectional view showing an outline of a conventional device. 1... Chip mounting tab, 2... Chip, 3... Electrode, 4... Lead frame, 5... Thin metal wire, 6 ... Resin, 7 ... Insulating thin layer body. Name of agent Patent attorney Toshio Nakao One idiot Figure 1 Figure 2 12, 67- Figure 3 Figure 4 57 6 \ \ \
.

Claims (1)

【特許請求の範囲】[Claims] 樹脂により封止された内部リードを半導体チップ上まで
延長し、かつ、前記半導体チップとの間に絶縁性薄層体
を介在させたことを特徴とする樹脂封止型半導体装置。1. A resin-sealed semiconductor device, characterized in that internal leads sealed with resin extend above a semiconductor chip, and an insulating thin layer is interposed between the leads and the semiconductor chip.
JP14082186A 1986-06-17 1986-06-17 Resin-sealed semiconductor device Pending JPS62296528A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14082186A JPS62296528A (en) 1986-06-17 1986-06-17 Resin-sealed semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14082186A JPS62296528A (en) 1986-06-17 1986-06-17 Resin-sealed semiconductor device

Publications (1)

Publication Number Publication Date
JPS62296528A true JPS62296528A (en) 1987-12-23

Family

ID=15277503

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14082186A Pending JPS62296528A (en) 1986-06-17 1986-06-17 Resin-sealed semiconductor device

Country Status (1)

Country Link
JP (1) JPS62296528A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS647628A (en) * 1987-06-30 1989-01-11 Hitachi Ltd Semiconductor device and manufacture thereof
JPH0250438A (en) * 1988-08-12 1990-02-20 Hitachi Ltd Semiconductor device
JPH08241953A (en) * 1996-03-21 1996-09-17 Hitachi Ltd Semiconductor device
JPH08241905A (en) * 1996-03-21 1996-09-17 Hitachi Ltd Semiconductor device
JPH08274243A (en) * 1996-03-21 1996-10-18 Hitachi Ltd Semiconductor device

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS647628A (en) * 1987-06-30 1989-01-11 Hitachi Ltd Semiconductor device and manufacture thereof
JPH0250438A (en) * 1988-08-12 1990-02-20 Hitachi Ltd Semiconductor device
JPH08241953A (en) * 1996-03-21 1996-09-17 Hitachi Ltd Semiconductor device
JPH08241905A (en) * 1996-03-21 1996-09-17 Hitachi Ltd Semiconductor device
JPH08274243A (en) * 1996-03-21 1996-10-18 Hitachi Ltd Semiconductor device

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