JPS611042A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS611042A
JPS611042A JP59121486A JP12148684A JPS611042A JP S611042 A JPS611042 A JP S611042A JP 59121486 A JP59121486 A JP 59121486A JP 12148684 A JP12148684 A JP 12148684A JP S611042 A JPS611042 A JP S611042A
Authority
JP
Japan
Prior art keywords
semiconductor device
leads
semiconductor chip
lead
internal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP59121486A
Other languages
Japanese (ja)
Inventor
Kenji Minami
健治 南
Masaru Katagiri
優 片桐
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP59121486A priority Critical patent/JPS611042A/en
Publication of JPS611042A publication Critical patent/JPS611042A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495Lead-frames or other flat leads
    • H01L23/49541Geometry of the lead-frame
    • H01L23/49548Cross section geometry
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8538Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/85385Shape, e.g. interlocking features
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation

Abstract

PURPOSE:To eliminate the exfoliation of a sealer by improving the sealability of the sealer by utilizing the variation in the thickness of internal leads, thereby eliminating the removal of external leads. CONSTITUTION:A semiconductor chip 1 is die bonded to a bed 2 of a lead frame, internal leads 20 arranged around the bed 2 are connected with electrodes through metal wirings 7 on the chip 1, and sealed by thermosetting resin 8. External leads 21 continued to the leads 20 are formed out of the resin 8. In this case, a recess 22 is formed on the leads 20. Recesses and projections may be alternately formed on both ends of the leads 20 instead of the recess 22, and a projection may be formed on the leads 20. The above recess or projection is engaged with the resin at the inner leads to increase the contacting area. Accordingly, the leads are hardly removed, and moisture is hardly invaded.

Description

【発明の詳細な説明】 (発明の技術分野〕 本発明は半導体装置に係り、特に樹脂封止パッケージ、
低融点ガラス封止パッケージ等の14止型外囲器を備え
たものに関する。
DETAILED DESCRIPTION OF THE INVENTION (Technical Field of the Invention) The present invention relates to a semiconductor device, and particularly to a resin-sealed package,
It relates to a package with a 14-stop type envelope such as a low melting point glass sealed package.

〔発明の技術的背景とその問題点〕[Technical background of the invention and its problems]

半導体装置の外囲器としては、す゛−ドフレームを用い
半導体チップとのワイヤボンディングを行った後封止を
行う封止型のものが品質と信頼性の向上と相俟って従来
セラミックパッケージを使用していた分野にも広く使用
されるようになっている。封止型のパッケージには、ワ
イヤボンディング完了後のリードフレームを型の中に入
れ熱硬化性プラスチック樹脂でモールドする樹脂封止型
のものと、セラミック基板の上に搭載したワイヤボンデ
ィング後の集積回路チップを低融点ガラスで封止しキャ
ップで被うサーディツプパッケージがあり、後者は特に
大電流の流れるチップに適用される。
As the envelope for semiconductor devices, the sealed type, which uses a wood frame and performs wire bonding with the semiconductor chip and then seals it, has improved in quality and reliability, and has replaced conventional ceramic packages. It has come to be widely used in the fields where it was previously used. Sealed packages include resin sealed packages in which the lead frame after wire bonding is placed in a mold and molded with thermosetting plastic resin, and resin sealed packages in which the wire bonded integrated circuit is mounted on a ceramic substrate. There is a cerdip package in which the chip is sealed with low-melting glass and covered with a cap, and the latter is especially applicable to chips that carry large currents.

これらの封止型パッケージでは封止が完全に行われで外
部リードの抜けがなく、また外部リードと封止材の境界
部にはがれ等による空隙が発生しないことが要求される
These sealed packages are required to be completely sealed so that the external leads do not come off, and that no voids are formed at the boundary between the external leads and the sealing material due to peeling or the like.

すなわち、半導体装置は第5図の断面図に示すように集
積回路チップ1はリードフレームのベッド部2に導電性
接着剤3等によりダイボンディングされており、ベッド
部2の周囲に配設された内    ゛部リード4と集積
回路チップ1上の電極6とは金またはアルミニウム等の
金属ワイヤ7で接続されており、これらは熱硬化性樹脂
8により封止されている。この樹脂封止体の外部に延出
したリードは外部リードと称され、例えばプリント基板
との接続に使用される。
That is, as shown in the cross-sectional view of FIG. 5, in the semiconductor device, an integrated circuit chip 1 is die-bonded to a bed portion 2 of a lead frame using a conductive adhesive 3 or the like, and is arranged around the bed portion 2. The internal leads 4 and the electrodes 6 on the integrated circuit chip 1 are connected by metal wires 7 made of gold, aluminum, etc., and these are sealed with a thermosetting resin 8. The leads extending outside the resin sealing body are called external leads and are used, for example, for connection to a printed circuit board.

近年、樹脂封止技術は著しく改善され、信頼性が向上し
ているが、それでもリードと樹脂との密着性が悪かった
り、両者の熱#服率が著しく相違した場合には第5図に
示すようにはがれ9が生じこのためリード4.5が抜け
やすくなり、またこのはがれ9部を通じて空気中の水分
が外囲器内部に侵入し半導体装置の信頼性を著しく低下
させる。
In recent years, resin sealing technology has been significantly improved and its reliability has improved, but if the adhesion between the lead and the resin is still poor, or if the heat absorption rate of the two is significantly different, as shown in Figure 5. As a result, the leads 4.5 are likely to come off, and moisture in the air can enter the envelope through the peeled portions 9, significantly reducing the reliability of the semiconductor device.

このため、リード抜けを防止し、耐湿性を向上させる目
的で内部リードの形状について種々の提案がなされてい
る。
For this reason, various proposals have been made regarding the shape of the internal leads in order to prevent the leads from coming off and improve moisture resistance.

第6図は従来の内部リード4の形状を示す平面図であっ
て、第6図(a)は内部リードに丸穴11を開孔させた
もの、第6図(b)は突起部12を設けたもの、第6図
(C)は切欠き部13を設けたもの、第6図1)は屈曲
部14を設けたものである。このような形状の採用によ
り樹脂とリードの密着性が向上し引張強度および耐湿性
の向上を図ることができる。
FIG. 6 is a plan view showing the shape of a conventional internal lead 4, in which FIG. 6(a) shows a circular hole 11 formed in the internal lead, and FIG. The one shown in FIG. 6(C) is provided with a notch 13, and the one shown in FIG. 6(C) is provided with a bent portion 14. By adopting such a shape, the adhesion between the resin and the lead can be improved, and tensile strength and moisture resistance can be improved.

しかしながら、このような形状を採用しても特に耐湿性
に関しては不充分な場合がある。また、半導体装置の高
集積化に伴ない、内部リードの幅についての制限が厳し
くなっており、特に第6図(b)および(d)のような
形状を採用することは困難である。
However, even if such a shape is adopted, the moisture resistance may be insufficient. Furthermore, with the increase in the degree of integration of semiconductor devices, restrictions on the width of internal leads have become stricter, and it is particularly difficult to adopt the shapes shown in FIGS. 6(b) and 6(d).

〔発明の目的〕[Purpose of the invention]

本発明は上記事情に鑑みてなされたもので、リードの抜
けがなく、また、耐湿性のすぐれた半導体装置を提供す
ることを目的とする。
The present invention has been made in view of the above circumstances, and it is an object of the present invention to provide a semiconductor device that prevents leads from falling out and has excellent moisture resistance.

〔発明の概要) 上記目的達成のため、本発明においては半導体チップと
、この半導体チップの周囲に配設されて前記半導体チッ
プと接続され、かつ前記半導体チップとの接続部分以外
に厚さが変化する部分を設けた内部リードと、この内部
リードおよび前記集積回路チップを気密状態で封止する
封止体と、この封止体から外部に延出し、前記内部リー
ドと連続した外部リードと、を備えた半導体装置を備え
ており、耐湿性の優れた高集積化半導体装置を得ること
ができるものである。
[Summary of the Invention] In order to achieve the above object, the present invention includes a semiconductor chip, a semiconductor chip that is disposed around the semiconductor chip, is connected to the semiconductor chip, and has a thickness that changes at a portion other than the connection portion with the semiconductor chip. an internal lead provided with a portion that connects the internal lead; a sealing body that hermetically seals the internal lead and the integrated circuit chip; and an external lead that extends outward from the sealing body and is continuous with the internal lead. A highly integrated semiconductor device with excellent moisture resistance can be obtained.

また、他の本発明においては、半導体チップと、この半
導体チップの周囲に配設されて前記半導体チップと接続
され、かつ前記半導体チップとの接続部分以外に幅およ
び厚さが変化する部分を設けた内部リードと、を備えて
おり、耐湿性のさらに優れた半導体装置を得ることがで
きるものである。
Further, in another aspect of the present invention, a semiconductor chip and a portion disposed around the semiconductor chip and connected to the semiconductor chip and whose width and thickness vary other than the connecting portion with the semiconductor chip are provided. The semiconductor device is equipped with internal leads that are resistant to moisture, thereby making it possible to obtain a semiconductor device with even better moisture resistance.

(発明の実施例) 以下、図面を参照しながら本発明の実施例のいくつかを
詳細に説明する。
(Embodiments of the Invention) Hereinafter, some embodiments of the present invention will be described in detail with reference to the drawings.

第1図は本発明にかかる半導体装置の構成を示す断面図
であって、第5図と同様、半導体チップ1はリードフレ
ームのベッド部2に導電性接着剤3等によりダイボンデ
ィングされ、ベッド部2の周囲に配設された内部リード
20は半導体デツプ1上の電極6と金属ワイヤ7により
接続されており、これらは熱硬化性樹脂8により封止さ
れている。樹脂8外には内部リード20に連続した外部
リード21が設けられている。この実施例においては内
部リード20に凹部22が形成されている。
FIG. 1 is a cross-sectional view showing the structure of a semiconductor device according to the present invention. Similar to FIG. 5, a semiconductor chip 1 is die-bonded to a bed portion 2 of a lead frame with a conductive adhesive 3, An internal lead 20 disposed around the semiconductor chip 2 is connected to an electrode 6 on the semiconductor depth 1 by a metal wire 7, and these are sealed with a thermosetting resin 8. Outside the resin 8, an external lead 21 continuous to the internal lead 20 is provided. In this embodiment, a recess 22 is formed in the internal lead 20.

この凹部22はリード厚250μに対し50μ程度であ
る。
This recess 22 has a thickness of about 50 μm with respect to a lead thickness of 250 μm.

第2図および第3図は他の実施例を示す断面図であって
、内部リード部分を中心にして描いである。
FIGS. 2 and 3 are sectional views showing other embodiments, and are drawn centering on the internal lead portion.

第2図においては内部リード20の両面に凹部22およ
び23が交互に形成されている。
In FIG. 2, recesses 22 and 23 are alternately formed on both sides of the internal lead 20.

このような凹部は各種の方法で形成することができるが
、一般的にはリードフレームをプレスで打抜く際に型を
用いたコイニングを行う方法と、エツチングでリードフ
レームを抜く際に所望部分をさらにエツチングする方法
が採用される。
Such recesses can be formed by various methods, but generally speaking, coining is performed using a mold when punching the lead frame with a press, and etching is used to form the desired portion when punching out the lead frame. Further, a method of etching is employed.

第3図は内部リード20上に凸部24を設けて厚さを変
化させたものである。この凸部24はめつき、溶射等に
より金属を付着させることによって形成される。
In FIG. 3, a convex portion 24 is provided on the internal lead 20 to change the thickness. The convex portion 24 is formed by attaching metal by plating, thermal spraying, or the like.

以上のような凹部あるいは凸部は樹脂と内部リードをか
み合わせ、また接触面積を増大させるから、リードは抜
けにくくなり、水分が侵入しにくくなって耐湿性が向上
する。
The recesses or protrusions described above engage the resin and the internal leads and increase the contact area, making it difficult for the leads to come off and for moisture to enter, improving moisture resistance.

第4図は本発明にかかる半導体装置に使用される内部リ
ード300種々の実施例の構成を示す平面図であって、
断面形状は第2図に示したものであるとして描いである
。第4図(a)では厚さの変化と共にリード幅を変化さ
せる切欠き部31を有している。また第4図(b)では
突起部32、第4図(C)では円形孔33が設けられリ
ード幅を変化させている。第4図(d)においては内部
リード30自体が屈曲部34を有しており、リード幅に
対し、見かけのリード幅を増大させている。
FIG. 4 is a plan view showing the configuration of various embodiments of the internal lead 300 used in the semiconductor device according to the present invention,
The cross-sectional shape is drawn as shown in FIG. In FIG. 4(a), there is a notch 31 that changes the lead width as the thickness changes. Further, a protrusion 32 is provided in FIG. 4(b), and a circular hole 33 is provided in FIG. 4(c) to change the lead width. In FIG. 4(d), the internal lead 30 itself has a bent portion 34, increasing the apparent lead width relative to the lead width.

このように厚さ変化と幅変化を共に有する内部リードで
は、樹脂と内部リードの接触面積がさらに増大するため
耐湿性をさらに向上させることができる。
With the internal lead having both thickness and width changes in this manner, the contact area between the resin and the internal lead is further increased, so that the moisture resistance can be further improved.

以上の実施例においては、樹脂封止型の半導体装置につ
いて説明したが、低融ガラスにより封止が行われるいわ
ゆるサーディツプパッケージにも適用することができる
In the above embodiments, a resin-sealed semiconductor device has been described, but the present invention can also be applied to a so-called cerdip package in which sealing is performed using low-melt glass.

また、厚さ変化部、幅変化部の形状は実施例に示したも
のの他あらゆる形状を採用することができ、それらの数
、大きさも適宜選択することができる。
Further, the shapes of the thickness changing portion and the width changing portion may be any shape other than those shown in the embodiments, and the number and size thereof may also be selected as appropriate.

さらに厚さ変化部は実施例ではリード幅全体にわたって
いるが、その必要は必ずしもなくリード幅の一部に厚さ
変化を設【プてもよい。
Further, although the thickness changing portion extends over the entire lead width in the embodiment, it is not necessary and the thickness changing portion may be provided in a part of the lead width.

〔発明の効果〕〔Effect of the invention〕

以上−のように、本発明においては内部リードの厚さ変
化を利用して封止体との密着性を向上させているので、
高集積化された封止型半導体装置においても外部リード
の抜けを招くことがなく、また封止体のはがれ等が生じ
ないことから耐湿性を向上させることができる。
As described above, in the present invention, the change in the thickness of the internal lead is used to improve the adhesion with the sealing body.
Even in highly integrated sealed semiconductor devices, external leads do not come off, and the sealing body does not peel off, so moisture resistance can be improved.

また、内部リードの厚さ変化部と幅変化部を併有する本
発明においては、封止体と内部リードの接触面積増大に
伴って外部リードの固定と耐湿性をさらに良好にするこ
とができる。
Further, in the present invention in which the inner lead has both a thickness changing portion and a width changing portion, the fixation and moisture resistance of the external lead can be further improved as the contact area between the sealing body and the internal lead is increased.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明にかかる半導体装置の構成を示す断面図
、第2図および第3図は他の実施例の内部リード部分を
示寸断面図、第4図は他の本発明にかかる半導体装置に
使用される内部リードの構成を示す平面図、第5図は従
来の半導体装置の構成と問題点を説明する断面図、第6
図は従来の半導体装置に使用される内部リードを示す平
面図である。 1・・・半導体チップ、2・・・ベッド部、4,20゜
30・・・内部リード、5.21・・・外部リード、2
2.23・・・凹部、24・・・凸部、13.31・・
・切欠き部、12.32・・・突起部、11.33・・
・円形孔、14.34・・・屈曲部。
FIG. 1 is a sectional view showing the structure of a semiconductor device according to the present invention, FIGS. 2 and 3 are sectional views showing internal lead portions of other embodiments, and FIG. 4 is a sectional view showing the structure of a semiconductor device according to another embodiment. FIG. 5 is a plan view showing the structure of internal leads used in the device; FIG. 5 is a cross-sectional view explaining the structure and problems of a conventional semiconductor device; FIG.
The figure is a plan view showing an internal lead used in a conventional semiconductor device. DESCRIPTION OF SYMBOLS 1... Semiconductor chip, 2... Bed part, 4, 20°30... Internal lead, 5.21... External lead, 2
2.23... Concave portion, 24... Convex portion, 13.31...
・Notch part, 12.32... Protrusion part, 11.33...
・Circular hole, 14.34...bent part.

Claims (1)

【特許請求の範囲】 1、半導体チップと、この半導体チップの周囲に配設さ
れて前記半導体チップと接続され、かつ前記半導体チッ
プとの接続部分以外に厚さが変化する部分を設けた内部
リードと、この内部リードおよび前記集積回路チップを
気密状態で封止する封止体と、この封止体から外部に延
出し、前記内部リードと連続した外部リードと、を備え
た半導体装置。 2、厚さ変化部分が凹部である特許請求の範囲第1項記
載の半導体装置。 3、凹部が内部リードの両面に形成されたものである特
許請求の範囲第2項記載の半導体装置。 4、凹部がコイニングにより形成されたものである特許
請求の範囲第2項記載の半導体装置。 5、厚さ変化部分が凸部である特許請求の範囲第1項記
載の半導体装置の外囲器。 6、凸部が内部リードの両面に形成されたものである特
許請求の範囲第5項記載の半導体装置。 7、凸部がめっきにより形成されたものである特許請求
の範囲第5項記載の半導体装置。 8、半導体チップと、この半導体チップの周囲に配設さ
れて前記半導体チップと接続され、かつ前記半導体チッ
プとの接続部分以外に幅および厚さが変化する部分を設
けた内部リードと、この内部リードおよび前記半導体チ
ップを気密状態で封止する封止体と、この封止体から外
部に延出し、前記内部リードと連続した外部リードと、
を備えた半導体装置。 9、幅変化部分が内部リードに形成された貫通孔である
特許請求の範囲第8項記載の半導体装置。 10、幅変化部分が切欠き部である特許請求の範囲第8
項記載の半導体装置。 11、幅変化部分が突起部である特許請求の範囲第8項
記載の半導体装置。 12、幅変化部分が屈曲部である特許請求の範囲第8項
記載の半導体装置。 13、厚さ変化部分が凹部である特許請求の範囲第8項
ないし第12項のいずれかの半導体装置。 14、厚さ変化部分が凸部である特許請求の範囲第8項
ないし第12項のいずれかの半導体装置。
[Claims] 1. A semiconductor chip, and an internal lead disposed around the semiconductor chip, connected to the semiconductor chip, and having a portion whose thickness changes other than the connection portion with the semiconductor chip. A semiconductor device comprising: a sealing body that hermetically seals the internal leads and the integrated circuit chip; and an external lead extending outward from the sealing body and continuous with the internal leads. 2. The semiconductor device according to claim 1, wherein the thickness changing portion is a recess. 3. The semiconductor device according to claim 2, wherein the recesses are formed on both sides of the internal lead. 4. The semiconductor device according to claim 2, wherein the recess is formed by coining. 5. The envelope for a semiconductor device according to claim 1, wherein the thickness changing portion is a convex portion. 6. The semiconductor device according to claim 5, wherein the convex portions are formed on both sides of the internal lead. 7. The semiconductor device according to claim 5, wherein the convex portion is formed by plating. 8. A semiconductor chip, an internal lead disposed around the semiconductor chip, connected to the semiconductor chip, and having a portion whose width and thickness vary other than the connection portion with the semiconductor chip; a sealing body that hermetically seals the leads and the semiconductor chip; an external lead extending outward from the sealing body and continuous with the inner lead;
A semiconductor device equipped with 9. The semiconductor device according to claim 8, wherein the width changing portion is a through hole formed in the internal lead. 10. Claim 8 in which the width changing portion is a notch portion
1. Semiconductor device described in Section 1. 11. The semiconductor device according to claim 8, wherein the width changing portion is a protrusion. 12. The semiconductor device according to claim 8, wherein the width changing portion is a bent portion. 13. The semiconductor device according to any one of claims 8 to 12, wherein the thickness changing portion is a recess. 14. The semiconductor device according to any one of claims 8 to 12, wherein the thickness changing portion is a convex portion.
JP59121486A 1984-06-13 1984-06-13 Semiconductor device Pending JPS611042A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59121486A JPS611042A (en) 1984-06-13 1984-06-13 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59121486A JPS611042A (en) 1984-06-13 1984-06-13 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS611042A true JPS611042A (en) 1986-01-07

Family

ID=14812348

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59121486A Pending JPS611042A (en) 1984-06-13 1984-06-13 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS611042A (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02137251A (en) * 1988-11-17 1990-05-25 Nec Corp Semiconductor device
WO1999000826A2 (en) 1997-06-27 1999-01-07 Matsushita Electronics Corporation Resin molded type semiconductor device and a method of manufacturing the same
US6861735B2 (en) 1997-06-27 2005-03-01 Matsushita Electric Industrial Co., Ltd. Resin molded type semiconductor device and a method of manufacturing the same
JP2010021259A (en) * 2008-07-09 2010-01-28 Toshiba Corp Optical semiconductor device
JP2018064051A (en) * 2016-10-14 2018-04-19 株式会社トーキン Electric double-layer capacitor
WO2018096656A1 (en) * 2016-11-25 2018-05-31 三菱電機株式会社 Semiconductor device

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5129874A (en) * 1974-09-06 1976-03-13 Hitachi Ltd JUSHIFUSHIGATAHANDOTAISOCHI
JPS58119660A (en) * 1982-01-11 1983-07-16 Oki Electric Ind Co Ltd Semiconductor device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5129874A (en) * 1974-09-06 1976-03-13 Hitachi Ltd JUSHIFUSHIGATAHANDOTAISOCHI
JPS58119660A (en) * 1982-01-11 1983-07-16 Oki Electric Ind Co Ltd Semiconductor device

Cited By (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02137251A (en) * 1988-11-17 1990-05-25 Nec Corp Semiconductor device
WO1999000826A2 (en) 1997-06-27 1999-01-07 Matsushita Electronics Corporation Resin molded type semiconductor device and a method of manufacturing the same
WO1999000826A3 (en) * 1997-06-27 1999-05-27 Matsushita Electronics Corp Resin molded type semiconductor device and a method of manufacturing the same
US6861735B2 (en) 1997-06-27 2005-03-01 Matsushita Electric Industrial Co., Ltd. Resin molded type semiconductor device and a method of manufacturing the same
US6900524B1 (en) 1997-06-27 2005-05-31 Matsushita Electric Industrial Co., Ltd. Resin molded semiconductor device on a lead frame and method of manufacturing the same
US7538416B2 (en) 1997-06-27 2009-05-26 Panasonic Corporation Resin molded type semiconductor device and a method of manufacturing the same
JP2010021259A (en) * 2008-07-09 2010-01-28 Toshiba Corp Optical semiconductor device
JP2018064051A (en) * 2016-10-14 2018-04-19 株式会社トーキン Electric double-layer capacitor
US10566146B2 (en) 2016-10-14 2020-02-18 Tokin Corporation Electric double-layer capacitor including a terminal having a protruding portion in an exterior body thereof
WO2018096656A1 (en) * 2016-11-25 2018-05-31 三菱電機株式会社 Semiconductor device
JPWO2018096656A1 (en) * 2016-11-25 2019-04-11 三菱電機株式会社 Semiconductor device
CN110024118A (en) * 2016-11-25 2019-07-16 三菱电机株式会社 Semiconductor device
US10763183B2 (en) 2016-11-25 2020-09-01 Mitsubishi Electric Corporation Semiconductor device

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