JPH09181223A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH09181223A
JPH09181223A JP34017195A JP34017195A JPH09181223A JP H09181223 A JPH09181223 A JP H09181223A JP 34017195 A JP34017195 A JP 34017195A JP 34017195 A JP34017195 A JP 34017195A JP H09181223 A JPH09181223 A JP H09181223A
Authority
JP
Japan
Prior art keywords
substrate
sealing resin
wiring pattern
semiconductor device
bonding wire
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP34017195A
Other languages
Japanese (ja)
Inventor
Hiroshi Nishida
浩 西田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Priority to JP34017195A priority Critical patent/JPH09181223A/en
Publication of JPH09181223A publication Critical patent/JPH09181223A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H01L2224/48228—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item the bond pad being disposed in a recess of the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48235—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a via metallisation of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Abstract

PROBLEM TO BE SOLVED: To enhance the bond properties of a sealing resin by providing bond regions bringing a substrate and the sealing region into direct contact with one another in the regions outside the connecting parts of the bonding wires but inside the peripheries of the substrate. SOLUTION: A chip element 3 is mounted on almost the central part of a substrate 2 while wiring patterns 4 in a specific shape are formed from almost the central part on the substrate 2 to the peripheries thereof. Next, the wiring patterns 4 and the chip element 3 are connected by bonding wires 5 and then bonding regions S bringing the substrate 2 and a sealing region 7 into direct contact with each other. Through these procedures, the bond properties of the sealing resin 7 can be enhanced even if the sealing resin 7 is released from the substrate 2 due to the thermal shock or with the change over aging.

Description

【発明の詳細な説明】Detailed Description of the Invention

【０００１】[0001]

【発明の属する技術分野】本発明は、基板上に搭載され
た素子と配線パターンとをボンディングワイヤーで接続
し、これらを封止樹脂にて一体封止してパッケージを構
成する半導体装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device in which an element mounted on a substrate and a wiring pattern are connected by a bonding wire and these are integrally sealed with a sealing resin to form a package.

【０００２】[0002]

【従来の技術】図２は従来の半導体装置を説明する概略
図であり、ＯＭＰＡＣ（Ｏｖｅｒ Ｍｏｌｄｅｄ Ｐａ
ｄ Ｇｒｉｄ Ａｒｒａｙ）型またはプラスティックＢ
ＧＡ（Ｂａｌｌ Ｇｒｉｄ Ａｒｒａｙ）型のパッケー
ジを構成するものを示している。2. Description of the Related Art FIG. 2 is a schematic diagram for explaining a conventional semiconductor device, which is an OMPAC (Over Molded Pa).
d Grid Array) or plastic B
The figure shows a component of a GA (Ball Grid Array) type package.

【０００３】すなわち、図２（ａ）の断面図に示すよう
に、この半導体装置１’は、エポキシ系の基板２の略中
央（ダイパッド部）に搭載されるチップ状の素子３と、
基板２上の略中央から周辺に向けて形成された所定形状
の配線パターン４と、素子３と配線パターン４とを接続
するボンディングワイヤー５と、配線パターン４のボン
ディングワイヤー５の接続部分４ａを除く表面に形成さ
れた保護膜であるソルダーレジスト６と、基板２上にお
いて素子３やボンディングワイヤー５を一体封止する封
止樹脂７とから構成されてる。That is, as shown in the sectional view of FIG. 2 (a), this semiconductor device 1'includes a chip-shaped element 3 mounted on the epoxy-based substrate 2 at substantially the center (die pad portion) thereof.
Except for a wiring pattern 4 having a predetermined shape formed from the substantial center of the substrate 2 toward the periphery, a bonding wire 5 for connecting the element 3 and the wiring pattern 4, and a connecting portion 4a of the bonding wire 5 of the wiring pattern 4. It is composed of a solder resist 6, which is a protective film formed on the surface, and a sealing resin 7, which integrally seals the element 3 and the bonding wire 5 on the substrate 2.

【０００４】また、基板２の下側には配線パターン４と
導通するはんだボール８がアレイ状に取り付けられてい
る。これにより、半導体装置１’を実装用基板（図示せ
ず）上に載置し、所定の熱を加えることによってはんだ
ボール８を溶融し、固化することで、半導体装置１’の
実装と電気的接続とを同時に行うようにしている。On the lower side of the substrate 2, solder balls 8 which are electrically connected to the wiring pattern 4 are attached in an array. As a result, the semiconductor device 1'is mounted on a mounting substrate (not shown), and the solder balls 8 are melted and solidified by applying a predetermined heat, so that the semiconductor device 1'is mounted and electrically connected. I try to connect and connect at the same time.

【０００５】ところで、配線パターン４のボンディング
ワイヤー５の接続部分４ａを除く表面に形成されたソル
ダーレジスト６は、銅等の金属から成る配線パターン４
の表面酸化等を防止する一種の絶縁性のインクであり、
１０〜５０μｍ程度の厚さで塗布されている。By the way, the solder resist 6 formed on the surface of the wiring pattern 4 excluding the connecting portion 4a of the bonding wire 5 has a wiring pattern 4 made of a metal such as copper.
It is a kind of insulating ink that prevents surface oxidation of
It is applied in a thickness of about 10 to 50 μm.

【０００６】図２（ｂ）の平面図は、説明を分かりやす
くするため封止樹脂７を除いた状態（外形線のみ破線で
表示）を示しているが、図に示されるように、ソルダー
レジスト６は、ボンディングワイヤー５の接続部分４ａ
を除く基板２上のほぼ全体にわたり塗布されている。The plan view of FIG. 2B shows the state (only the outline is shown by a broken line) without the sealing resin 7 for the sake of easy understanding, but as shown in the figure, the solder resist is used. 6 is a connecting portion 4a of the bonding wire 5
It is applied almost all over the substrate 2 except.

【０００７】[0007]

【発明が解決しようとする課題】しかし、このような半
導体装置においては、上述したソルダーレジストと封止
樹脂との密着性が非常に悪い。このため、例えば封止樹
脂の形成工程で、所定の金型内に封止樹脂を注入した
後、その金型を開く際に封止樹脂が金型とともに基板か
ら剥離してしまうという問題が生じる。However, in such a semiconductor device, the adhesion between the solder resist and the sealing resin is extremely poor. Therefore, for example, in the step of forming the sealing resin, after the sealing resin is injected into a predetermined mold, the sealing resin is separated from the substrate together with the mold when the mold is opened. .

【０００８】図３は剥離の状態を示す概略断面図であ
る。つまり、ソルダーレジスト６と封止樹脂７との密着
力が低いために、図中矢印Ａで示す周縁部分から封止樹
脂７が容易に剥がれてしまう。この剥離は、金型を開く
場合のみならず、製造工程中の熱衝撃や、その後の経時
変化によっても生じ、ここからのダストおよび水分侵入
等による半導体装置１’の信頼性低下の要因となってい
る。FIG. 3 is a schematic sectional view showing a peeled state. That is, since the adhesive force between the solder resist 6 and the sealing resin 7 is low, the sealing resin 7 is easily peeled off from the peripheral edge portion indicated by the arrow A in the figure. This peeling occurs not only when the mold is opened, but also due to thermal shock during the manufacturing process and subsequent aging, which becomes a factor of reducing the reliability of the semiconductor device 1 ′ due to dust and moisture intrusion from here. ing.

【０００９】[0009]

【課題を解決するための手段】本発明はこのような課題
を解決するために成された半導体装置である。すなわ
ち、本発明は、基板上の略中央に搭載されるチップ状の
素子と、基板上の略中央から周辺に向けて形成される配
線パターンと、素子と配線パターンとを接続するボンデ
ィングワイヤーと、配線パターンの表面を保護する保護
膜と、基板上において素子、配線パターンおよびボンデ
ィングワイヤーを一体封止する封止樹脂とを備えた半導
体装置であり、配線パターン上のボンディングワイヤー
の接続部分より外側で、基板の周縁より手前の領域に、
基板と封止樹脂とが直接接触する密着領域を備えた構成
となっている。The present invention is a semiconductor device made to solve the above problems. That is, the present invention is a chip-shaped element mounted substantially in the center on the substrate, a wiring pattern formed from the substantially center on the substrate toward the periphery, and a bonding wire connecting the element and the wiring pattern, A semiconductor device comprising a protective film that protects the surface of a wiring pattern and a sealing resin that integrally seals an element, a wiring pattern, and a bonding wire on a substrate, and is outside the connection portion of the bonding wire on the wiring pattern. , In the area before the edge of the board,
It is configured to have a contact region where the substrate and the sealing resin are in direct contact with each other.

【００１０】この基板上の密着領域には、保護膜が形成
されていないため、封止樹脂と基板とが直接接触する状
態となる。これにより、保護膜を介して封止樹脂を形成
する場合に比べて封止樹脂の密着性が高まる。また、こ
の密着領域内には配線パターンが形成されているため、
基板との間の凹凸に封止樹脂が入り込む状態となってさ
らに密着性が高まることになる。Since the protective film is not formed on the adhesion region on the substrate, the sealing resin and the substrate are in direct contact with each other. As a result, the adhesion of the sealing resin is enhanced as compared with the case where the sealing resin is formed via the protective film. Further, since the wiring pattern is formed in this adhesion region,
The sealing resin enters into the irregularities between the substrate and the substrate, and the adhesion is further enhanced.

【００１１】[0011]

【発明の実施の形態】以下に、本発明の半導体装置にお
ける実施の形態を図に基づいて説明する。図１は本発明
の半導体装置における実施形態を説明する概略断面図
で、（ａ）は断面図、（ｂ）は平面図である。なお、説
明を分かりやすくするため、図１（ｂ）では封止樹脂７
を除いた状態（外形線のみ破線で表示）が示されてい
る。BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of a semiconductor device of the present invention will be described below with reference to the drawings. 1A and 1B are schematic cross-sectional views illustrating an embodiment of a semiconductor device of the present invention. FIG. 1A is a cross-sectional view and FIG. 1B is a plan view. In addition, in order to make the explanation easy to understand, in FIG.
Is shown (only the outline is shown by a broken line).

【００１２】図１（ａ）に示すように、本実施形態にお
ける半導体装置１は、ＯＭＰＡＣ型またはプラスティッ
クＢＧＡ型のパッケージを備えたものであり、基板２の
略中央（ダイパッド部）に搭載されるチップ状の素子３
と、基板２上の略中央から周辺に向けて形成された所定
形状の配線パターン４と、素子３と配線パターン４とを
接続するボンディングワイヤー５と、配線パターン４の
基板周縁部分のみに形成された保護膜であるソルダーレ
ジスト６と、基板２上において素子３たボンディングワ
イヤー５を封止する封止樹脂７とから構成されてる。ま
た、基板２の下側には配線パターン４と導通するはんだ
ボール８がアレイ状に取り付けられている。As shown in FIG. 1A, the semiconductor device 1 in this embodiment is provided with an OMPAC type or plastic BGA type package, and is mounted on the substrate 2 at substantially the center (die pad portion). Chip-shaped element 3
A wiring pattern 4 having a predetermined shape formed from the substantial center of the substrate 2 toward the periphery; a bonding wire 5 connecting the element 3 and the wiring pattern 4; It is composed of a solder resist 6 which is a protective film and a sealing resin 7 which seals the bonding wire 5 formed on the substrate 2 on the substrate 2. Further, solder balls 8 that are electrically connected to the wiring pattern 4 are attached to the lower side of the substrate 2 in an array.

【００１３】特に、本実施形態における半導体装置１
は、ボンディングワイヤー５の接続部分４ａから基板２
の周縁より手前の領域にソルダーレジスト６の塗布され
ていない密着領域Ｓを備えている点に特徴がある。In particular, the semiconductor device 1 in this embodiment
Is from the connecting portion 4a of the bonding wire 5 to the substrate 2
It is characterized in that a contact region S where the solder resist 6 is not applied is provided in a region before the peripheral edge of the.

【００１４】図１（ｂ）の２点鎖線で示すように、密着
領域Ｓは、ボンディングワイヤー５の接続部分４ａより
外側で、基板２の周縁部分に設けられたソルダーレジス
ト６の手前位置まで設けられている。つまり、封止樹脂
７はこの密着領域Ｓにおいて基板２と直接接触する状態
となり、ソルダーレジスト６を介して封止樹脂７が形成
されている場合と比べてその密着力が大幅に向上するこ
とになる。As shown by the chain double-dashed line in FIG. 1 (b), the adhesion region S is provided outside the connection portion 4a of the bonding wire 5 and before the solder resist 6 provided on the peripheral portion of the substrate 2. Has been. That is, the sealing resin 7 is in a state of directly contacting the substrate 2 in the contact area S, and the adhesive force is significantly improved as compared with the case where the sealing resin 7 is formed via the solder resist 6. Become.

【００１５】一般に、基板２上のソルダーレジスト６を
介して封止樹脂７を形成した場合の接着強度は、基板２
上に直接封止樹脂７を形成した場合の接着強度に比べて
１０〜５０％程度となっている。したがって、本実施形
態のように密着領域Ｓを設けて基板２と封止樹脂７とが
直接接触する面積を増加させることにより、封止樹脂７
の密着力が向上し、剥離を防止できるようになる。Generally, the adhesive strength when the sealing resin 7 is formed via the solder resist 6 on the substrate 2 is
The adhesive strength is about 10 to 50% compared to the adhesive strength when the sealing resin 7 is directly formed thereon. Therefore, as in the present embodiment, by providing the adhesion region S to increase the area where the substrate 2 and the sealing resin 7 are in direct contact with each other, the sealing resin 7
The adhesive strength of is improved and peeling can be prevented.

【００１６】また、この密着領域Ｓ内には所定形状の配
線パターン４が形成されていることから、基板２と配線
パターン４とによって凹凸が形成される状態となる。本
実施形態における半導体装置１では、この凹凸部分に封
止樹脂７が入り込む状態となり、さらに密着力を高める
ことが可能となる。Further, since the wiring pattern 4 having a predetermined shape is formed in the close contact area S, the substrate 2 and the wiring pattern 4 form an unevenness. In the semiconductor device 1 according to the present embodiment, the sealing resin 7 enters the concave and convex portions, and the adhesion can be further increased.

【００１７】本実施形態における半導体装置１を製造す
るには、先ず、基板２上に所定の配線パターン４をエッ
チング等によって形成し、その後、先に説明した密着領
域Ｓを構成するようソルダーレジスト６を基板２の周縁
部分のみに塗布する。In order to manufacture the semiconductor device 1 in this embodiment, first, a predetermined wiring pattern 4 is formed on the substrate 2 by etching or the like, and then the solder resist 6 is formed so as to form the adhesion region S described above. Is applied only to the peripheral portion of the substrate 2.

【００１８】ソルダーレジスト６は、例えばスクリーン
印刷法によって塗布する。なお、基板２の周縁部分にソ
ルダーレジスト６を塗布するのは、基板２の周縁部分に
ある、後に形成する封止樹脂７の内部に入らない配線パ
ターン４の表面を酸化等から保護するためである。The solder resist 6 is applied, for example, by a screen printing method. The solder resist 6 is applied to the peripheral portion of the substrate 2 in order to protect the surface of the wiring pattern 4 in the peripheral portion of the substrate 2 that does not enter the sealing resin 7 to be formed later from oxidation or the like. is there.

【００１９】次に、基板２の略中央部（ダイパッド部）
にチップ状の素子３を銀ペースト剤等を介して搭載し、
所定の加熱によって硬化させる。その後、素子３と配線
パターン４の接続部分４ａとをボンディングワイヤー５
によって接続する。Next, the substantially central portion of the substrate 2 (die pad portion)
The chip-shaped element 3 is mounted on the
It is cured by predetermined heating. After that, the element 3 and the connection portion 4a of the wiring pattern 4 are bonded to each other by the bonding wire 5
Connect by.

【００２０】次いで、素子３の搭載およびボンディング
ワイヤー５による配線の完了した基板２を所定の金型に
挿入する。この金型にはキャビティが設けられ、キャビ
ティ内に封止したい素子３、ボンディングワイヤー５等
を配置しておく。Next, the substrate 2 on which the mounting of the element 3 and the wiring by the bonding wire 5 are completed is inserted into a predetermined mold. The mold is provided with a cavity, and the element 3 to be sealed, the bonding wire 5 and the like are arranged in the cavity.

【００２１】この状態でキャビティ内に熱硬化性の封止
樹脂７を充填し、所定の加熱によって硬化させる。そし
て、封止樹脂７が硬化した後に、金型を開けてパッケー
ジ化された半導体装置１を取り出す。この際、先に説明
したように、基板２上の密着領域Ｓにおいて基板２と封
止樹脂７とが直接接触し、その接着力が高まっているこ
とから、金型を開ける際に封止樹脂７を一緒に剥がして
しまうことがなくなる。In this state, the thermosetting sealing resin 7 is filled in the cavity and cured by predetermined heating. Then, after the sealing resin 7 is cured, the mold is opened and the packaged semiconductor device 1 is taken out. At this time, as described above, since the substrate 2 and the sealing resin 7 are in direct contact with each other in the contact area S on the substrate 2 and the adhesive force thereof is increased, the sealing resin is opened when the mold is opened. No more peeling 7 together.

【００２２】これにより、半導体装置１を製造した後
も、経時変化等による封止樹脂７の剥離は発生せず、実
装基板上への実装時、さらには実装後の使用状態におい
てもダストや水分の混入を防止できる半導体装置１を製
造できることになる。As a result, even after the semiconductor device 1 is manufactured, the sealing resin 7 is not peeled off due to a change with time, etc., and dust and moisture are not caused when the semiconductor device 1 is mounted on the mounting board and also in a usage state after mounting. It is possible to manufacture the semiconductor device 1 capable of preventing the mixture of

【００２３】[0023]

【発明の効果】以上説明したように、本発明の半導体装
置によれば次のような効果がある。すなわち、基板上に
設けた密着領域によって封止樹脂と基板とが直接接触す
る状態となり、封止樹脂の密着力を大幅に向上できるこ
とになる。これによって、製造工程中の熱衝撃や経時変
化等によっても封止樹脂が基板から剥離してしまうこと
がなくなり、ダストや水分等の侵入を確実に防止でき、
信頼性の高い半導体装置を提供できるようになる。As described above, the semiconductor device of the present invention has the following effects. That is, the adhesion region provided on the substrate brings the sealing resin and the substrate into direct contact with each other, and the adhesion force of the sealing resin can be significantly improved. This prevents the sealing resin from peeling off from the substrate due to thermal shock during the manufacturing process, aging, etc., and can reliably prevent dust, moisture, etc. from entering.
A highly reliable semiconductor device can be provided.

【図面の簡単な説明】[Brief description of the drawings]

【図１】本発明の半導体装置における実施形態を説明す
る概略図で、（ａ）は断面図、（ｂ）は平面図である。FIG. 1 is a schematic diagram illustrating an embodiment of a semiconductor device of the present invention, in which (a) is a sectional view and (b) is a plan view.

【図２】従来の半導体装置を説明する概略図で、（ａ）
は断面図、（ｂ）は平面図である。FIG. 2 is a schematic diagram illustrating a conventional semiconductor device, (a)
Is a sectional view, and (b) is a plan view.

【図３】封止樹脂の剥離の状態を示す概略断面図であ
る。FIG. 3 is a schematic cross-sectional view showing a peeled state of a sealing resin.

【符号の説明】[Explanation of symbols]

１ 半導体装置 ２ 基板 ３ 素子 ４ 配線パターン ４ａ 接続部分 ５ ボンディングワイヤー ６ ソルダーレジスト ７ 封止樹脂 ８ はんだボール Ｓ 密着領域 1 Semiconductor Device 2 Substrate 3 Element 4 Wiring Pattern 4a Connection Part 5 Bonding Wire 6 Solder Resist 7 Sealing Resin 8 Solder Ball S Adhesion Area

Claims (1)

【特許請求の範囲】[Claims] 【請求項１】 基板上の略中央に搭載されるチップ状の
素子と、該基板上の略中央から周辺に向けて形成される
配線パターンと、該素子と該配線パターンとを接続する
ボンディングワイヤーと、該配線パターンの表面を保護
する保護膜と、該基板上において該素子、該配線パター
ン、該ボンディングワイヤーを一体封止する封止樹脂と
を備えている半導体装置であって、 前記配線パターン上の前記ボンディングワイヤーの接続
部分より外側で、前記基板の周縁より手前の領域に、該
基板と前記封止樹脂とが直接接触する密着領域が設けら
れていることを特徴とする半導体装置。1. A chip-shaped element mounted substantially in the center of a substrate, a wiring pattern formed from the substantially center of the substrate toward the periphery, and a bonding wire connecting the element and the wiring pattern. And a protective film that protects the surface of the wiring pattern, and a sealing resin that integrally seals the element, the wiring pattern, and the bonding wire on the substrate. A semiconductor device, wherein an adhesion region where the substrate and the sealing resin are in direct contact with each other is provided outside the connection portion of the bonding wire above and in the region before the peripheral edge of the substrate.
JP34017195A 1995-12-27 1995-12-27 Semiconductor device Pending JPH09181223A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP34017195A JPH09181223A (en) 1995-12-27 1995-12-27 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP34017195A JPH09181223A (en) 1995-12-27 1995-12-27 Semiconductor device

Publications (1)

Publication Number Publication Date
JPH09181223A true JPH09181223A (en) 1997-07-11

Family

ID=18334419

Family Applications (1)

Application Number Title Priority Date Filing Date
JP34017195A Pending JPH09181223A (en) 1995-12-27 1995-12-27 Semiconductor device

Country Status (1)

Country Link
JP (1) JPH09181223A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002016193A (en) * 2000-06-30 2002-01-18 Mitsumi Electric Co Ltd Packaged semiconductor device and manufacturing method thereof
JP2012256842A (en) * 2011-05-13 2012-12-27 Sharp Corp Manufacturing method of semiconductor module and semiconductor module

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002016193A (en) * 2000-06-30 2002-01-18 Mitsumi Electric Co Ltd Packaged semiconductor device and manufacturing method thereof
JP2012256842A (en) * 2011-05-13 2012-12-27 Sharp Corp Manufacturing method of semiconductor module and semiconductor module
US9076892B2 (en) 2011-05-13 2015-07-07 Sharp Kabushiki Kaisha Method of producing semiconductor module and semiconductor module

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