JP2600689B2 - Hollow package for semiconductor device - Google Patents

Hollow package for semiconductor device

Info

Publication number
JP2600689B2
JP2600689B2 JP62167008A JP16700887A JP2600689B2 JP 2600689 B2 JP2600689 B2 JP 2600689B2 JP 62167008 A JP62167008 A JP 62167008A JP 16700887 A JP16700887 A JP 16700887A JP 2600689 B2 JP2600689 B2 JP 2600689B2
Authority
JP
Japan
Prior art keywords
lead
resin
resin substrate
package
hollow
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP62167008A
Other languages
Japanese (ja)
Other versions
JPS6411356A (en
Inventor
英治 小滝
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Priority to JP62167008A priority Critical patent/JP2600689B2/en
Publication of JPS6411356A publication Critical patent/JPS6411356A/en
Application granted granted Critical
Publication of JP2600689B2 publication Critical patent/JP2600689B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/301Electrical effects
    • H01L2924/30107Inductance

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、半導体装置用中空パッケージに関し、特に
リードインダクタンスの小さい高周波トランジスタ用パ
ッケージに関する。
Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a hollow package for a semiconductor device, and more particularly to a package for a high-frequency transistor having a small lead inductance.

〔発明の概要〕[Summary of the Invention]

本発明は、半導体装置用中空パッケージにおいて、半
導体チップとワイヤボンド部とが樹脂基板の上面に露出
されると共にリードがこの樹脂基板を貫通し、かつこの
樹脂基板の底面に沿ってリードの延長部が延在して露出
される如く樹脂モールドして、このリードと樹脂との界
面に沿って外部から浸入する水分の浸入経路及びリーク
パスを長くし、この樹脂基板の上面にこの半導体チップ
とワイヤボンド部とを保護する中空を有するキャップを
設けたものであって、インダクタンスが小さく、かつ耐
湿性に優れたパッケージである。
According to the present invention, in a hollow package for a semiconductor device, a semiconductor chip and a wire bond portion are exposed on an upper surface of a resin substrate, and a lead penetrates the resin substrate, and an extension of the lead extends along a bottom surface of the resin substrate. Is extended so as to be exposed, so that the infiltration path and leak path of moisture entering from the outside along the interface between the lead and the resin are lengthened, and the semiconductor chip and the wire bond are formed on the upper surface of the resin substrate. A package having a hollow cap for protecting the portion and having a small inductance and having excellent moisture resistance.

〔従来の技術〕[Conventional technology]

従来、高周波トランジスタのパッケージは、リード間
の容量が小さく、インピーダンスの小さい小型中空パッ
ケージが用いられていた。このパッケージは、第3図に
示すように基板材としてセラミックまたは樹脂を用い
る。この基板上に接着剤を用いてリードを接着し、この
リードの一端のタブに半導体チップを置載し、金属細線
を用いて他のリード先端部に接続する。その後、セラミ
ック製キャップを接着剤で接着する。接着剤は、パッケ
ージの気密性を保持するため、リークの少ない、低融点
ガラスや樹脂等が用いられる。また、リードの引抜き強
度を向上させるために、実公昭52−36536に示されてい
るように、中空モールド内部で凹状にリードを屈曲さ
せ、引抜き強度の改善をはかったものもある。
Conventionally, a small-sized hollow package having a small impedance between leads and a small impedance has been used for a package of a high-frequency transistor. This package uses ceramic or resin as a substrate material as shown in FIG. Leads are adhered on the substrate using an adhesive, a semiconductor chip is mounted on a tab at one end of the leads, and connected to the tip of another lead using a thin metal wire. Thereafter, the ceramic cap is bonded with an adhesive. As the adhesive, low-melting-point glass, resin, or the like with little leakage is used to maintain the airtightness of the package. In addition, as shown in Japanese Utility Model Publication No. 52-36536, in order to improve the pull-out strength of the lead, there is a method in which the lead is bent in a concave shape inside the hollow mold to improve the pull-out strength.

この高周波トランジスタをプリント基板等に実装する
には、パッケージの側面から導出されている外部リード
を、樹脂基板底面方向へ折り曲げ、プリント基板に半田
づけ等により取付ける。
To mount this high-frequency transistor on a printed circuit board or the like, external leads extending from the side of the package are bent toward the bottom surface of the resin substrate, and attached to the printed circuit board by soldering or the like.

〔本発明が解決しようとする問題点〕[Problems to be solved by the present invention]

しかしながら、近年、マイクロウーブ領域で使用され
る高周波トランジスタの寸法は、インダクタンスを極力
小さくするために、リードの長さを短くする必要があ
る。従来の中空パッケージにおいては、リードがパッケ
ージの側面から導出されて、外部リードの導出部を樹脂
基板底面方向へ折り曲げて使用するため、リードの長さ
を短くすることが困難であった。また、導出部での折り
曲げ時に力が加わるため、リードと樹脂の界面に歪を生
じ、耐湿性が低下する恐れがあった。
However, in recent years, the size of a high-frequency transistor used in a microwave region requires a reduction in the length of a lead in order to minimize inductance. In the conventional hollow package, the lead is led out from the side surface of the package, and the lead-out portion of the external lead is used by being bent toward the bottom surface of the resin substrate. Therefore, it has been difficult to shorten the length of the lead. In addition, since a force is applied at the time of bending at the lead-out portion, distortion may occur at the interface between the lead and the resin, and the moisture resistance may be reduced.

〔問題点を解決するための手段〕[Means for solving the problem]

本発明は、前記問題点を解決するために、半導体チッ
プとワイヤボンド部とが樹脂基板の上面に露出されると
共にリードがこの樹脂基板を貫通し、かつこの樹脂基板
の底面に沿って、このリードの延長部が延在して露出さ
れる如く樹脂モールドして、このリードと樹脂との界面
に沿って外部から浸入する水分の浸入経路及びリークパ
スを長くし、この樹脂基板の上面にこの半導体チップと
ワイヤボンド部とを保護する中空を有するキャップを設
けたものである。
According to the present invention, in order to solve the above problems, the semiconductor chip and the wire bond portion are exposed on the upper surface of the resin substrate, and the leads penetrate the resin substrate, and along the bottom surface of the resin substrate, The resin is molded so that the extended portion of the lead extends and is exposed, and the length of the infiltration path and leak path of moisture entering from the outside along the interface between the lead and the resin is increased. A cap having a hollow for protecting the chip and the wire bond portion is provided.

〔作用〕[Action]

本発明によれば、外部リードを樹脂基板底面から取り
出すことにより、リードの長さを短くすることが出来
る。かつ、内部リードは樹脂基板内を貫通しているた
め、リードと樹脂の界面に沿って外部から浸入する水分
の浸入経路、すなわちリークパスを長くすることが出来
る。このことによってインダクタンスが小さく、かつ耐
湿性の優れた高周波トランジスタ用中空パッケージを実
現することが出来る。
According to the present invention, by taking out the external leads from the bottom surface of the resin substrate, the length of the leads can be reduced. In addition, since the internal lead penetrates through the resin substrate, it is possible to lengthen a path of moisture entering from the outside along the interface between the lead and the resin, that is, a leak path. This makes it possible to realize a hollow package for a high-frequency transistor having small inductance and excellent moisture resistance.

〔実施例〕〔Example〕

以下、本発明の実施例について図面を参照しながら詳
細に説明する。
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

第1図は、本発明の第1の実施例のパッケージの断面
図である。
FIG. 1 is a sectional view of a package according to a first embodiment of the present invention.

まず、第1図に示す、リード先端部12aおよびダイパ
ッド12eから外部導出部12bにいたるリードの形状を、樹
脂基板11の上面から底面にいたる高さになるように成形
する。次に、半導体チップ13をダイパッドの電極とリー
ド先端部との間を金属細線14によってワイヤボンドす
る。
First, as shown in FIG. 1, the shape of the lead from the lead tip 12a and the die pad 12e to the external lead-out portion 12b is formed so as to have a height from the top surface to the bottom surface of the resin substrate 11. Next, the semiconductor chip 13 is wire-bonded between the electrode of the die pad and the tip of the lead with a thin metal wire 14.

半導体チップが置載されたリードを、金型を用いて樹
脂モールドする。このとき、半導体チップとワイヤボン
ド部が樹脂基板の上面に露出し、かつ、樹脂基板底面に
外部リードが露出する寸法に設計されている。
The lead on which the semiconductor chip is mounted is resin-molded using a mold. At this time, the dimensions are designed such that the semiconductor chip and the wire bond portion are exposed on the upper surface of the resin substrate, and the external leads are exposed on the lower surface of the resin substrate.

さらに、樹脂基板の上面に露出している半導体チップ
および金属細線を保護するため、中空17を有するキャッ
プ16を接着剤15を用いて接着する。このキャップシール
は、耐湿性の向上と、接着強度を確保するために、接着
剤溜18を形成しておくのが好ましい。
Further, a cap 16 having a hollow 17 is bonded using an adhesive 15 in order to protect the semiconductor chip and the fine metal wire exposed on the upper surface of the resin substrate. This cap seal is preferably formed with an adhesive reservoir 18 in order to improve moisture resistance and ensure adhesive strength.

他の実施例として、第2図に示すように、樹脂基板
に、第1の樹脂基板11aと、第2の樹脂基板11bを用いた
二重モールド構造のパッケージを用いることによって、
製造方法を容易にし、かつ確実にすることが出来る。
As another embodiment, as shown in FIG. 2, by using a package having a double mold structure using a first resin substrate 11a and a second resin substrate 11b as the resin substrate,
The manufacturing method can be made easy and reliable.

第2図において、まず、成形されたリードを、第1の
樹脂でモールドする。次に、ダイボンド、ワイヤボンド
を第1の実施例のように行う。第1の樹脂基板は、ダイ
ボンド、ワイヤボンド時に下方からの加熱支持柱を挿入
出来るように、ダイパッドおよびリード先端部の裏面近
傍に空間を設ける。加熱支持柱によって、ダイボンドお
よびワイヤボンド時の熱や圧力条件を自由に設定するこ
とが出来る。次に、第2の樹脂を用いて、第1の樹脂の
外周を覆うようにモールドする。
In FIG. 2, first, the formed lead is molded with a first resin. Next, die bonding and wire bonding are performed as in the first embodiment. The first resin substrate has a space near the rear surface of the die pad and the tip of the lead so that the heating support pillar from below can be inserted at the time of die bonding and wire bonding. Heat and pressure conditions during die bonding and wire bonding can be freely set by the heating support columns. Next, the second resin is molded so as to cover the outer periphery of the first resin.

第1の樹脂と第2の樹脂は、特にリードとの接着強度
および熱膨張率の差の小さい熱可塑性樹脂を用いる。例
えばPPS(ポリフェニレンサルファイド)は、二重モー
ルドに使用して好適な熱可塑性樹脂である。
As the first resin and the second resin, a thermoplastic resin having a small difference between the adhesive strength to the lead and the coefficient of thermal expansion is used. For example, PPS (polyphenylene sulfide) is a suitable thermoplastic resin for use in the double mold.

〔発明の効果〕〔The invention's effect〕

本発明によれば、リードが樹脂基板内を貫通し外部に
導出しているので、従来側面から取り出し折り曲げて接
続していたリードの長さよりも短くすることが出来るの
で、インダクタンスを小さくすることが出来る。また、
リードと樹脂基板とが一体成形されているので密着性も
良く耐湿性の向上に寄与する。
According to the present invention, since the lead penetrates through the resin substrate and extends to the outside, the lead can be shorter than the length of the lead that has been conventionally taken out from the side surface and bent and connected, so that the inductance can be reduced. I can do it. Also,
Since the lead and the resin substrate are integrally formed, the adhesion is good and the moisture resistance is improved.

【図面の簡単な説明】[Brief description of the drawings]

第1図は本発明の第1の実施例の断面図、第2図は本発
明の他の実施例の断面図、第3図は従来例を示す中空パ
ッケージの断面図を示す。 11、1……樹脂基板 11a……第1の樹脂 11b……第2の樹脂 12a、2a……リード先端部 12b、2b……外部導出部 12c、2c……内部リード 12d、2d……外部リード 12e、2e……ダイパッド 13、3……半導体チップ 14、4……金属細線 15、5……接着剤 16、6……キャップ 17、7……中空 18……接着剤溜
1 is a sectional view of a first embodiment of the present invention, FIG. 2 is a sectional view of another embodiment of the present invention, and FIG. 3 is a sectional view of a hollow package showing a conventional example. 11, 1 ... Resin board 11a ... First resin 11b ... Second resin 12a, 2a ... Lead tip 12b, 2b ... External lead-out part 12c, 2c ... Internal lead 12d, 2d ... External Leads 12e, 2e Die pad 13, 3, Semiconductor chip 14, 4, Fine metal wire 15, 5, Adhesive 16, 6, Cap 17, 7, Hollow 18, Adhesive reservoir

Claims (1)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】半導体チップとワイヤボンド部とが樹脂基
板の上面に露出されると共にリードが前記樹脂基板を貫
通し、かつ前記樹脂基板の底面に沿って前記リードの延
長部が延在して露出される如く樹脂モールドして、前記
リードと樹脂との界面に沿って外部から浸入する水分の
浸入経路及びリークパスを長くし、前記樹脂基板の上面
に前記半導体チップとワイヤボンド部とを保護する中空
を有するキャップを設けたことを特徴とする半導体装置
用中空パッケージ。
A semiconductor chip and a wire bond portion are exposed on an upper surface of a resin substrate, a lead penetrates the resin substrate, and an extension of the lead extends along a bottom surface of the resin substrate. Resin molding is performed so as to be exposed, so that the infiltration path and leak path of moisture entering from the outside along the interface between the lead and the resin are lengthened to protect the semiconductor chip and the wire bond portion on the upper surface of the resin substrate. A hollow package for a semiconductor device, comprising a cap having a hollow.
JP62167008A 1987-07-06 1987-07-06 Hollow package for semiconductor device Expired - Fee Related JP2600689B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62167008A JP2600689B2 (en) 1987-07-06 1987-07-06 Hollow package for semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62167008A JP2600689B2 (en) 1987-07-06 1987-07-06 Hollow package for semiconductor device

Publications (2)

Publication Number Publication Date
JPS6411356A JPS6411356A (en) 1989-01-13
JP2600689B2 true JP2600689B2 (en) 1997-04-16

Family

ID=15841670

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62167008A Expired - Fee Related JP2600689B2 (en) 1987-07-06 1987-07-06 Hollow package for semiconductor device

Country Status (1)

Country Link
JP (1) JP2600689B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1096566A2 (en) 1999-10-26 2001-05-02 Nec Corporation Electronic part and method of assembling the same
US7004325B2 (en) 2001-05-08 2006-02-28 Nec Compound Semiconductor Devices, Ltd. Resin-molded package with cavity structure

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0468379B1 (en) * 1990-07-21 1999-11-17 Mitsui Chemicals, Inc. Semiconductor device having a package
JP2842355B2 (en) * 1996-02-01 1999-01-06 日本電気株式会社 package
KR100541654B1 (en) * 2003-12-02 2006-01-12 삼성전자주식회사 Wiring substrate and solid-state imaging apparatus using thereof

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61208853A (en) * 1985-03-14 1986-09-17 Toshiba Corp Ic package
JPS61269344A (en) * 1985-05-24 1986-11-28 Hitachi Ltd Lead frame and semiconductor device using said lead frame
JPH069223B2 (en) * 1985-10-05 1994-02-02 山一電機工業株式会社 IC package

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1096566A2 (en) 1999-10-26 2001-05-02 Nec Corporation Electronic part and method of assembling the same
US6518501B1 (en) 1999-10-26 2003-02-11 Nrs Technologies Inc. Electronic part and method of assembling the same
US7004325B2 (en) 2001-05-08 2006-02-28 Nec Compound Semiconductor Devices, Ltd. Resin-molded package with cavity structure
US7187073B2 (en) 2001-05-08 2007-03-06 Nec Electronics Corporation Resin-molded package with cavity structure

Also Published As

Publication number Publication date
JPS6411356A (en) 1989-01-13

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