JP2522182B2 - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JP2522182B2 JP2522182B2 JP25126793A JP25126793A JP2522182B2 JP 2522182 B2 JP2522182 B2 JP 2522182B2 JP 25126793 A JP25126793 A JP 25126793A JP 25126793 A JP25126793 A JP 25126793A JP 2522182 B2 JP2522182 B2 JP 2522182B2
- Authority
- JP
- Japan
- Prior art keywords
- insulating substrate
- element mounting
- external electrode
- external electrodes
- package
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
Landscapes
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】Detailed Description of the Invention
【０００１】[0001]
【産業上の利用分野】本発明は半導体装置に関し、特に
リードレスチップキャリア（以下ＬＣＣと記す）パッケ
ージに関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a leadless chip carrier (hereinafter referred to as LCC) package.
【０００２】[0002]
【従来の技術】チップ実装密度を高めるために一つのパ
ッケージ内に複数の半導体チップを搭載する場合があ
る。2. Description of the Related Art A plurality of semiconductor chips may be mounted in one package in order to increase the chip mounting density.
【０００３】図３（ａ）〜（ｃ）は従来の半導体装置の
第１の例を示す平面図およびＡ−Ａ′線断面図並びにＢ
−Ｂ′線断面図である。3 (a) to 3 (c) are a plan view showing a first example of a conventional semiconductor device, a sectional view taken along the line AA ', and B.
It is a B-B 'line sectional view.
【０００４】図３（ａ）〜（ｃ）に示すように、下面に
素子搭載用の凹部を形成した絶縁基板１の上面に設けた
第１の素子載置部の周囲に配置し、絶縁基板１の外側壁
に形成した溝内に延在させた第１の外部電極２ａと、絶
縁基板１の下面凹部に設けた第２の素子載置部の周囲に
配置して絶縁基板１の側壁を貫通し且つ絶縁基板１の外
側壁に形成した溝内に導出した第２の外部電極２ｂと、
絶縁基板１の上面周縁部に設けた絶縁枠４とを有するＬ
ＣＣ構造のパッケージの第１および第２の素子載置部の
それぞれに半導体チップ５，６をマウントし、この半導
体チップ５，６と外部電極２ａ，２ｂとの間をボンディ
ングワイヤ７で電気的に接続した後、絶縁枠４および凹
部内に樹脂８を充填して封止する。As shown in FIGS. 3A to 3C, the insulating substrate is arranged around the first element mounting portion provided on the upper surface of the insulating substrate 1 having the recess for mounting the element on the lower surface. The first external electrode 2a extending in the groove formed on the outer wall of the first substrate 1 and the second element mounting portion provided in the recessed portion of the lower surface of the insulating substrate 1 are arranged around the sidewall of the insulating substrate 1. A second external electrode 2b which penetrates and is led out into a groove formed in the outer wall of the insulating substrate 1;
L having an insulating frame 4 provided on the peripheral portion of the upper surface of the insulating substrate 1.
The semiconductor chips 5 and 6 are mounted on each of the first and second element mounting portions of the CC structure package, and the bonding wires 7 electrically connect the semiconductor chips 5 and 6 and the external electrodes 2a and 2b. After the connection, the resin 8 is filled in the insulating frame 4 and the concave portion and sealed.
【０００５】ここで、絶縁基板１の上面に搭載された半
導体チップ５と接続する外部電極２ａと絶縁基板１の下
面に搭載された半導体チップ６と接続する外部電極２ｂ
とは絶縁基板１の同じ外側壁に配置されている。Here, an external electrode 2a connected to the semiconductor chip 5 mounted on the upper surface of the insulating substrate 1 and an external electrode 2b connected to the semiconductor chip 6 mounted on the lower surface of the insulating substrate 1.
Are arranged on the same outer wall of the insulating substrate 1.
【０００６】また、チップ実装密度を高める他の例とし
て特開平１−２５７３６１号公報に記載された樹脂封止
型のものがある。Another example of increasing the chip mounting density is a resin-sealed type disclosed in Japanese Patent Application Laid-Open No. 1-257361.
【０００７】図４は従来の半導体装置の第２の例を示す
模式的断面図である。FIG. 4 is a schematic sectional view showing a second example of a conventional semiconductor device.
【０００８】図４に示すように、半導体チップ１１ａを
搭載したアイランド１２ａおよびこのアイランド１２ａ
の周囲に配置して半導体チップ１１ａと電気的に接続し
たリード１３ａを含む第１のリードフレームと、同様
に、半導体チップ１１ｂを搭載したアイランド１２ｂお
よびこのアイランド１２ｂの周囲に配置して半導体チッ
プ１１ｂと電気的に接続したリード１３ｂを含む第２の
リードフレームとを絶縁性接着剤１４を介して接着した
上で樹脂体１５によりモールド封止している。As shown in FIG. 4, an island 12a on which a semiconductor chip 11a is mounted and this island 12a.
The first lead frame including the leads 13a electrically connected to the semiconductor chip 11a by being arranged around the semiconductor chip 11a, and similarly, the island 12b on which the semiconductor chip 11b is mounted and the semiconductor chip 11b arranged around the island 12b. A second lead frame including a lead 13b electrically connected to the above is adhered via an insulating adhesive 14 and is then molded and sealed with a resin body 15.
【０００９】[0009]
【発明が解決しようとする課題】この従来の半導体装置
では、絶縁基板の外側壁にのみ外部電極を有しているた
め、両面搭載によりチップ実装密度を上げても外部電極
数で外形寸法が制限され、小型化が困難であるという問
題があった。In this conventional semiconductor device, since the external electrodes are provided only on the outer side wall of the insulating substrate, the external dimensions are limited by the number of external electrodes even if the chip mounting density is increased by mounting on both sides. However, there is a problem that miniaturization is difficult.
【００１０】またモールド封止した構造では、少なくと
もリード分だけＬＣＣパッケージより外形寸法が大きく
なり、その上、上面と下面の半導体チップ間を電気的に
接続できないという問題があった。In addition, the mold-sealed structure has a problem that the outer dimensions are larger than those of the LCC package by at least the amount of leads, and moreover, the upper and lower semiconductor chips cannot be electrically connected.
【００１１】[0011]
【課題を解決するための手段】本発明の半導体装置は、
下面に凹部を形成した絶縁基板、前記絶縁基板の上面に
形成した第１の素子載置部の近傍から前記絶縁基板の外
側壁を経由して前記下面に至る第１の外部電極および前
記凹部内に形成した第２の素子載置部の近傍から前記凹
部の側壁を経由して前記下面に至り前記第１の外部電極
とは別個の第２の外部電極を有するリードレスチップキ
ャリアパッケージと、前記パッケージの第１の素子載置
部および第２の素子載置部のそれぞれに搭載され前記第
１の外部電極および第２の外部電極とそれぞれ電気的に
接続された第１の半導体チップおよび第２の半導体チッ
プと、前記第１の半導体チップ及び第２の半導体チップ
のそれぞれを封止する第１の樹脂および第２の樹脂とを
含んで構成される。According to the present invention, there is provided a semiconductor device comprising:
An insulating substrate having a recess on a lower surface, said first element and the first external electrode and front from the vicinity of the mounting portion reaching the lower surface through the outer wall of the insulating substrate formed on the upper surface of the insulating substrate <br The first external electrode extending from the vicinity of the second element mounting portion formed in the recess to the lower surface via the sidewall of the recess.
Leadless chip carrier package, a first element mounted in the package with a separate second outer electrodes and
A first semiconductor chip and a second semiconductor chip mounted on each of the first portion and the second element mounting portion and electrically connected to the first external electrode and the second external electrode, respectively; And a first resin and a second resin that seal the semiconductor chip and the second semiconductor chip, respectively.
【００１２】[0012]
【実施例】次に、本発明について図面を参照して説明す
る。Next, the present invention will be described with reference to the drawings.
【００１３】図１（ａ），（ｂ）は本発明の第１の実施
例を示す模式的断面図および底面図である。1A and 1B are a schematic sectional view and a bottom view showing a first embodiment of the present invention.
【００１４】図１（ａ），（ｂ）に示すように、下面に
凹部を形成したセラミック等からなる絶縁基板１と、絶
縁基板１の上面中央部に形成した第１の素子載置部の周
囲に配置し絶縁基板１の外側壁に形成した溝内に延在さ
せた第１の外部電極２と、同様に絶縁基板１の下面凹部
の中央部に形成した第２の素子載置部の周囲に配置し絶
縁基板１の内側壁（凹部の側壁）に形成した溝内に延在
させた第２の外部電極３と、絶縁基板１上面の周縁部に
設けた絶縁枠４とを有してＬＣＣ構造のパッケージを構
成し、第１および第２の素子載置部のそれぞれにマウン
トした半導体チップ５，６と外部電極２．３との間をボ
ンディングワイヤ７で電気的に接続した後、絶縁枠４お
よび凹部内に樹脂８を充填して封止する。As shown in FIGS. 1A and 1B, an insulating substrate 1 made of ceramic or the like having a recess formed in the lower surface thereof and a first element mounting portion formed in the central portion of the upper surface of the insulating substrate 1 are formed. The first external electrode 2 arranged in the periphery and extending in the groove formed on the outer wall of the insulating substrate 1 and the second element mounting portion formed in the central portion of the lower surface concave portion of the insulating substrate 1 similarly. It has a second external electrode 3 which is arranged in the periphery and extends in a groove formed on the inner side wall (side wall of the recess) of the insulating substrate 1, and an insulating frame 4 provided on the peripheral portion of the upper surface of the insulating substrate 1. After forming a package having an LCC structure by electrically connecting the semiconductor chips 5 and 6 mounted on each of the first and second element mounting portions and the external electrode 2.3 with a bonding wire 7, A resin 8 is filled in the insulating frame 4 and the concave portion and sealed.
【００１５】図２は本発明の第２の実施例を示す模式的
断面図である。FIG. 2 is a schematic sectional view showing a second embodiment of the present invention.
【００１６】図２に示すように、底面に凹部を形成した
絶縁基板の代りに多層配線基板１ａを用いた以外は第１
の実施例と同様の構成を有しており、多層配線基板１ａ
の内部配線を介して上面と下面にマウントした半導体チ
ップ５，６相互間の接続や外部電極２，３への接続もピ
ン位置に制限されずに任意に接続できる利点がある。As shown in FIG. 2, a first multilayer wiring board 1a is used in place of the insulating substrate having a recess formed on the bottom surface.
Of the multi-layer wiring board 1a
The connection between the semiconductor chips 5 and 6 mounted on the upper surface and the lower surface via the internal wiring and the connection to the external electrodes 2 and 3 are not limited to the pin positions, and can be arbitrarily connected.
【００１７】[0017]
【発明の効果】以上説明したように本発明は、絶縁基板
の底面に設けた凹部の内側壁に絶縁基板の外側壁に設け
た外部電極と同様の外部電極を設けることにより、外部
電極数を増加したＬＣＣ構造のパッケージを実現できる
という効果を有する。また、外部電極数の増加により、
回路基板上に実装したときの接続個所も増加して放熱性
が向上するという効果を有する。As described above, the present invention reduces the number of external electrodes by providing the external electrodes similar to the external electrodes provided on the outer wall of the insulating substrate on the inner wall of the recess provided on the bottom surface of the insulating substrate. This has the effect of realizing a package with an increased LCC structure. Also, due to the increase in the number of external electrodes,
This also has the effect of increasing the number of connection points when mounted on a circuit board and improving heat dissipation.
【図１】本発明の第１の実施例を示す模式的断面図およ
び底面図。FIG. 1 is a schematic sectional view and a bottom view showing a first embodiment of the present invention.
【図２】本発明の第２の実施例を示す模式的断面図。FIG. 2 is a schematic sectional view showing a second embodiment of the present invention.
【図３】従来の半導体装置の第１の例を示す平面図およ
びＡ−Ａ′線断面図並びにＢ−Ｂ′線断面図。3A and 3B are a plan view, a cross-sectional view taken along the line AA ′, and a cross-sectional view taken along the line BB ′ of the conventional semiconductor device.
【図４】従来の半導体装置の第２の例を示す模式的断面
図。FIG. 4 is a schematic cross-sectional view showing a second example of a conventional semiconductor device.
１ 絶縁基板 １ａ 多層配線基板 ２，２ａ，２ｂ，３ 外部電極 ４ 絶縁枠 ５，６，１１ａ，１１ｂ 半導体チップ ７ ボンディングワイヤ ８ 樹脂 １２ａ，１２ｂ アイランド １３ａ，１３ｂ リード １４ 絶縁性接着剤 １５ 樹脂体 1 Insulating Substrate 1a Multilayer Wiring Substrate 2, 2a, 2b, 3 External Electrode 4 Insulating Frame 5, 6, 11a, 11b Semiconductor Chip 7 Bonding Wire 8 Resin 12a, 12b Island 13a, 13b Lead 14 Insulating Adhesive 15 Resin Body
Claims (1)
縁基板の上面に形成した第１の素子載置部の近傍から前
記絶縁基板の外側壁を経由して前記下面に至る第１の外
部電極および前記凹部内に形成した第２の素子載置部の
近傍から前記凹部の側壁を経由して前記下面に至り前記
第１の外部電極とは別個の第２の外部電極を有するリー
ドレスチップキャリアパッケージと、前記パッケージの
第１の素子載置部および第２の素子載置部のそれぞれに
搭載され前記第１の外部電極および第２の外部電極とそ
れぞれ電気的に接続された第１の半導体チップおよび第
２の半導体チップと、前記第１の半導体チップ及び第２
の半導体チップのそれぞれを封止する第１の樹脂および
第２の樹脂とを含むことを特徴とする半導体装置。1. An insulating substrate having a recess formed on a lower surface thereof , and a first element mounting portion formed on an upper surface of the insulating substrate from the vicinity of the insulating substrate to the lower surface via an outer wall of the insulating substrate. Of the first external electrode and the second element mounting portion formed in the recess.
From the vicinity to the lower surface via the side wall of the recess,
A leadless chip carrier package having a separate second outer electrode and the first external electrode, the first being mounted on each of the first element mounting portion and the second element mounting portion of the package A first semiconductor chip and a second semiconductor chip electrically connected to the external electrode and the second external electrode, respectively, and the first semiconductor chip and the second semiconductor chip .
A first resin for sealing each of the semiconductor chips of
A semiconductor device comprising a second resin.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP25126793A JP2522182B2 (en) | 1993-10-07 | 1993-10-07 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP25126793A JP2522182B2 (en) | 1993-10-07 | 1993-10-07 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH07106462A JPH07106462A (en) | 1995-04-21 |
| JP2522182B2 true JP2522182B2 (en) | 1996-08-07 |
Family
ID=17220250
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP25126793A Expired - Lifetime JP2522182B2 (en) | 1993-10-07 | 1993-10-07 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2522182B2 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR0179921B1 (en) * | 1996-05-17 | 1999-03-20 | 문정환 | Stacked semiconductor package |
| WO2006090827A1 (en) * | 2005-02-25 | 2006-08-31 | Kyocera Corporation | Electronic device and method for manufacturing same |
-
1993
- 1993-10-07 JP JP25126793A patent/JP2522182B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH07106462A (en) | 1995-04-21 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 19960402 |