JPS6232636A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS6232636A JPS6232636A JP60172661A JP17266185A JPS6232636A JP S6232636 A JPS6232636 A JP S6232636A JP 60172661 A JP60172661 A JP 60172661A JP 17266185 A JP17266185 A JP 17266185A JP S6232636 A JPS6232636 A JP S6232636A
- Authority
- JP
- Japan
- Prior art keywords
- bonding pad
- layer
- pad layer
- hole
- bonding
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
- H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
- H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
- H01L2224/02165—Reinforcing structures
- H01L2224/02166—Collar structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/05099—Material
- H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/05124—Aluminium [Al] as principal constituent
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/05624—Aluminium [Al] as principal constituent
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/852—Applying energy for connecting
- H01L2224/85201—Compression bonding
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明はボンディングパッドを有する半導体装置に関し
、特にボンディングパッド及び配線部の耐腐食性を向上
した半導体装置に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device having a bonding pad, and more particularly to a semiconductor device in which the corrosion resistance of the bonding pad and wiring portion is improved.
一般に半導体装置には内部回路配線に接続されたボンデ
ィングパッドが設けられ、外部リード等に接続される金
属細線がボンディングされる。Generally, a semiconductor device is provided with a bonding pad connected to internal circuit wiring, to which a thin metal wire connected to an external lead or the like is bonded.
例えば、第３図及び第４図はその一例であり、半導体基
板２１表面の絶縁膜２２上にアルミニウム等の金属膜か
らなるボンディングパッド２３が形成されている。この
ボンディングパッド２３は、図外の内部回路にまで延設
される内部配線２４に接続しており、これとの境にはボ
ンディング時の集中応力による配線２４の切断を防止す
るためのバンド引出し部２５を形成している。これらボ
ンディングパッド２３、内部配線２４及びバンド引出し
部２５は表面保護膜２６により被覆されているが、ボン
ディングバンド２３位置に設けた方形の開口２７からボ
ンディングパッド２３のみを露出させている。そして、
このボンディングパッド２３の露出面には図外の外部リ
ードに接続される金属細線２８の一端がボンディングさ
れる。For example, FIGS. 3 and 4 are examples of this, in which a bonding pad 23 made of a metal film such as aluminum is formed on an insulating film 22 on the surface of a semiconductor substrate 21. This bonding pad 23 is connected to an internal wiring 24 that extends to an internal circuit (not shown), and a band lead-out portion is provided at the boundary to prevent the wiring 24 from being cut due to concentrated stress during bonding. 25 is formed. These bonding pads 23, internal wiring 24, and band extension portions 25 are covered with a surface protective film 26, but only the bonding pads 23 are exposed through rectangular openings 27 provided at the bonding band 23 positions. and,
One end of a thin metal wire 28 connected to an external lead (not shown) is bonded to the exposed surface of the bonding pad 23.
上述した従来のポンディングバッド２３構造の半導体装
置を樹脂封止して高温、高湿度下での信頼性試験を行う
と、ボンディングパッド２３の露出面において腐食が生
じることが比較的多く観察される。この腐食は、前述し
た外部リードを構成するリードフレームと樹脂との界面
及び樹脂表面から浸入する水分と、樹脂中に含まれる塩
素イオン（ｃｌ−）又はナトリウムイオン（Ｎａ” ）
等の不純物イオンとの相互作用により生しることが明ら
かにされている（応用物理第４９巻第２号「半導体素子
における封止樹脂の問題」）。また、腐食は時間ととも
に進行し、ボンディングパッド２３のみならずボンディ
ングパッドに接続した配線２４にもおよびこれが断線に
到る場合もある。When a semiconductor device with the conventional bonding pad 23 structure described above is sealed with resin and subjected to a reliability test under high temperature and high humidity, it is observed that corrosion occurs relatively frequently on the exposed surface of the bonding pad 23. . This corrosion is caused by moisture that enters from the interface between the lead frame and the resin that make up the external lead and the resin surface, and by chlorine ions (Cl-) or sodium ions (Na'') contained in the resin.
It has been clarified that this is caused by interaction with impurity ions such as (Applied Physics Vol. 49, No. 2, "Problems with Sealing Resins in Semiconductor Devices"). Moreover, corrosion progresses over time, and may reach not only the bonding pad 23 but also the wiring 24 connected to the bonding pad, leading to disconnection.
このような腐食を防止するために、これまではボンディ
ングパッド２３における開口２７を小さくしてボンディ
ングパッド２３の露出面積をできるだけ狭くする対策、
或いは水分の浸入を防ぐために信頼性の高いセラミック
パッケージを使用する対策等が施されている。しかしな
がら、前者ではボンディングパッド２３と金属細線２８
との接触面積が小さくなるためにボンディング強度が低
下して組立て歩留を低下させ、後者では量産性の低下、
価格の増大を生じることになる。In order to prevent such corrosion, measures have been taken so far to make the opening 27 in the bonding pad 23 smaller to make the exposed area of the bonding pad 23 as narrow as possible.
Alternatively, measures are taken to prevent moisture from entering, such as using highly reliable ceramic packages. However, in the former case, the bonding pad 23 and the thin metal wire 28
As the contact area with the product becomes smaller, the bonding strength decreases and the assembly yield decreases, and in the latter case, mass productivity decreases.
This will result in an increase in price.
本発明の半導体装置は、ボンディング時・ノドを改善し
て信頼性及び歩留の向上を図るために、半導体基板の絶
縁膜上に形成して内部配線に接続する第１ボンディング
パッド層と、この第１ボンディングパッド層上の層間絶
縁膜上に形成して金属細線等を接続する第２ポンデイン
グパソド層とでボンディングパッドを構成し、これら両
ボンディングバソド層は、前記層間絶縁膜に形成したス
ルーホールを通して相互に接続し、かつこのスルーホー
ルは前記金属細線の接触面内に位置するように構成して
いる。The semiconductor device of the present invention includes a first bonding pad layer formed on an insulating film of a semiconductor substrate and connected to internal wiring, in order to improve reliability and yield by improving bonding and bonding. A bonding pad is formed with a second bonding pad layer formed on the interlayer insulating film on the first bonding pad layer and connecting thin metal wires, etc., and both of these bonding pad layers are formed on the interlayer insulating film. The metal wires are connected to each other through a through hole, and the through hole is located within the contact surface of the thin metal wire.
次に、本発明を図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第１図及び第２図は本発明の一実施例の平面図と断面図
である。1 and 2 are a plan view and a sectional view of an embodiment of the present invention.
所定の回路素子が形成されている半導体基板ｌの表面に
設けた絶縁膜２上には、アルミニウム層３を形成し、こ
のアルミニウム層３の一部を第１ボンディングパッド層
４として構成している。即ち、このアルミニウム層３は
、第１ボンディングパッド層４、ボンディング時の応力
を緩和するためのパッド引出し部５及び図外の回路素子
にまで延設される内部配線６を構成しており、パッド引
出し部５と内部配線６を介して第１ボンデイングパフド
Ｎ４を前記回路素子に接続している。An aluminum layer 3 is formed on an insulating film 2 provided on the surface of a semiconductor substrate l on which predetermined circuit elements are formed, and a part of this aluminum layer 3 is configured as a first bonding pad layer 4. . That is, this aluminum layer 3 constitutes a first bonding pad layer 4, a pad lead-out portion 5 for relieving stress during bonding, and an internal wiring 6 extending to a circuit element (not shown). A first bonding puff N4 is connected to the circuit element via a lead-out portion 5 and an internal wiring 6.
前記アルミニウム層３の上には層間絶縁膜７を形成する
とともに、この層間絶縁膜７には前記第１ボンディング
パッド層４上の位置を方形に小さく開口したスルーホー
ル８を形成している。そして、この層間絶縁膜７上には
アルミニウム膜を被着し、かつこれを前記第１ボンディ
ングパッド層４と略同−形状にパターニングして第２ボ
ンデインクバンド層９を形成している。この場合、スル
ーホール８はこれらボンディングパッド層４．９の略中
央位置に開設し、かつ後述する金属細線１２のボンディ
ング接触面内に含まれるような大きさとし、このスルー
ホール８によって前記第１ポンデイングパツドＮ４と第
２ボンディングパッド層９を相互に接続している。更に
、その上には保護膜１０を被着し、ここに方形の窓１１
を開口して前記第２ボンディングパッド層９を露出させ
ている。An interlayer insulating film 7 is formed on the aluminum layer 3, and a small rectangular through hole 8 is formed in the interlayer insulating film 7 at a position above the first bonding pad layer 4. Then, an aluminum film is deposited on the interlayer insulating film 7 and patterned to have substantially the same shape as the first bonding pad layer 4 to form a second bonding ink band layer 9. In this case, the through hole 8 is opened approximately in the center of these bonding pad layers 4.9 and is sized to be included within the bonding contact surface of the thin metal wire 12, which will be described later. The bonding pad N4 and the second bonding pad layer 9 are interconnected. Furthermore, a protective film 10 is applied thereon, and a rectangular window 11 is formed thereon.
is opened to expose the second bonding pad layer 9.
このように構成した上で、図外の外部リードに接続され
る金属細線１２の一端を、熱圧着法によって前記第２ポ
ンデイングパソド層９の露出された表面に接続している
。With this structure, one end of the thin metal wire 12 connected to an external lead (not shown) is connected to the exposed surface of the second padding pad layer 9 by thermocompression bonding.
したがって、このボンディングパッド構造によれば、第
２ボンディングパッド層９が露出されてはいるが、第１
ボンディングパッド層４は第２ポンデイングパソド層９
や保護膜１０に覆われているために、露出されることは
ない。このため、浸入してきた水分によって第２ボンデ
ィングパッド層９が腐食される場合にも、この水分は直
接には第１ボンディングパッド層４には作用せず、この
ボンディングパッド層４を腐食させることはない。Therefore, according to this bonding pad structure, although the second bonding pad layer 9 is exposed, the first bonding pad layer 9 is exposed.
The bonding pad layer 4 is a second bonding pad layer 9
Since it is covered with a protective film 10, it is not exposed. Therefore, even if the second bonding pad layer 9 is corroded by the moisture that has entered, this moisture does not directly act on the first bonding pad layer 4, and the bonding pad layer 4 will not be corroded. do not have.
この場合、第２ボンデイングバノド層９と保護膜１０及
び層間絶縁膜７との間の隙間から水分が浸入し、ようと
しても、スルーホール８の前述した構成により、水分の
浸入経路が従来よりも長くなり、水分が第１ボンディン
グパッド層４に到る確率を低減させ腐食を有効に抑制す
る。In this case, moisture may infiltrate through the gaps between the second bonding layer 9, the protective film 10, and the interlayer insulating film 7, and even if an attempt is made, the above-mentioned structure of the through hole 8 prevents the moisture from entering through the path compared to the conventional one. This also reduces the probability that moisture will reach the first bonding pad layer 4 and effectively suppresses corrosion.
また、第１及び第２の各ボンディングパッド層４．９を
相互に接続するスルーホール８は、金属細線１２の接触
面内に含まれているために、第２ボンディングパッド層
９に腐食が生じても、金属細線１２の下側では第２ボン
デイングバソド層９が残されているため、スルーホール
８内での腐食は防止でき、したがってこのスルーホール
８に続いている第１ボンディングパッド層４の腐食を防
止できる。Further, since the through hole 8 that interconnects the first and second bonding pad layers 4.9 is included in the contact surface of the thin metal wire 12, corrosion occurs in the second bonding pad layer 9. However, since the second bonding bath layer 9 remains below the thin metal wire 12, corrosion within the through hole 8 can be prevented, and therefore the first bonding pad layer 4 following the through hole 8 can be prevented from corrosion. Can prevent corrosion.
以上説明したように本発明によれば、内部配線に接続す
る第１ボンディングパッド層と、この第１ボンディング
パッド層上の層間絶縁膜上に形成して金属細線等を接続
する第２ボンデイングバソド層とでボンディングパッド
を構成し、これら両ボンディングパッド層を前記層間絶
縁膜に形成したスルーホールを通して相互に接続し、か
つこのスルーホールを前記金属細線の接触面内に位置す
るように構成しているので、第２ボンディングパッド層
が腐食される場合にも金属細線下のスルーホール箇所に
おいてはその腐食を防止でき、かつこれに続く第１ボン
ディングパッド層の腐食を防止することができる。また
、露出した第２ボンデイングパフド層から第１ボンディ
ングパッド層に到る水分の浸入経路を長くでき、第１ボ
ンディングパッド層の水分の直接作用による腐食を防止
できる。これにより、内部配線の腐食及びその切断を防
止でき、信頼性及び歩留の高い半導体装置を得ることが
できる。As explained above, according to the present invention, there is a first bonding pad layer that connects to internal wiring, and a second bonding bath layer that is formed on the interlayer insulating film on the first bonding pad layer and connects thin metal wires, etc. constitute a bonding pad, and both bonding pad layers are connected to each other through a through hole formed in the interlayer insulating film, and the through hole is configured to be located within the contact surface of the thin metal wire. Therefore, even if the second bonding pad layer is corroded, the corrosion can be prevented at the through-hole location under the thin metal wire, and the subsequent corrosion of the first bonding pad layer can be prevented. Furthermore, the path of moisture infiltration from the exposed second bonding puffed layer to the first bonding pad layer can be lengthened, and corrosion of the first bonding pad layer due to direct action of moisture can be prevented. As a result, corrosion of the internal wiring and its cutting can be prevented, and a semiconductor device with high reliability and high yield can be obtained.
第１図は本発明の一実施例の平面図、第２図は第１図の
ＡＡ線断面図、第３図は従来構造の平面図、第４図は第
３図のＢＢ線断面図である。
ｌ、２１・・・半４体基板、２，２２・・・絶縁膜、３
・・・アルミニウム膜、４・・・第１ボンディングパッ
ド層、５・・・バッド引出し部、６・・・内部配線、７
・・・層間絶縁膜、８・・・スルーホール、９・・・第
２ボンデイングバソド層、１０・・・保護膜、１１・・
・窓、１２・・・金属細線、２３・・・ボンディングパ
ッド、２４・・・内部配線、２５・・・パッド引出し部
、２６・・・保護膜、２７・・・開口、２８・・・金属
細線。
第３図
第４図Fig. 1 is a plan view of an embodiment of the present invention, Fig. 2 is a sectional view taken along line AA in Fig. 1, Fig. 3 is a plan view of a conventional structure, and Fig. 4 is a sectional view taken along line BB in Fig. 3. be. l, 21... Half-quad board, 2, 22... Insulating film, 3
. . . aluminum film, 4 . . . first bonding pad layer, 5 . . . pad lead-out portion, 6 .
...Interlayer insulating film, 8...Through hole, 9...Second bonding bath layer, 10...Protective film, 11...
・Window, 12... Metal thin wire, 23... Bonding pad, 24... Internal wiring, 25... Pad extraction part, 26... Protective film, 27... Opening, 28... Metal Thin line. Figure 3 Figure 4
Claims (1)
れる第１ボンディングパッド層と、この第１ボンディン
グパッド層の上に設けた層間絶縁膜上に形成し、その表
面に金属細線等を接続する第２ボンディングパッド層と
でボンディングパッドを構成してなり、これら両ボンデ
ィングパッド層は、前記層間絶縁膜に形成したスルーホ
ールを通して相互に接続し、かつこのスルーホールは前
記金属細線と第２ボンディングパッド層との接触面内に
位置するように構成したことを特徴とする半導体装置。1. A first bonding pad layer formed on an insulating film of a semiconductor substrate and connected to internal wiring, and an interlayer insulating film provided on the first bonding pad layer, and a thin metal wire etc. A bonding pad is formed by a second bonding pad layer that connects the thin metal wire and the second bonding pad layer, and both of these bonding pad layers are connected to each other through a through hole formed in the interlayer insulating film, and this through hole connects the thin metal wire and the second bonding pad layer. 1. A semiconductor device characterized in that the semiconductor device is configured to be located within a contact surface with two bonding pad layers.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60172661A JPS6232636A (en) | 1985-08-05 | 1985-08-05 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60172661A JPS6232636A (en) | 1985-08-05 | 1985-08-05 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6232636A true JPS6232636A (en) | 1987-02-12 |
Family
ID=15946028
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60172661A Pending JPS6232636A (en) | 1985-08-05 | 1985-08-05 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6232636A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5235212A (en) * | 1988-03-18 | 1993-08-10 | Kabushiki Kaisha Toshiba | Semiconductor device having a mechanical buffer |
| US7982254B2 (en) | 2005-07-04 | 2011-07-19 | Fujitsu Semiconductor Limited | Semiconductor device and method of fabricating the same |
-
1985
- 1985-08-05 JP JP60172661A patent/JPS6232636A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5235212A (en) * | 1988-03-18 | 1993-08-10 | Kabushiki Kaisha Toshiba | Semiconductor device having a mechanical buffer |
| US7982254B2 (en) | 2005-07-04 | 2011-07-19 | Fujitsu Semiconductor Limited | Semiconductor device and method of fabricating the same |
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