JP2000228485A - Semiconductor device of chip-on-chip structure and semiconductor chip - Google Patents

Abstract

PROBLEM TO BE SOLVED: To increase the degree of freedom in the position of a pad opening. SOLUTION: On the surface of a master chip 1, a plurality of bumps B1 and a surface wiring W1, which are electrically connected to an inside wiring through pad openings, are formed. On the surface of a slave chip 2, a plurality of bumps B2 and a surface wiring W2, which are connected to an inside wiring through pad openings, are formed. The slave chip 2 is joined to the master chip 1, with the surface of the slave chip 2 face to face with that of the master chip 1 by, so called, a face down mounting method. With the bumps B2 connected to the bumps B1 or the surface wiring W1 of the master chip 1 and the surface wiring W2 connected to the bumps B1 or the surface wiring W1 of the master chip 1, the slave chip 2 is electrically connected to the master chip 1 with a specified distance kept between the surface of the master chip 1 and that of the slave chip 2.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a chip-on-chip structure in which, for example, another semiconductor chip is overlapped on the surface of a semiconductor chip and joined, and a semiconductor chip.

[0002]

2. Description of the Related Art For example, a so-called chip-on-chip structure, in which a plurality of semiconductor chips are overlapped and joined so that their surfaces face each other, has been known as a structure for achieving miniaturization and high integration of a semiconductor device. is there. This tip
In each semiconductor chip applied to the on-chip structure, for example, a pad opening for partially exposing the internal wiring is formed on the surface, and the pad opening is formed on the internal wiring exposed through the pad opening. A bump is provided. In the semiconductor device having the chip-on-chip structure, the internal wiring of one semiconductor chip is electrically connected to the internal wiring of the other semiconductor chip by connecting the bumps of the opposing semiconductor chips. Therefore, it is necessary to form the pad opening for partially exposing the internal wiring in a position in consideration of the bump of the opposing semiconductor chip.

[0003]

However, if the pad opening can be formed irrespective of the bump position of the opposing semiconductor chip, the degree of freedom in arranging wiring and functional elements increases, thereby increasing the size of the semiconductor device. Further miniaturization and high integration can be achieved. Therefore, an object of the present invention is to provide a semiconductor device and a semiconductor chip having a chip-on-chip structure that can achieve miniaturization and high integration by increasing the degree of freedom of the formation position of a pad opening. is there.

[0004]

Means for Solving the Problems and Effects of the Invention According to the first aspect of the present invention, a pad opening for partially exposing an internal wiring is formed on a surface. And a pad opening for partially exposing the internal wiring is formed on the surface facing the first semiconductor chip, the pad opening being formed on the surface facing the first semiconductor chip. 2 and the pad opening of the first semiconductor chip,
A surface wiring electrically connected to the internal wiring of the first semiconductor chip; and an inter-wiring connecting portion for connecting the surface wiring to the internal wiring exposed through a pad opening of the second semiconductor chip. A semiconductor device having a chip-on-chip structure.

[0005] The inter-wiring connection may be a surface wiring electrically connected to an internal wiring of the second semiconductor chip via a pad opening of the second semiconductor chip.
Further, the inter-wiring connection may be a bump formed on an internal wiring exposed through a pad opening of the second semiconductor chip. Here, the surface wiring means a portion having a portion extending from above the pad opening along the surface of the semiconductor chip, and the bump means a portion formed to protrude above the pad opening.

According to the present invention, the first semiconductor chip and the second semiconductor chip are electrically connected to each other by connecting the surface wiring and the internal wiring of the second semiconductor chip through the wiring connection portion. In other words, electrical connection between the first semiconductor chip and the second semiconductor chip can be achieved by patterning the surface wiring so that the surface wiring and the inter-wiring connection portion are connected. Therefore, the formation position of the pad opening of the first semiconductor chip can be determined regardless of the position of the pad opening of the second semiconductor chip. As a result, the degree of freedom in arranging the internal wiring and the functional element of the first semiconductor chip is increased, and as a result, the semiconductor device can be further miniaturized and highly integrated.

In the case where the inter-wiring connection is a surface wiring, the pad opening of the first semiconductor chip and the pad opening of the second semiconductor chip are respectively replaced with the pad opening of the second semiconductor chip and the pad opening of the second semiconductor chip. The first semiconductor chip can be formed at a position irrespective of the arrangement of the pad openings. As a result, the degree of freedom in the arrangement of the internal wirings and functional elements of the first and second semiconductor chips increases, and
The size and integration of the semiconductor chip can be reduced.

According to a second aspect of the present invention, there is provided a surface protection film covering the internal wiring, a pad opening opened in the surface protection film and exposing a part of the internal wiring, and formed on the surface protection film. And a surface wiring electrically connected to the internal wiring through the pad opening. When the semiconductor chip according to the present invention is applied to, for example, a semiconductor device having a chip-on-chip structure, an electric connection between the semiconductor chips is achieved by coupling the surface wiring to bumps of the opposing semiconductor chip. Since the connection can be achieved, the pad opening can be formed without considering the bump position of the opposing semiconductor chip. As a result, the degree of freedom in the arrangement of wirings and functional elements can be increased, and the semiconductor chip can be reduced in size and highly integrated.

According to a third aspect of the present invention, the front surface wiring comprises:
3. The semiconductor chip according to claim 2, wherein the semiconductor chip is made of a material having oxidation resistance. According to the present invention, since there is no possibility that the surface wiring is susceptible to corrosion due to oxidation, it is not necessary to form a protective film for protecting the surface wiring. Therefore, the number of manufacturing steps of the semiconductor chip can be reduced as compared with the case where the internal wiring has a multilayer structure in order to increase the number of wirings.

The invention according to claim 4 is formed by laminating a seed film on the surface of the surface protection film in which the pad opening is formed, and selectively plating the seed film in the pad opening. 4. The semiconductor chip according to claim 2, further comprising a bump, wherein the surface wiring is formed by patterning the seed film.

According to the present invention, for example, when a seed film used for forming a bump is removed, the surface wiring can be formed by selectively removing and patterning the seed film. There is no need to prepare materials for Therefore, an increase in cost due to the provision of the surface wiring can be suppressed. The invention according to claim 5 is the semiconductor chip according to claim 4, wherein the surface wiring and the bump are made of the same material.

According to the present invention, since the surface wiring and the bump are made of the same material, the surface wiring and the bump can be formed in the same step, and the manufacturing process is simplified.

[0013]

Embodiments of the present invention will be described below in detail with reference to the accompanying drawings. FIG. 1 is an illustrative sectional view showing a schematic configuration of a semiconductor device according to an embodiment of the present invention. This semiconductor device has a so-called chip-on-chip structure, and is configured by superposing and bonding a child chip 2 to a surface 11 of a parent chip 1, sealing them with a resin, and putting them in a package 3. Have been.

The parent chip 1 is made of, for example, a silicon chip. The surface 11 of the parent chip 1 is a surface on the active surface layer region side on which a functional element such as a transistor is formed on a semiconductor substrate forming a base of the parent chip 1, and the outermost surface is a surface protection film made of, for example, silicon nitride. Covered with. On this surface protective film, a plurality of pads 12 for external connection are arranged so as to be exposed near the periphery of the surface 11 of the parent chip 1 having a substantially rectangular planar shape. The external connection pad 12 is connected to a lead frame 14 by a bonding wire 13. A plurality of bumps B electrically connected to the internal wiring are formed on the surface protection film.
1 and a surface wiring W1 are provided.

The child chip 2 is made of, for example, a silicon chip. The surface 21 of the child chip 2 is a surface on the active surface layer region side on which a functional element such as a transistor is formed on a semiconductor substrate forming a base of the child chip 2, and the outermost surface is a surface protective film made of, for example, silicon nitride. Covered with. A plurality of bumps B2 connected to the internal wiring and a surface wiring W2 are provided on the surface protection film.

The child chip 2 is joined to the parent chip 1 by a so-called face-down method in which the front surface 21 faces the front surface 11 of the parent chip 1. The child chip 2 has the bumps B2 connected to the bumps B1 or the surface wirings W1 of the parent chip 1 and the surface wirings W2 connected to the bumps B1 or the surface wirings W1 of the parent chip 1 so that the surface of the parent chip 1 is formed. 11 and is electrically connected to the parent chip 1 while maintaining a predetermined interval.

FIG. 2 is an enlarged sectional view showing the configuration of the parent chip 1 and the child chip 2. As shown in FIG. Bump B of parent chip 1
1 and the surface wiring W1 are the same as the configuration of the bump B2 and the surface wiring W2 of the child chip 2, so that only the child chip 2 will be described below, and in FIG. Each part is denoted by the reference numeral of the corresponding part of the child chip 2.

A field oxide film 23 made of, for example, silicon oxide is formed on the semiconductor substrate 22 of the child chip 2, and internal wirings 24A and 24B are arranged on the field oxide film 23. The surfaces of the field oxide film 23 and the wirings 24A, 24B are covered with a surface protection film 25 having an insulating property.
The pad openings 26A and 26B are connected to the wiring 2 respectively.
4A and 24B.

The materials of the internal wirings 24A and 24B are, for example, aluminum, an alloy of aluminum and silicon, an alloy of aluminum, silicon and copper,
An alloy of aluminum and copper, copper, or the like can be used. Further, as a material of the surface protection film 25, for example, silicon oxide, silicon nitride, silicon fluoride, SiON, or the like can be used.

The bump B2 is made of an oxidation-resistant metal (for example, gold, a lead-based alloy, platinum, silver, palladium, iridium, or an alloy containing them), and is formed on the internal wiring 24A exposed through the pad opening 26A. It is formed in a raised state. On the other hand, the surface wiring W2 is formed on the surface protection film 25 using the same material as the bump B2, protrudes above the pad opening 26B, and further extends along the surface of the surface protection film 25.

The bump B2 and the surface wiring W2 can be formed in the same step. That is, after the pad openings 26A and 26B are formed in the surface protection film 25, the surface protection film 25 in which the pad openings 26A and 26B are formed and the surface protection film 25 are exposed through the pad openings 26A and 26B. The seed film 27 is formed on the surfaces of the internal wirings 24A and 24B by, for example, a sputtering method. Then, after a resist film is formed on the seed film 27 other than the portion facing the pad openings 26A and 26B and the portion where the surface wiring W2 is to be formed, plating using the material of the bump B2 and the surface wiring W2 is performed. . Then, the seed film 2
By removing the resist film on 7 and further removing the seed film 27 exposed by removing the resist film, bumps B2 and surface wiring W2 having substantially the same height can be obtained.

When the bump B2 and the surface wiring W2 are made of Au (gold), for example, a TiW (titanium tungsten) film 28 is laminated on the surface protection film 25 by a sputtering method. It may be formed by stacking an Au film 29 on the TiW film 28 by a sputtering method. As described above, according to this embodiment, the pad openings 26 are provided on the surfaces of the parent chip 1 and the child chip 2.
B1, the surface wiring W1 connected to the internal wiring 24B via
W2 is formed, and a sub chip 2 is formed on the surface wiring W1.
Is connected to the bump B2 or the surface wiring W2.
The electrical connection between the parent chip 1 and the child chip 2 can be achieved by connecting the bump B1 of the parent chip 1 or the surface wiring W1 to the element 2. Therefore, the pad openings 26B of the parent chip 1 and the child chip 2 can be formed independently of the pad openings 26A, 26B of the child chip 2 and the parent chip 1, respectively. As a result, the degree of freedom in arranging the internal wirings 24A and 24B and the functional elements of the parent chip 1 and the child chip 2 is increased, and the miniaturization and high integration of the semiconductor device can be achieved.

In this embodiment, the surface wirings W1,
Although the configuration in which W2 is connected only to the internal wiring 24B has been described, for example, the internal wiring 24A and the internal wiring 24B
And surface wirings W1 and W2 can be formed so as to be connected. In this case, the following effects can be achieved. That is, when a new internal wiring is provided above the internal wirings 24A and 25B and the internal wiring 24A and the internal wiring 24B are connected by this internal wiring (in the case of a multilayer wiring), an increase in chip thickness is suppressed. Therefore, the thickness of the new internal wiring cannot be increased, and the wiring resistance of the new internal wiring becomes relatively large. On the other hand, since the surface wirings W1 and W2 have substantially the same height as the bumps B1 and B2, the wiring resistance is relatively small. Therefore, the internal wiring 24A and the internal wiring 2 are formed by the surface wirings W1 and W2.
4B, the parent chip 1 or the child chip 2 having excellent power saving can be realized without increasing the chip thickness.

Further, since the surface wirings W1 and W2 are made of a metal material having oxidation resistance, there is no possibility of being subjected to corrosion due to oxidation. Therefore, the surface wirings W1, W2
It is not necessary to provide a protective film for protecting the internal wiring, and the number of steps can be reduced as compared with a case where the internal wiring has a multilayer structure and the number of wirings is increased. In this embodiment, the bumps B1,
Although B2 and the surface wirings W1 and W2 are made of the same material, the bumps B1 and B2 and the surface wirings W1 and W2 may be made of different materials. In this case, the surface wiring W
1, W2 is formed in a different process from the bumps B1, B2.

FIG. 3 is a cross-sectional view showing a configuration and a manufacturing process of a semiconductor chip according to a second embodiment of the present invention. In this embodiment, the surface wirings 42A and 42B are formed by the seed film 41 laminated on the surface of the semiconductor chip 4 to form the bump B. More specifically, a field oxide film 44 made of, for example, silicon oxide is formed on a semiconductor substrate 43 serving as a base of the semiconductor chip 4.
Internal wirings 45A, 45B, and 45C are provided thereon. Field oxide film 44 and internal wires 45A, 45
The surfaces of B and 45C are covered with a surface protection film 46 having an insulating property, and the surface protection film 46 has pad openings 47A, 47B and 47C, respectively, with internal wirings 45A and 45C.
It is formed facing 45B and 45C. On the pad opening 47A, a bump B made of an oxidation-resistant metal (for example, gold, a lead-based alloy, platinum, silver, palladium, iridium, or an alloy containing them) is formed. On the other hand, the surface wiring 42A is formed on the surface protection film 46, and the surface wiring 42B is connected to the internal wiring 45B via the pad opening 47B and to the internal wiring 45C via the pad opening 47C. It is connected.

When the bumps B and the surface wirings 42A and 42B are formed, first, pad openings 47A and 47B are formed in the surface protection film 46 by, for example, photolithography.
B, 47C are formed. Next, the pad opening 47
A seed film 41 made of an oxidation-resistant material is formed on the surface of the surface protection film 46 on which A, 47B, and 47C are formed, for example, by a sputtering method. Then, a patterning film 48 made of, for example, silicon oxide, silicon nitride, silicon fluoride, SiON or SiOF is formed on the region where the seed film 41 is to be left as the surface wirings 42A and 42B (see FIG. 3A). .

Thereafter, a resist film 49 is formed on the seed film 41 other than the portion facing the pad opening 47A by, for example, a photolithography technique, and then plating using the material of the bump B is performed. As a result, the pad opening 4 is formed on the seed film 41 exposed from the pad opening 47A.
A raised bump B is formed on 7A (see FIG. 3B).

Thereafter, a resist film 49 on the seed film 41 is formed.
Is removed. Then, the seed film 41 is etched using the patterning film 48 as a mask. The seed film 41 is made of a TiW (titanium tungsten) film 41A and Au.
When the Au film (B) 41B is formed of a laminate, the Au film (B) 41B is etched using a chemical such as KI / I (aqueous potassium iodide solution), and then a chemical such as hydrogen peroxide is used. Is used to etch titanium tungsten film 41A. Thereby, the surface of the bump B is thinly etched, and the portion of the seed film 41 that is not in contact with the bump B and the patterning film 48 is removed, so that the bump B and the surface wirings 42A and 42B can be obtained (FIG. 3 (c)). )).

The patterning film 48 on the surface wirings 42A and 42B may be removed after etching the seed film 41, or may be left as it is. According to this embodiment, the seed film 4 used for forming the bump B is used.
When 1 is removed, the surface wirings 42A and 42B can be formed by selectively removing the seed film 41, so that there is no need to prepare a material for the surface wirings 42A and 42B. Therefore, an increase in cost due to the provision of the surface wirings 42A and 42B can be suppressed.

Further, since the seed film 41 forming the surface wirings 42A and 42B is made of a material having oxidation resistance, there is no possibility that the surface wirings 42A and 42B are corroded by oxidation. Therefore, there is no need to provide a protective film for protecting the surface wirings 42A and 42B, and the number of steps can be reduced as compared with the case where the number of wirings is increased by forming the internal wirings into a multilayer structure.

Note that the seed film 41 exposed by removing the resist film 49 after the formation of the bump B without forming the patterning film 48 is selectively removed by photolithography to form the surface wiring 42.
A and 42B may be formed. However, when the height of the bump B is large (for example, about 10 μm), it is difficult to pattern the seed film 41 precisely.
As in this embodiment, the seed film 4 is formed before the bump B is formed.
It is preferable that a patterning film 48 is formed on the substrate 1.

Although the two embodiments of the present invention have been described above, the present invention is not limited to the above embodiments. For example, in the above-described first embodiment, the parent chip and the child chip are both chips made of silicon. However, in addition to silicon, any other semiconductor material such as a gallium arsenide semiconductor or a germanium semiconductor may be used. May be used. In this case, the semiconductor material of the parent chip and the semiconductor material of the child chip may be the same or different.

In the first embodiment, the surface wiring is provided on each of the parent chip and the child chip. However, the surface wiring is provided only on one of the parent chip and the child chip, and the other surface is provided on this surface wiring. Chip-on-chip bonding may be performed by connecting bumps of the chip.
In addition, one of the bumps and the surface wiring of the parent chip or the child chip may be formed of a metal film (for example, a vapor-deposited film) that is not raised as high as the bumps.

In addition, various design changes can be made within the scope of the matters described in the claims.

[Brief description of the drawings]

FIG. 1 is an illustrative sectional view showing a schematic configuration of a semiconductor device according to an embodiment of the present invention.

FIG. 2 is an enlarged sectional view showing a configuration of a parent chip and a child chip.

FIG. 3 is a cross-sectional view showing a configuration and a manufacturing process of a semiconductor chip according to a second embodiment of the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Parent chip (1st or 2nd semiconductor chip) 11 Surface (1st or 2nd semiconductor chip) 2 Child chip (2nd or 1st semiconductor chip) 21 Surface (2nd or 1st semiconductor) 24A, 24B Internal wiring 25 Surface protection film 26A, 26B Pad opening B1, B2 Bump W1, W2 Surface wiring 4 Semiconductor chip 41 Seed film 42A, 42B Surface wiring 45A, 45B, 45C Internal wiring 46 Surface protection film 47A, 47B, 47C Pad opening B bump

Claims (5)

[Claims] A first semiconductor chip having a pad opening for partially exposing an internal wiring formed on a surface thereof; and a first semiconductor chip superposed and joined to the surface of the first semiconductor chip. A second semiconductor chip in which a pad opening for partially exposing internal wiring is formed on a surface facing the semiconductor chip; and a first opening through the pad opening of the first semiconductor chip. A surface wiring electrically connected to the internal wiring of the semiconductor chip; and a wiring connecting portion connecting the surface wiring and the internal wiring exposed through the pad opening of the second semiconductor chip. Semiconductor device with a chip-on-chip structure. A surface protection film covering the internal wiring; a pad opening formed in the surface protection film to expose a part of the internal wiring; and a pad opening formed on the surface protection film. And a surface wiring electrically connected to the internal wiring via a portion. 3. The semiconductor chip according to claim 2, wherein said surface wiring is made of a material having oxidation resistance. 4. A bump formed by laminating a seed film on the surface of the surface protection film having the pad opening formed thereon and selectively plating the seed film in the pad opening, 4. The semiconductor chip according to claim 2, wherein the surface wiring is formed by patterning the seed film. 5. The semiconductor chip according to claim 4, wherein said surface wiring and said bump are made of the same material.