JPH06120406A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH06120406A JPH06120406A JP4264795A JP26479592A JPH06120406A JP H06120406 A JPH06120406 A JP H06120406A JP 4264795 A JP4264795 A JP 4264795A JP 26479592 A JP26479592 A JP 26479592A JP H06120406 A JPH06120406 A JP H06120406A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor device
- lead frame
- transistor
- lead
- tie bar
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
Landscapes
- Lead Frames For Integrated Circuits (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】この発明は、リードフレーム上に
トランジスタ素子、半導体素子および受動部品を搭載
し、一体樹脂成形して、チップ部品複合化した、いわゆ
るＭＣＰ（Multi Chip Package)の半導体装置に関し、
特にリードフレームのタイバ部のカット時に生じる応力
を吸収できる半導体装置のリードフレーム構造に関する
ものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a so-called MCP (Multi Chip Package) semiconductor device in which a transistor element, a semiconductor element and a passive component are mounted on a lead frame and integrally molded with resin to form a composite chip component. ,
In particular, the present invention relates to a lead frame structure of a semiconductor device capable of absorbing stress generated when cutting the tie bar portion of the lead frame.
【０００２】[0002]
【従来の技術】図５および図６はそれぞれ従来の半導体
装置における樹脂封止前および樹脂封止後の状態を示す
斜視図であり、図において１はリードフレームであり、
このリードフレーム１はシリコン基板上にパワートラン
ジスタが形成されたトランジスタ素子２を搭載するトラ
ンジスタ素子搭載部１ａ、トランジスタ素子２を制御す
る半導体素子３を搭載する半導体素子搭載部１ｂ、トラ
ンジスタ素子２および半導体素子３の電極パッドとの間
でワイヤボンディングされるインナーリード１ｃおよび
外部との電気信号のやり取りを行うアウターリード１ｄ
からなり、トランジスタ素子搭載部１ａの厚みを厚く、
半導体素子搭載部１ｂ、インナーリード１ｃおよびアウ
ターリード１ｄの厚みを一様に構成し、それぞれタイバ
部４により結合されている。５は受動部品としてのチッ
プ抵抗素子、６はチップ抵抗素子５をリードフレーム１
上に接合する半田、７はボンディング用のワイヤとして
の金線、８は封止樹脂である。2. Description of the Related Art FIGS. 5 and 6 are perspective views showing states of a conventional semiconductor device before and after resin encapsulation, in which 1 is a lead frame,
The lead frame 1 includes a transistor element mounting portion 1a for mounting a transistor element 2 having a power transistor formed on a silicon substrate, a semiconductor element mounting portion 1b for mounting a semiconductor element 3 for controlling the transistor element 2, a transistor element 2 and a semiconductor. Inner leads 1c wire-bonded to the electrode pads of the element 3 and outer leads 1d for exchanging electrical signals with the outside.
And the thickness of the transistor element mounting portion 1a is increased,
The semiconductor element mounting portion 1b, the inner lead 1c, and the outer lead 1d have a uniform thickness and are connected by the tie bar portion 4. 5 is a chip resistance element as a passive component, 6 is the chip resistance element 5 as a lead frame 1
Solder bonded on top, 7 is a gold wire as a wire for bonding, and 8 is a sealing resin.
【０００３】このように構成された従来の半導体装置を
組み立てるには、まず、例えば銅合金をプレス成形して
リードフレーム１を形成する。ついで、トランジスタ素
子搭載部１ａおよび半導体素子搭載部１ｂ上にそれぞれ
トランジスタ素子２および半導体素子３をダイボンディ
ングする。また、所望のインナーリード１ｃ間にチップ
抵抗素子５を半田６により接合する。つぎに、トランジ
スタ素子２および半導体素子３の電極パッドと所望のイ
ンナーリード１ｃとの間を金線７を用いてワイヤボンデ
ィングして、図５に示すように、トランジスタ素子２、
半導体素子３およびチップ抵抗素子５がリードフレーム
１上に搭載される。To assemble the conventional semiconductor device having such a structure, first, for example, a copper alloy is press-molded to form the lead frame 1. Next, the transistor element 2 and the semiconductor element 3 are die-bonded on the transistor element mounting portion 1a and the semiconductor element mounting portion 1b, respectively. Further, the chip resistance element 5 is joined with the solder 6 between the desired inner leads 1c. Next, wire bonding is performed between the electrode pads of the transistor element 2 and the semiconductor element 3 and the desired inner lead 1c using the gold wire 7, and as shown in FIG.
The semiconductor element 3 and the chip resistance element 5 are mounted on the lead frame 1.
【０００４】その後、封止樹脂８、例えばエポキシ樹脂
を用いて、図６に示すように、モールディングする。こ
の時、トランジスタ素子搭載部１ａの底面は封止樹脂８
から露呈するようにモールディングされている。さら
に、タイバ部４をカットして、トランジスタ素子２、半
導体素子３およびチップ抵抗素子６が１パッケージに複
合化された半導体装置が得られる。After that, a sealing resin 8 such as an epoxy resin is used for molding as shown in FIG. At this time, the bottom surface of the transistor element mounting portion 1a is covered with the sealing resin 8
It is molded so as to be exposed from. Further, the tie bar portion 4 is cut to obtain a semiconductor device in which the transistor element 2, the semiconductor element 3 and the chip resistance element 6 are combined into one package.
【０００５】つぎに、上記従来の半導体装置の動作につ
いて説明する。半導体素子３は、トランジスタ素子２の
通電電流をチップ抵抗素子６の両端の電圧を検出するこ
とにより、トランジスタ電流をコントロールする。ま
た、トランジスタ素子２に通電することによりトランジ
スタ素子２で発生する熱は、トランジスタ素子搭載部１
ａの底面から放熱される。Next, the operation of the above conventional semiconductor device will be described. The semiconductor element 3 controls the transistor current by detecting the current across the transistor element 2 and the voltage across the chip resistor element 6. In addition, the heat generated in the transistor element 2 by energizing the transistor element 2 is the same as that of the transistor element mounting portion 1.
Heat is radiated from the bottom surface of a.
【０００６】[0006]
【発明が解決しようとする課題】従来の半導体装置は以
上のように構成されているので、タイバ部４をカットす
る際に生じる引っ張り力が、アウターリード１ｄを介し
てインナーリード１ｃに加わり、インナーリード１ｃ間
に搭載されたチップ抵抗素子５に亀裂を発生させ、ある
いはチップ抵抗素子５の半田６からの剥離を発生させ、
チップ抵抗素子５の両端に生じる電圧が不安定となり、
半導体装置の動作の信頼性を低下させるという課題があ
った。Since the conventional semiconductor device is constructed as described above, the pulling force generated when the tie bar portion 4 is cut is applied to the inner lead 1c through the outer lead 1d, The chip resistance element 5 mounted between the leads 1c is cracked, or the chip resistance element 5 is peeled from the solder 6,
The voltage generated across the chip resistance element 5 becomes unstable,
There is a problem that the reliability of the operation of the semiconductor device is reduced.
【０００７】この発明は、上記のような課題を解決する
ためになされたもので、タイバ部をカットする際に生じ
る引っ張り力によるインナーリード側への応力を低減
し、搭載される受動部品の破損あるいは半田からの受動
部品の剥離を防止して、信頼性に優れた半導体装置を得
ることを目的とする。The present invention has been made to solve the above problems, and reduces the stress on the inner lead side due to the pulling force generated when the tie bar is cut, thereby damaging the mounted passive components. Alternatively, it is an object of the present invention to obtain a highly reliable semiconductor device by preventing separation of passive components from solder.
【０００８】[0008]
【課題を解決するための手段】この発明に係る半導体装
置は、リードフレーム上にトランジスタ素子、このトラ
ンジスタ素子を制御する半導体素子および受動部品を搭
載し、一体樹脂成形された半導体装置において、受動部
品を搭載したリードフレームのアウターリード側に応力
吸収部を設けたものである。According to another aspect of the present invention, there is provided a semiconductor device in which a transistor element, a semiconductor element for controlling the transistor element, and a passive component are mounted on a lead frame, and the semiconductor device is integrally resin-molded. The stress absorbing portion is provided on the outer lead side of the lead frame on which is mounted.
【０００９】[0009]
【作用】この発明においては、受動部品を搭載したリー
ドフレームのアウターリード側に応力吸収部が設けられ
ているので、リードフレームのタイバ部をカットする際
に生じる引っ張り力によりアウターリードを介してイン
ナーリードに作用する応力はこの応力吸収部により吸収
され、受動部品を接合する半田部に加わる応力が緩和さ
れる。In the present invention, since the stress absorbing portion is provided on the outer lead side of the lead frame on which the passive component is mounted, the inner frame is pulled through the outer lead by the pulling force generated when the tie bar portion of the lead frame is cut. The stress acting on the lead is absorbed by this stress absorbing portion, and the stress applied to the solder portion joining the passive components is relieved.
【００１０】[0010]
【実施例】以下、この発明の実施例を図について説明す
る。 実施例１．図１および図２はそれぞれこの発明の実施例
１を示す半導体装置における樹脂封止前および樹脂封止
後の状態の斜視図、図３はこの発明の実施例１を示す半
導体装置の要部拡大斜視図であり、図において図５およ
び図６に示した従来の半導体装置と同一または相当部分
には同一符号を付し、その説明を省略する。Embodiments of the present invention will be described below with reference to the drawings. Example 1. 1 and 2 are perspective views of a semiconductor device showing a first embodiment of the present invention before and after resin encapsulation, and FIG. 3 is an enlarged main part of a semiconductor device showing the first embodiment of the present invention. FIG. 7 is a perspective view, in which the same or corresponding portions as those of the conventional semiconductor device shown in FIGS. 5 and 6 are designated by the same reference numerals, and description thereof will be omitted.
【００１１】図において、９はチップ抵抗素子５が搭載
されたインナーリード１ｃのアウターリード１ｄ側に設
けられた応力吸収部としての溝である。In the figure, 9 is a groove as a stress absorbing portion provided on the outer lead 1d side of the inner lead 1c on which the chip resistance element 5 is mounted.
【００１２】この実施例１による半導体装置は、チップ
抵抗素子５が所望のインナーリード１ｃ間に半田６によ
り接合され、このインナーリード１ｃのチップ抵抗素子
５搭載部よりアウターリード１ｄ側の部位に溝９を設け
ている。なお、他の構成は、図５および図６に示した従
来の半導体装置と同じ構成である。In the semiconductor device according to the first embodiment, the chip resistance element 5 is joined between the desired inner leads 1c by the solder 6, and a groove is formed in a portion of the inner lead 1c closer to the outer lead 1d than the chip resistance element 5 mounting portion. 9 is provided. The other structure is the same as that of the conventional semiconductor device shown in FIGS.
【００１３】このように構成された上記実施例１によれ
ば、封止樹脂８でモールディングした後、タイバ部４を
カットする際にリードフレーム１に作用する引っ張り力
は溝９で吸収され、チップ抵抗素子５搭載部に加わる応
力は緩和される。According to the above-described first embodiment, the pulling force acting on the lead frame 1 when the tie bar portion 4 is cut after being molded by the sealing resin 8 is absorbed by the groove 9 and the chip 9 is formed. The stress applied to the mounting portion of the resistance element 5 is relaxed.
【００１４】したがって、上記実施例１によれば、チッ
プ抵抗素子５に亀裂が発生したり、チップ抵抗素子５が
半田６から剥離したりすることが防止でき、動作の信頼
性を向上することができるという効果がある。Therefore, according to the first embodiment, it is possible to prevent the chip resistance element 5 from cracking and the chip resistance element 5 from peeling off from the solder 6, thereby improving the reliability of operation. The effect is that you can do it.
【００１５】実施例２．上記実施例１では、インナーリ
ード１ｃのチップ抵抗素子５搭載部よりアウターリード
１ｄ側の部位に溝９を設けるものとしているが、この実
施例２では、図４に示すように、インナーリード１ｃの
チップ抵抗素子５搭載部よりアウターリード１ｄ側の部
位に折り曲げ部１０を設け、タイバ部４をカットする際
にリードフレーム１に作用する引っ張り力を折り曲げ部
１０の段差で吸収するものとし、同様の効果を奏する。Example 2. In the first embodiment, the groove 9 is provided in the portion of the inner lead 1c closer to the outer lead 1d than the chip resistance element 5 mounting portion. However, in the second embodiment, as shown in FIG. The bending portion 10 is provided in a portion closer to the outer lead 1d than the mounting portion of the chip resistance element 5, and the pulling force acting on the lead frame 1 when the tie bar portion 4 is cut is absorbed by the step of the bending portion 10. Produce an effect.
【００１６】なお、上記各実施例では、受動部品として
チップ抵抗素子５を用いるものとして説明しているが、
受動部品は抵抗素子に限らず、例えばコンデンサ素子、
コイル素子であってもよい。In the above embodiments, the chip resistance element 5 is used as a passive component, but
Passive components are not limited to resistive elements, but include, for example, capacitor elements,
It may be a coil element.
【００１７】[0017]
【発明の効果】以上のようにこの発明によれば、リード
フレーム上にトランジスタ素子、このトランジスタ素子
を制御する半導体素子および受動部品を搭載し、一体樹
脂成形された半導体装置において、受動部品を搭載した
リードフレームのアウターリード側に応力吸収部を設け
ているので、リードフレームのタイバ部をカットする際
に生じる引っ張り力により受動部品の搭載部に作用する
応力が応力吸収部で吸収され、受動部品の搭載部に作用
する応力が緩和され、受動部品の亀裂の発生や受動部品
の剥離が抑えられ、信頼性の向上を図ることができる半
導体装置が得られる効果がある。As described above, according to the present invention, a transistor element, a semiconductor element for controlling the transistor element and a passive component are mounted on a lead frame, and the passive component is mounted in a semiconductor device integrally molded with resin. Since the stress absorbing part is provided on the outer lead side of the lead frame, the stress acting on the mounting part of the passive component is absorbed by the stress absorbing part due to the tensile force generated when cutting the tie bar part of the lead frame, There is an effect that the stress acting on the mounting portion of the semiconductor device is relaxed, cracking of the passive component and peeling of the passive component are suppressed, and the reliability of the semiconductor device can be improved.
【図１】この発明の実施例１を示す半導体装置における
樹脂封止前の状態の斜視図である。FIG. 1 is a perspective view of a semiconductor device showing a first embodiment of the present invention before resin sealing.
【図２】この発明の実施例１を示す半導体装置における
樹脂封止後の状態の斜視図である。FIG. 2 is a perspective view of a semiconductor device showing a first embodiment of the present invention after resin sealing.
【図３】この発明の実施例１を示す半導体装置の要部拡
大斜視図である。FIG. 3 is an enlarged perspective view of a main part of the semiconductor device showing the first embodiment of the present invention.
【図４】この発明の実施例２を示す半導体装置の要部拡
大斜視図である。FIG. 4 is an enlarged perspective view of a main part of a semiconductor device showing a second embodiment of the present invention.
【図５】従来の半導体装置における樹脂封止前の状態を
示す斜視図である。FIG. 5 is a perspective view showing a state before resin sealing in a conventional semiconductor device.
【図６】従来の半導体装置における樹脂封止後の状態を
示す斜視図である。FIG. 6 is a perspective view showing a state after resin sealing in a conventional semiconductor device.
１ リードフレーム １ｄ アウターリード ２ トランジスタ素子 ３ 半導体素子 ５ チップ抵抗素子（受動部品） ８ 封止樹脂 ９ 溝（応力吸収部） １０ 折り曲げ部（応力吸収部） 1 Lead Frame 1d Outer Lead 2 Transistor Element 3 Semiconductor Element 5 Chip Resistive Element (Passive Component) 8 Sealing Resin 9 Groove (Stress Absorption Part) 10 Bent Part (Stress Absorption Part)
─────────────────────────────────────────────────────
─────────────────────────────────────────────────── ───
【手続補正書】[Procedure amendment]
【提出日】平成５年２月１６日[Submission date] February 16, 1993
【手続補正１】[Procedure Amendment 1]
【補正対象書類名】明細書[Document name to be amended] Statement
【補正対象項目名】００１６[Correction target item name] 0016
【補正方法】変更[Correction method] Change
【補正内容】[Correction content]
【００１６】なお、上記各実施例では、受動部品として
チップ抵抗素子５を用いるものとして説明しているが、
受動部品は抵抗素子に限らず、例えばコンデンサ素子、
コイル素子であってもよく、さらにボンディング用のワ
イヤとして金線７を用いるものとして説明しているが、
金線７に限らずアルミ線を用いてもよい。In the above embodiments, the chip resistance element 5 is used as a passive component, but
Passive components are not limited to resistive elements, but include, for example, capacitor elements,
Rather it may also be a coil element, a further sum of bonding
Although it is explained that the gold wire 7 is used as an ear,
Be used aluminum wire is not limited to the gold wire 7 not good.
Claims (1)
前記トランジスタ素子を制御する半導体素子および受動
部品を搭載し、一体樹脂成形された半導体装置におい
て、前記受動部品を搭載した前記リードフレームのアウ
ターリード側に応力吸収部を設けたことを特徴とする半
導体装置。1. A transistor element on a lead frame,
In a semiconductor device in which a semiconductor element for controlling the transistor element and a passive component are mounted and integrally molded by resin, a stress absorbing portion is provided on the outer lead side of the lead frame on which the passive component is mounted. apparatus.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4264795A JPH06120406A (en) | 1992-10-02 | 1992-10-02 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4264795A JPH06120406A (en) | 1992-10-02 | 1992-10-02 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH06120406A true JPH06120406A (en) | 1994-04-28 |
Family
ID=17408315
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4264795A Pending JPH06120406A (en) | 1992-10-02 | 1992-10-02 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH06120406A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007234737A (en) * | 2006-02-28 | 2007-09-13 | Denso Corp | Connection structure of electronic component |
| JP2009129952A (en) * | 2007-11-20 | 2009-06-11 | Denso Corp | Semiconductor device |
| US7719095B2 (en) | 2007-12-05 | 2010-05-18 | Kabushiki Kaisha Toshiba | Lead frame and semiconductor device provided with lead frame |
| JP2014093353A (en) * | 2012-11-01 | 2014-05-19 | Denso Corp | Semiconductor device and semiconductor device manufacturing method |
| US9917064B2 (en) | 2014-10-16 | 2018-03-13 | Mitsubishi Electric Corporation | Semiconductor device with a plate-shaped lead terminal |
-
1992
- 1992-10-02 JP JP4264795A patent/JPH06120406A/en active Pending
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007234737A (en) * | 2006-02-28 | 2007-09-13 | Denso Corp | Connection structure of electronic component |
| JP4640214B2 (en) * | 2006-02-28 | 2011-03-02 | 株式会社デンソー | Electronic component connection structure |
| JP2009129952A (en) * | 2007-11-20 | 2009-06-11 | Denso Corp | Semiconductor device |
| US7719095B2 (en) | 2007-12-05 | 2010-05-18 | Kabushiki Kaisha Toshiba | Lead frame and semiconductor device provided with lead frame |
| JP2014093353A (en) * | 2012-11-01 | 2014-05-19 | Denso Corp | Semiconductor device and semiconductor device manufacturing method |
| US9917064B2 (en) | 2014-10-16 | 2018-03-13 | Mitsubishi Electric Corporation | Semiconductor device with a plate-shaped lead terminal |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A02 | Decision of refusal |
Effective date: 20040427 Free format text: JAPANESE INTERMEDIATE CODE: A02 |