JPH0250438A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH0250438A
JPH0250438A JP63199857A JP19985788A JPH0250438A JP H0250438 A JPH0250438 A JP H0250438A JP 63199857 A JP63199857 A JP 63199857A JP 19985788 A JP19985788 A JP 19985788A JP H0250438 A JPH0250438 A JP H0250438A
Authority
JP
Japan
Prior art keywords
semiconductor chip
leads
chip
insulating film
bonding
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP63199857A
Other languages
Japanese (ja)
Other versions
JP2585738B2 (en
Inventor
Toshiyuki Sakuta
俊之 作田
Kazuyuki Miyazawa
一幸 宮沢
Satoshi Oguchi
聡 小口
Aizo Kaneda
金田　愛三
Masao Mitani
正男 三谷
Shozo Nakamura
省三 中村
Kunihiko Nishi
邦彦 西
Hajime Murakami
元 村上
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP63199857A priority Critical patent/JP2585738B2/en
Publication of JPH0250438A publication Critical patent/JPH0250438A/en
Application granted granted Critical
Publication of JP2585738B2 publication Critical patent/JP2585738B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/1012—Auxiliary members for bump connectors, e.g. spacers
    • H01L2224/10122—Auxiliary members for bump connectors, e.g. spacers being formed on the semiconductor or solid-state body to be connected
    • H01L2224/10125—Reinforcing structures
    • H01L2224/10126—Bump collar
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/4826—Connecting between the body and an opposite side of the item with respect to the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06—Polymers
    • H01L2924/078—Adhesive characteristics other than chemical
    • H01L2924/07802—Adhesive characteristics other than chemical not being an ohmic electrical conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Semiconductor Memories (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Wire Bonding (AREA)
  • Die Bonding (AREA)

Abstract

PURPOSE:To reduce the size of a semiconductor device by a method wherein a rectangular semiconductor chip or the like having a plurality of bonding pads on its center part is employed. CONSTITUTION:Bonding pads P7-P14 are provided on the part near the center of a semiconductor chip 1. After the surface of the semiconductor chip 1 on which the pads are formed is bonded and fixed to the rear of the leads of a lead frame by insulating adhesive 4 with an organic insulating film between, tip surfaces of inner leads provided on the surface side of the chip and the bonding pad parts are connected to each other by wire bonding and sealed with molding resin. Therefore, the leads do not protrude from the semiconductor chip. With this constitution, the size of a semiconductor device can be reduced corresponding to the extent of the protruding leads.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発８Ａは半導体装置、特にサイズの大きい長方形のＬ
ＳＩチップを小屋のパッケージに搭載するのに好適なチ
ップ構造およびパッケージの構造を有する樹脂封止形半
導体装置に関する。[Detailed description of the invention] [Industrial application field] The present invention 8A is a semiconductor device, especially a large rectangular L
The present invention relates to a resin-sealed semiconductor device having a chip structure and a package structure suitable for mounting an SI chip in a shed package.

〔従来の技術〕[Conventional technology]

従来、ＬＳＩチップをグラスチックパッケージに搭載す
る方法としては、パッケージの中央部にチップを搭載す
るためのタブが配置され、４辺にボンディングパッド部
が配置されたチップを該タブ上に導電性ペーストで接着
・搭載１．、リードフレームのリード先端部を該チップ
の４辺方向に配置して、該パッド部と該リード先端部と
を金線で相互結線し、レジンモールドする構造をとって
きた。Conventionally, as a method for mounting an LSI chip on a glass package, a tab for mounting the chip is placed in the center of the package, and the chip, which has bonding pads on the four sides, is placed on top of the tab using conductive paste. Adhesive and mounting 1. , a structure has been adopted in which the lead ends of the lead frame are arranged in the direction of the four sides of the chip, the pad parts and the lead ends are mutually connected with gold wire, and resin molded.

しかし、この構造では、チップとリード先端部との距離
を、金線が結線できる距離にまでとる必要があり、チッ
プの外端とパッケージの外端部までの距離が大きくなり
、大きなチップを小さなパッケージに収納するには幾何
学的な制約があった。However, with this structure, the distance between the chip and the lead tip needs to be long enough to connect the gold wire, which increases the distance between the outer edge of the chip and the outer edge of the package, making it possible to convert a large chip into a small one. There were geometrical constraints on how to fit it into a package.

さらは、リードのパッケージへの埋込み長さが小さく々
す、・外部リード成形時の機械的ストレスによる内部リ
ードとレジンとの界面の剥離が経験され、特にチップの
短辺方向に対し、パッケージの短辺長さを大きく設計す
る必要がありだ。Furthermore, the embedded length of the leads in the package is too small, and peeling of the interface between the internal leads and the resin due to mechanical stress during external lead molding has been experienced, especially in the short side direction of the chip. It is necessary to design the short side length to be large.

また、さらは、チップ寸法大のタブがパッケージの中央
部に配置されているためは、熱応力によるタブ下のレジ
ンの界面剥離と、それにともなう、タブ下にむか５レジ
ンのクラックがしばしば経験され、温度サイクルや耐り
７０−試験の結果を満足させるだめの好適な構造とは云
えなくなりてきた。Furthermore, since the chip-sized tab is placed in the center of the package, interface peeling of the resin under the tab due to thermal stress and resulting cracking of the resin toward the bottom of the tab are often experienced. It can no longer be said that this is a suitable structure that satisfies the results of the temperature cycle and durability tests.

上記、問題点に対処するためは、特開昭６０−１、６７
４５４号、特開昭６１−２１８１３９号及びＵＳＰ４．
６１２．５６４に提案されているようは、リードフレー
ムのリード先端をすべてチップの短辺側に配置し、タブ
をなくして、そのリード上に絶縁フィルムを接着剤で張
りつけ、そのフィルム上にデツプをダイボンディングし
て、該チップのボンディングパッド部とリード先端部と
を金線で相互結線するワイヤボンディング構造、いわゆ
るｃｈｌｐｏｐ　１ｅａｄ　　タイプのタブレスパッケ
ージが提案されている。In order to deal with the above problems, JP-A-60-1, 67
No. 454, JP-A No. 61-218139 and USP 4.
As proposed in 612.564, all the lead ends of the lead frame are placed on the short side of the chip, the tabs are eliminated, an insulating film is pasted on the leads with adhesive, and a depth is placed on the film. A so-called chlpop lead type tableless package has been proposed, which has a wire bonding structure in which the bonding pad portion of the chip and the lead tip portion of the chip are mutually connected with a gold wire through die bonding.

さらは、同様の問題点に対処するためは、特開昭５９−
９２５５６号及び特開昭６１−２３６１３０号に開示さ
れているようは、チップ上に接着剤でリードを接着し、
チップ上部に位置するリード先端部とチップのダンディ
ングパッドとを金線等で相互結線するワイヤボンディン
グ構造、いわゆるリードオンチップタイプのタブレスパ
ッケージが提案されている。Furthermore, in order to deal with the same problem,
As disclosed in No. 92556 and Japanese Unexamined Patent Publication No. 61-236130, leads are bonded onto the chip with an adhesive;
A so-called lead-on-chip type tableless package has been proposed, which has a wire bonding structure in which lead tips located on the top of the chip and dangling pads of the chip are interconnected using gold wire or the like.

〔発明が解決しようとする！ＩＭ１ 本発明者の検討によれば、前述の従来技術には次のよう
な問題点があることが判明した。[Invention tries to solve! IM1 According to the study conducted by the present inventor, it has been found that the above-mentioned conventional technology has the following problems.

前述のｌ・ａｄ　ｏｎ　ｃｈｉｐ　　タイプのタブレス
パッケージの半導体装置では、絶縁フィルム上のチップ
のボンディングパッド部と内部リード先端部とをワイヤ
ボンディングする方式のため、リード先端部はチップ長
辺よりもワイヤボンディングする距離分だけ長く設計す
る必要があり、レジンモールド時にボンディングワイヤ
が変形しチップ端部と接触しないようは、チップ長辺の
端部とパッケージ長辺の端部との距離を大きく設計する
必要があり、真に大きなチップを小さなパッケージに搭
載するＯに適した構造とは云えなかった。In the aforementioned l-ad on chip type tablets package semiconductor device, the bonding pad portion of the chip on the insulating film and the tip of the internal lead are wire-bonded, so the tip of the lead is closer to the wire than the long side of the chip. It is necessary to design it as long as the bonding distance, and to prevent the bonding wire from deforming and contacting the chip edge during resin molding, it is necessary to design a large distance between the long edge of the chip and the long edge of the package. Therefore, it could not be said that the structure was suitable for mounting a truly large chip in a small package.

また、前述の両タイプのタブレスパッケージの半導体装
置において、チップ上のボンディングパッドがチップ外
端部に位置している場合には、高温で樹脂モールドされ
た半導体装置が常温にもどる際は、半導体チップと樹脂
との膨張係数の違いにより生じる熱応力がチップの中央
より端の方で大きい為、ボンディングパッドとワイヤと
の接続部にＩＩＪＪＷｉＴ応力がかかり、疲労破断し易
い。In addition, in the semiconductor devices of both types of tableless packages mentioned above, if the bonding pad on the chip is located at the outer edge of the chip, when the semiconductor device molded with resin at high temperature returns to room temperature, the semiconductor device Since the thermal stress caused by the difference in expansion coefficient between the chip and the resin is greater at the edges than at the center of the chip, IIJJWiT stress is applied to the connection between the bonding pad and the wire, making it prone to fatigue fracture.

また、チップ上のボンディングパッドがチップ外端部に
位置している場合には、例えばダイナミックＲＡ　Ｍ　
（Ｒａｎｄｏｍ　Ａｃｃｅｓｓ　Ｍｅｍｏｒ７　）　、
　　スタティックＲＡＭ、ＲＯＭ等のメモリにおいては
、メモリセル部以外の周辺回路がチップ両端部に設けら
れている。その為、チップ両端部の周辺回路間を結ぶ配
線が長くなり配線抵抗Ｒ及び配線容量Ｃによる配線を伝
わる信号のＲｅ遅延が大きい。In addition, if the bonding pads on the chip are located at the outer edge of the chip, for example, dynamic RAM
(Random Access Memor7),
In memories such as static RAM and ROM, peripheral circuits other than the memory cell section are provided at both ends of the chip. Therefore, the wiring connecting the peripheral circuits at both ends of the chip becomes long, and the Re delay of the signal transmitted through the wiring due to the wiring resistance R and the wiring capacitance C becomes large.

さらは、前述のｌ＠息ｄ　ｏｎ　ｃｈｉｐ　　タイプの
半導体装置において、ボンディングパッドをチップの内
側に設けた場合、リードへのワイヤボンディングの際は
、下に位置するチップ表面を保膿している無機パッジペ
ージ璽ン膜にり２ツクが発生する。Furthermore, in the above-described on-chip type semiconductor device, when the bonding pad is provided inside the chip, when wire bonding to the lead, the underlying chip surface is exposed to the inorganic Two scratches occur on the pudge page seal.

本発明の目的は、半導体装置のサイズの縮小を図ること
ができる技術を提供することにある。An object of the present invention is to provide a technique that can reduce the size of a semiconductor device.

本発明の他の目的は、樹脂による応力によりボンディン
グパッドとワイヤーとのボンディング部で破断が生じる
のを防止することができる技術を提供することにある。Another object of the present invention is to provide a technique that can prevent breakage at the bonding portion between the bonding pad and the wire due to stress caused by the resin.

本発明の他の目的は、配線が長いことによる信号の遅延
を防止することができる技術を提供することにある。Another object of the present invention is to provide a technique that can prevent signal delays due to long wiring.

本発明の他の目的は、半導体チップのパッジベージ嘗ン
膜に発生するクラックを防止することにある。Another object of the present invention is to prevent cracks from occurring in the padding film of a semiconductor chip.

本発明の前記ならびにその他の目的と新規な特徴は、本
明細書の記述及び添付図面によって明らかになるであろ
う。The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

〔課題を屏決するための手段〕[Means for deciding issues]

本願において開示される発明のうち、代表的なもののＩ
＋［を簡単に説明すれば、下記のとおりである。Among the inventions disclosed in this application, I
A simple explanation of +[ is as follows.

すなわち、半導体チップのほぼ中央部にボンディングパ
ッドが設けられ、半導体チップのパッドの形成された表
面とリードフレームのリード裏面とを有機絶縁膜を介し
て絶縁性接着剤で接着固定したのち、該チップ表面側に
配置された内部リードの先端部表面と該ボンディングパ
ッド部とをワイヤボンディングして、モールドレジンで
封止したことを特徴とする。That is, a bonding pad is provided approximately at the center of a semiconductor chip, and the pad-formed surface of the semiconductor chip and the back surface of the leads of a lead frame are bonded and fixed with an insulating adhesive via an organic insulating film, and then the chip is bonded. A feature is that the front end surface of the internal lead disposed on the front side and the bonding pad are wire-bonded and sealed with mold resin.

又、半導体チップのほぼ中央部にボンディングパッド及
び周辺回路が設けられた半導体テップのパッドの形成さ
れた弐面とリードフレームのリード裏面とが有機絶縁膜
を介して絶縁性接着剤で接着固定され、さらにボンディ
ングパッドと内部リードの先端部がワイヤで接続されて
おり、内部リード、半導体チップ及びワイヤがモールド
レジンで封止されていることを％徴とする。Further, the pad-formed second side of the semiconductor chip, in which bonding pads and peripheral circuits are provided approximately at the center of the semiconductor chip, and the lead back side of the lead frame are adhesively fixed with an insulating adhesive through an organic insulating film. Furthermore, the bonding pad and the tip of the internal lead are connected by a wire, and the internal lead, semiconductor chip, and wire are sealed with mold resin.

〔作用〕[Effect]

上記した手段によれば、半導体チップからリードがはみ
出さないようにすることができるので、その分だけ半導
体装置のサイズの縮小を図ることができる。また、半導
体チップの中央部では、樹脂モールド後に常温にもどる
際に生じる半導体チップと樹脂との界面の応力が最も小
さいので、この応力によりボンディングパッドとワイヤ
ーとのボンディング部で破断が生じるのを防止すること
ができる。′：！−らは、半導体テップのほぼ中央部に
周辺回路が設けられているために配線の長さを短くする
ことができるので、Ｒｅ遅延を小さくすることができ、
従って配線が長いことによる信号の遅延を防止すること
ができる。According to the above-described means, it is possible to prevent the leads from protruding from the semiconductor chip, so that the size of the semiconductor device can be reduced accordingly. In addition, in the center of the semiconductor chip, the stress at the interface between the semiconductor chip and the resin that occurs when the temperature returns to room temperature after resin molding is the smallest, so this stress prevents breakage at the bonding area between the bonding pad and the wire. can do. ′:! - Since the peripheral circuit is provided almost in the center of the semiconductor chip, the length of the wiring can be shortened, so the Re delay can be reduced.
Therefore, signal delays due to long wiring can be prevented.

〔実施例〕〔Example〕

＠１図〜第４図に示すようは、本冥施例による樹脂封止
ＤＩＰパッケージにおいては、例えば４メガビツトのダ
イナミックＲＡＭを格成する例えばシリコンチップのよ
うな半導体チップ１が樹脂２により封止されている。符
号Ｌ□〜Ｌｒｉはリードでありて、これらのリードＬ１
〜ＬＩｍと前記半導体テップ１に設けられたボンディン
グパッドＰ８〜ｐＨとがワイヤーＷによりそれぞれボン
ディングされている。これらのリードＬ１〜ＬＩＩは、
笛６図に示すタブレスリードフレームＬＦｔ−用いて形
成されたものである。また、符号３は、例えば前記半導
体チップｌよりもわずかに大きく、かつその中央部に開
口３１が設けられている有機絶縁性被膜例えばポリイ（
ド樹脂板であって、このポリイミド樹脂板３Ｆｉ、例え
ばポリイぐド系樹脂から成る接着剤層４により前記リー
ドＬ８〜Ｌｌｌに接う−されている（第２図及び第３図
）、そして、前記半導体チップ１の素子が形成されてい
る側の光面に設けられた無機絶縁膜のバッジベージ璽ン
膜５とこのポリイミド樹脂板３とが上述と同様の接着剤
層４により接着されている。As shown in Figures 1 to 4, in the resin-sealed DIP package according to the present embodiment, a semiconductor chip 1 such as a silicon chip, which stores a 4 megabit dynamic RAM, is sealed with a resin 2. has been done. Symbols L□ to Lri are leads, and these leads L1
~LIm and bonding pads P8~pH provided on the semiconductor chip 1 are bonded by wires W, respectively. These leads L1 to LII are
The whistle is formed using the tableless lead frame LFt shown in FIG. Further, reference numeral 3 denotes an organic insulating film, such as a poly(
This polyimide resin plate 3Fi is in contact with the leads L8 to Lll by an adhesive layer 4 made of, for example, a polyimide resin (FIGS. 2 and 3), and The polyimide resin plate 3 is bonded to the badge film 5, which is an inorganic insulating film provided on the optical surface of the semiconductor chip 1 on the side where the elements are formed, by the same adhesive layer 4 as described above.

第５図に示すようは、前記半導体チップ１においては、
その中心部に周辺回路領域６が設けられ、この周辺回路
領域６の長辺に活って前記ボンディングパッドＰ、〜Ｐ
ｓａが集中的にｆ９ケられている。As shown in FIG. 5, in the semiconductor chip 1,
A peripheral circuit area 6 is provided in the center thereof, and the bonding pads P, ~P are formed on the long sides of this peripheral circuit area 6.
sa is focused on f9.

また、符号Ｍ−ＡＲＹは、メモリセルアレイである。Further, the symbol M-ARY is a memory cell array.

第１図及び第４図に示すようは、前記リードＬ。As shown in FIGS. 1 and 4, the lead L.

〜Ｌ、ｉは、その先端が前記ボンディングパッドＰ。~L,i has the tip thereof the bonding pad P.

〜Ｐ□に隣接するように股ゆられている。これによって
、既述の従来のタブレスリードフレームを用いたパッケ
ージの場合のように半導体チップからのリードのはみ出
しをなくすことができるので、その分だけパッケージの
サイズの縮小を図ることができる。このため、半導体デ
ツプ１のデツプサイズが１メガビツトのダイナミックＲ
ＡＭの場合に比べて大きくなっても、この１メガビツト
のダイナミックＲＡＭと同等のサイズのパッケージを用
いることが可能となる。また、上述のようは、。The legs are swayed so that they are adjacent to ~P□. As a result, it is possible to eliminate the protrusion of the leads from the semiconductor chip as in the case of the package using the conventional tableless lead frame described above, so that the size of the package can be reduced by that amount. Therefore, the depth size of semiconductor depth 1 is 1 megabit dynamic R.
Even if it is larger than in the case of AM, it is possible to use a package of the same size as this 1 megabit dynamic RAM. Also, as mentioned above.

ボンディングパッドＰ１〜Ｐ１．が半導体チップ１の中
央部に設けられているため、樹脂モールド後に常温にも
どる際に半導体テップｌと樹脂２との界面に生じる応力
はこれらのボンディングパッドＰｌ−Ｐ１．の近傍では
小さい、従って、この応力により、ワイヤーＷとボンデ
ィングパッドＰ、〜ＰＩやリードＬ１〜Ｌ１８とのボン
ディング部で破断が生じるのを効果的に防止することが
できる。Bonding pads P1 to P1. are provided in the center of the semiconductor chip 1, so that the stress generated at the interface between the semiconductor chip 1 and the resin 2 when the temperature returns to room temperature after resin molding is transferred to these bonding pads Pl-P1. Therefore, this stress can effectively prevent breakage at the bonding portions between the wire W and the bonding pads P, -PI, and the leads L1 to L18.

さらは、半導体チップ１の中心部に周辺回路６が設けら
れているため、半導体チップの短辺側の両端部に周辺回
路が設けられている既述の従来技術に比べて、この半導
体チップ１の長辺方向に溢って延びる配線の長さを短く
することができる。これによって、ＲＣ遅延による信号
の遅延を防止することかでどろので、メモリセルへのア
クセスの高速化を図ることがで鎗る。Furthermore, since the peripheral circuit 6 is provided in the center of the semiconductor chip 1, this semiconductor chip 1 is It is possible to shorten the length of the wiring that extends in the long side direction. This prevents signal delays due to RC delays, thereby making it possible to speed up access to memory cells.

なお、第１図及び第６図に示すようは、前記リードＬ１
＝ＬＩ＠には、樹脂２と外部空間との境界の部分に開口
Ｌａがそれぞれ設けられている。これによりて、樹脂２
と外部空間との境界部におけるこの樹脂２とリードＬ１
〜Ｌ　１１との界面の面積が小さくなるので、この樹脂
２の厚さが小さ（ても、樹脂モールド後に常温にもどる
際に前記界面に生じる応力によりこの樹脂２にクラック
等が生じるのを防止することができる。Note that as shown in FIGS. 1 and 6, the lead L1
=LI@ is provided with an opening La at the boundary between the resin 2 and the external space. As a result, resin 2
This resin 2 and lead L1 at the boundary between
Since the area of the interface with ~L 11 is small, the thickness of this resin 2 is small (even if the thickness of this resin 2 is small, cracks etc. are prevented from occurring in this resin 2 due to the stress generated at the interface when returning to room temperature after resin molding. can do.

次は、上述のように構成された本実施例による樹脂封止
ＤＩＰパッケージの製造方法の一例について説明する。Next, an example of a method for manufacturing the resin-sealed DIP package according to this embodiment configured as described above will be described.

第７図に示すようは、まずタブレスリード７し一五ＬＦ
にポリイミド樹脂板３を接着剤４により接着する。As shown in Figure 7, first, Tables Lead 7 and 15 LF
A polyimide resin plate 3 is bonded to the surface using an adhesive 4.

次に第８図に示すようは、半導体テップｌの表面のパッ
ジページ璽ン膜５と前記ポリイミド樹脂板３とを接着剤
４により接着する。Next, as shown in FIG. 8, the pad page seal film 5 on the surface of the semiconductor chip 1 and the polyimide resin plate 3 are bonded together with an adhesive 4. As shown in FIG.

次に第９図に示すようは、半導体チップｌのボンディン
グパッド（図示せず）とタブレスリードフレームＬＦと
をワイヤーＷによりボンディングする。Next, as shown in FIG. 9, bonding pads (not shown) of the semiconductor chip I and the tableless lead frame LF are bonded using wires W.

次は、樹脂モールドを行うことにより前記半導体チップ
１．ワイヤー・Ｗ等を封止した後、前記リードフレーム
ＬＦの切断成形を行って、第１図に示すよ５に目的とす
る樹脂封止ＤＩＰパッケージを完成させる。ここでモー
ルド樹脂としては、球状の石英フィン−を７５Ｖｏ１％
配合した線膨張係数が、１．０Ｘ１０　７℃の７エノー
ル樹脂硬化型クレゾールノボラツクエポキシ樹脂（エラ
ストマー分散系、日立化成■製）を用いた。Next, by performing resin molding, the semiconductor chip 1. After sealing the wires, W, etc., the lead frame LF is cut and molded to complete the desired resin-sealed DIP package 5 as shown in FIG. Here, as the mold resin, spherical quartz fins are used at 75Vo1%.
A 7-enol resin-curing cresol novolak epoxy resin (elastomer dispersion system, manufactured by Hitachi Chemical Co., Ltd.) having a linear expansion coefficient of 1.0×10 7° C. was used.

また、前記ポリイミド樹脂板３は、線膨張係数がＬ　２
　Ｘ　１０−’／”Ｃで厚さ２５μｍのボリビフエニル
系イ建ドフイルム（宇部興Ｂ■練、商品名工−ビレック
スＳ）を使用することも可能である。Further, the polyimide resin plate 3 has a linear expansion coefficient of L 2
It is also possible to use a volibiphenyl-based di-densified film (trade name: Virex S, manufactured by Ube Koki B-ren) and has a thickness of 25 μm and a thickness of 25 μm.

この場合、半導体テップとイ建ドフイルムとの接着には
、弾性率５０ｋｇｆ／ｌｊｏシリコーン樹脂系接着剤（
東しシリコーンＨ＆りを用いた。さらに半導体チップと
す〒ドとの接着には、液状熱硬化性エポキシ樹脂（油化
シェル■製、商品名エビ、−）８０７／ｚビ＋、７す２
弾性＄３５０ｋＪｆ／−）を用いた。In this case, a silicone resin adhesive with an elastic modulus of 50 kgf/ljo (
Eastishi silicone H&R was used. Furthermore, liquid thermosetting epoxy resin (manufactured by Yuka Shell ■, trade name Ebi, -) 807/z Bi+, 7S2 is used to bond the semiconductor chip to the board.
Elasticity $350kJf/-) was used.

さらは、バッタページ謬ン膜５を形成し終えた半導体デ
ツプ上にポリイミド樹脂（日立化成■製。Furthermore, polyimide resin (manufactured by Hitachi Chemical) is applied to the semiconductor layer on which the grasshopper film 5 has been formed.

登録商ｍＰ　Ｉ　Ｑ　）を形成し、その上に前述の液状
熱硬化性エポキシ樹脂を接着剤として形成し、半導体チ
ップとリードを接着した構造としてもよい。It is also possible to form a structure in which a semiconductor chip (registered trademark mPIQ) is formed, and the above-mentioned liquid thermosetting epoxy resin is formed thereon as an adhesive to bond the semiconductor chip and the leads.

上述の二つの例では、半導体ウェハ状態でイ建ドフイル
ム又はポリイミド樹脂を形成し、ヒドラジンのエツチン
グ液で、スフ２イブエリア゛及びチップ中央部のボンデ
ィングパッド部をエツチングし、その後ダイシングして
半導体チップを準備し、それをリードに接着すると、リ
ードとの位置合わせが容ＡＫ行５ことができる。In the above two examples, a semiconductor film or polyimide resin is formed in the semiconductor wafer state, and a hydrazine etching solution is used to etch the surface area and the bonding pad in the center of the chip, and then the semiconductor chip is diced. After preparing and gluing it to the lead, the alignment with the lead can be made as shown in Figure 5.

以上、本発明を実施例にもとづき具体的に説明したが、
本発明は、前記実施例に限定されるものではなく、その
簀旨を逸脱しない範囲において植々変更可能であること
は言５までもない。The present invention has been specifically explained above based on examples, but
It goes without saying that the present invention is not limited to the embodiments described above, and can be modified in various ways without departing from the spirit thereof.

例えば、半導体チップ１内の周辺回路６及びボンディン
グパッドＰ、〜Ｐ、の配ｆは上述の実旅例に限定される
ものではない０例えば、第１Ｏ図に示すようは、半導体
チップｌの中心部に２つの周辺回路６ａ、６ｂを互いた
対向させて設け、これらの周辺回路６ｍ、６ｂの間にボ
ンディングパッドＰ１〜Ｐｊ＆を設けたり、＠１１図に
示すようは、半導体チップ１の中心部に周辺回路６を設
け、この周辺回路６の長辺及び短辺に沿りてボンディン
グパッドｐｓ−ｐｔａを設けてもよい、さらにｒｔｇｔ
ｚに示すようは、半導体チップ中心部に一列にボンディ
ングパッドＰ１〜ｐｔａを設けてもよ〜１゜ また、本発明は、ＤＩＰパッケージ以外の各種＋２）／
＜ッケージに適用することができる。さらは、本発明は
、半導体チップ１がダイチオツクＲＡＭ以外のＭＯ８Ｌ
ＳＩを構成する場合に適用することができることは勿論
、例えばバイポーラＬＳＩに適用することもできる。For example, the arrangement f of the peripheral circuit 6 and bonding pads P, ~P, in the semiconductor chip 1 is not limited to the above-mentioned actual example.For example, as shown in FIG. Two peripheral circuits 6a and 6b are provided facing each other in the central part of the semiconductor chip 1, and bonding pads P1 to Pj& are provided between these peripheral circuits 6m and 6b. A peripheral circuit 6 may be provided in the peripheral circuit 6, and bonding pads ps-pta may be provided along the long and short sides of the peripheral circuit 6.
As shown in z, bonding pads P1 to pta may be provided in a row at the center of the semiconductor chip.
<Can be applied to packages. Furthermore, in the present invention, the semiconductor chip 1 is a MO8L other than a Daichioku RAM.
It goes without saying that the present invention can be applied to configuring an SI, but can also be applied to, for example, a bipolar LSI.

〔発明の効果〕〔Effect of the invention〕

本願において開示される発明のうち代表的なものにより
て得られる効果を簡単に説明すれば、下記のとおりであ
る。A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows.

すなわち、半導体装置のサイズの縮小を図ることができ
る。また、樹脂による応力によりボンディングパッドと
ワイヤーとのボンディング部で破断が生じるのを防止す
ることができる。さらは、配線が長いこと（よる信号の
遅延を防止することができる。That is, the size of the semiconductor device can be reduced. Furthermore, it is possible to prevent breakage at the bonding portion between the bonding pad and the wire due to stress caused by the resin. Furthermore, signal delays caused by long wiring can be prevented.

さらは、半導体チップとリードとの間に有機絶縁膜が存
在する為、リード側へのワイヤボンディング時に１半導
体チップのパッジページ藁ン膜にクラックが発生するの
を防止できる。Furthermore, since the organic insulating film is present between the semiconductor chip and the leads, it is possible to prevent cracks from occurring in the pad page straw film of one semiconductor chip during wire bonding to the leads.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は、本発明の−実り例による衝脂封止ＤＩＰパッ
ケージの全体構成を示す斜視図であり、！２図及び第３
図は、それぞれ第１図のＡ、　−Ａ線及びＢ−８組に溢
りての断面図であり、第４図は、第１図に示す樹脂封止
ＤＩＰパッケージの要部を示す斜視図であり、第５図は
、第１図に示す樹脂封止ＤＩＰパッケージ中の半導体チ
ップを示す平面図、 第６図は、第１図に示す樹脂封止ＤＩＰパッケージの製
造に用いるタブレスリードフレームを示す平面図、 第７図〜第９図は、第１図に示す樹脂封止ＤＩＰパッケ
ージの製造方法の一例を工程順に説明するための断面図
、 第１０図、第１１図及び＠１２図は、本発明の変形例を
示す平面図である。 図中、１−・半導体チップ、２・・・樹脂、３・・・ポ
リイミド樹脂板、４・・・接着剤、５・・・パッジベー
ジ璽ン膜、６・・・周辺回路、Ｌｉ〜Ｌｌｉ””リード
、Ｐ。 〜Ｐ１．・・・ボンディングパッド、ＬＦ・・・タブレ
スリードフレームである。 噴 味FIG. 1 is a perspective view showing the overall structure of a grease-sealed DIP package according to a practical example of the present invention. Figure 2 and 3
The figures are cross-sectional views overflowing to lines A, -A and B-8 in Fig. 1, respectively, and Fig. 4 is a perspective view showing the main parts of the resin-sealed DIP package shown in Fig. 1. 5 is a plan view showing a semiconductor chip in the resin-sealed DIP package shown in FIG. 1, and FIG. 6 is a tableless lead frame used for manufacturing the resin-sealed DIP package shown in FIG. 1. FIGS. 7 to 9 are cross-sectional views for explaining step-by-step an example of the method for manufacturing the resin-sealed DIP package shown in FIG. 1, FIGS. 10, 11, and 12 FIG. 2 is a plan view showing a modification of the present invention. In the figure, 1--Semiconductor chip, 2--Resin, 3--Polyimide resin plate, 4--Adhesive, 5--Padge base film, 6--Peripheral circuit, Li~Lli'' ”Reed, P. ~P1. . . . bonding pad, LF . . . tableless lead frame. spout taste

Claims (1)

【特許請求の範囲】 １、（ａ）中央部に複数のボンディングパッドを有する
長方形の半導体チップ； （ｂ）前記半導体チップ表面を被い、前記複数のボンデ
ィングパッド部に開口を有する有機絶縁性被膜； （ｃ）前記絶縁性被膜上の接着剤層； （ｄ）前記半導体チップ表面の絶縁性被膜上に前記接着
剤層を介して接着された複数のリード；（ｅ）前記複数
のボンディングパッドと前記複数のリードとを電気的に
接続する複数のワイヤ；（ｆ）前記半導体チップ及び前
記複数のリードの一部分を封止した樹脂。 とからなる半導体装置。 ２、前記ボンディングパッドは、前記半導体チップの長
辺方向に一列に配置されていることを特徴とする特許請
求の範囲第１項記載の半導体装置。 ３、前記半導体チップは、メモリセルアレイ領域と周辺
回路領域とを有し、周辺回路領域は前記半導体チップの
中央に位置することを特徴とする特許請求の範囲第１項
記載の半導体装置。 ４、前記ボンディングパッドは、周辺回路領域の周辺に
配置されていることを特徴とする特許請求の範囲第３項
記載の半導体装置。 ５、前記周辺回路領域は、二つのブロックからなり、前
記ボンディングパッドは、二つのブロックの間に配置さ
れていることを特徴とする特許請求の範囲第３項記載の
半導体装置。 ６、前記有機絶縁性被膜はポリイミド膜であることを特
徴とする特許請求の範囲第１項記載の半導体装置。 ７、前記有機絶縁性被膜は、ポリピフェニル系樹脂膜で
あることを特徴とする特許請求の範囲第１項記載の半導
体装置。 ８、（ａ）中央部に複数のボンディングパッドを有し、
ボンディングパッド部以外の部分を無機の絶縁膜で被わ
れた長方形の半導体チップ； （ｂ）前記半導体チップ上に位置し、前記複数のボンデ
ィングパッド部に開口を有する有機絶縁性被膜； （ｃ）前記有機絶縁性被膜上に位置する複数のリード； （ｄ）前記半導体チップと前記有機絶縁性被膜とを接着
する第１の接着剤層； （ｅ）前記有機絶縁性被膜と前記複数のリードとを接着
する第２の接着剤層； （ｆ）前記複数のリードと前記ボンディングパッドを電
気的に接続する複数のワイヤ； （ｇ）前記半導体チップ及び前記複数のリードの一部分
を封止した樹脂。 とからなる半導体装置。[Claims] 1. (a) a rectangular semiconductor chip having a plurality of bonding pads in the center; (b) an organic insulating film covering the surface of the semiconductor chip and having openings in the plurality of bonding pads; (c) an adhesive layer on the insulating film; (d) a plurality of leads bonded to the insulating film on the surface of the semiconductor chip via the adhesive layer; (e) a plurality of bonding pads; a plurality of wires electrically connecting the plurality of leads; (f) a resin sealing a portion of the semiconductor chip and the plurality of leads; A semiconductor device consisting of. 2. The semiconductor device according to claim 1, wherein the bonding pads are arranged in a line in the long side direction of the semiconductor chip. 3. The semiconductor device according to claim 1, wherein the semiconductor chip has a memory cell array area and a peripheral circuit area, and the peripheral circuit area is located at the center of the semiconductor chip. 4. The semiconductor device according to claim 3, wherein the bonding pad is arranged around a peripheral circuit area. 5. The semiconductor device according to claim 3, wherein the peripheral circuit area consists of two blocks, and the bonding pad is arranged between the two blocks. 6. The semiconductor device according to claim 1, wherein the organic insulating film is a polyimide film. 7. The semiconductor device according to claim 1, wherein the organic insulating film is a polypyphenyl resin film. 8. (a) Having a plurality of bonding pads in the center,
a rectangular semiconductor chip whose portion other than the bonding pad portion is covered with an inorganic insulating film; (b) an organic insulating film located on the semiconductor chip and having openings in the plurality of bonding pad portions; (c) the aforementioned a plurality of leads located on the organic insulating film; (d) a first adhesive layer for bonding the semiconductor chip and the organic insulating film; (e) a first adhesive layer for bonding the organic insulating film and the plurality of leads; a second adhesive layer to be bonded; (f) a plurality of wires electrically connecting the plurality of leads and the bonding pad; (g) a resin sealing a portion of the semiconductor chip and the plurality of leads; A semiconductor device consisting of.
JP63199857A 1988-08-12 1988-08-12 Semiconductor storage device Expired - Lifetime JP2585738B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP63199857A JP2585738B2 (en) 1988-08-12 1988-08-12 Semiconductor storage device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63199857A JP2585738B2 (en) 1988-08-12 1988-08-12 Semiconductor storage device

Publications (2)

Publication Number Publication Date
JPH0250438A true JPH0250438A (en) 1990-02-20
JP2585738B2 JP2585738B2 (en) 1997-02-26

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ID=16414807

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04164353A (en) * 1990-10-29 1992-06-10 Nec Corp Resin-sealed semiconductor device
EP2371910A1 (en) 2010-03-30 2011-10-05 Fujifilm Corporation Ink composition, inkjet recording method and process for producing molded printed material
JP2012094909A (en) * 2012-02-01 2012-05-17 Rohm Co Ltd Semiconductor integrated circuit device

Citations (4)

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