JP2012094909A - Semiconductor integrated circuit device - Google Patents

Semiconductor integrated circuit device Download PDF

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JP2012094909A
JP2012094909A JP2012019603A JP2012019603A JP2012094909A JP 2012094909 A JP2012094909 A JP 2012094909A JP 2012019603 A JP2012019603 A JP 2012019603A JP 2012019603 A JP2012019603 A JP 2012019603A JP 2012094909 A JP2012094909 A JP 2012094909A
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circuit block
external connection
circuit
electrodes
input
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JP5442047B2 (en
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Kunihiro Komiya
邦裕 小宮
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Rohm Co Ltd
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    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
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    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
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    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
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    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H01L2224/49113—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting different bonding areas on the semiconductor or solid-state body to a common bonding area outside the body, e.g. converging wires
    • H—ELECTRICITY
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    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
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    • H01L2924/3011—Impedance

Abstract

PROBLEM TO BE SOLVED: To shorten input wiring of an input circuit block and output wiring of an output circuit block.SOLUTION: In a semiconductor integrated circuit device 30, a plurality of electrodes P2 and P3 for external connection for an input circuit block 32 are disposed between the input circuit block 32 and an output circuit block 33, and a plurality of electrodes P1 and P4 for external connection for the output circuit block 33 are disposed between the output circuit block 33 and lead electrodes 34 and 35. The lead electrode 34 connected to the electrodes P1 and P2 for external connection through thin metallic wires Wb1 and Wb2 and the lead electrode 35 connected to the electrodes P3 and P4 for external connection through thin metallic wires Wb3 and Wb4 are disposed in a plurality of numbers in the direction parallel to the direction in which the input circuit block 32, the electrodes P2 and P3 for external connection, the output circuit block 33, the electrodes P1 and P4 for external connection, and the lead electrodes 34 and 35 are disposed in this order.

Description

本発明は、入力信号と出力信号とが同一の外部端子により入出力される半導体集積回路装置（ＩＣ）に関する。   The present invention relates to a semiconductor integrated circuit device (IC) in which an input signal and an output signal are input / output through the same external terminal.

入力信号回路と出力信号回路が設けられ、それら両回路の入出力信号が同一の外部接続端子により入出力されるように構成されたＩＣが、例えば磁気ディスク装置の読出／書込用等に使用されている。   An input signal circuit and an output signal circuit are provided, and an IC configured such that input / output signals of both circuits are input / output through the same external connection terminal is used, for example, for reading / writing of a magnetic disk device Has been.

図４は、従来の、同一ヘッドで読出／書込を行う機能を持った磁気ディスク装置用のＩＣの構成を示す図であり、図５はその回路を例示する図である。   FIG. 4 is a diagram showing a configuration of a conventional IC for a magnetic disk device having a function of reading / writing with the same head, and FIG. 5 is a diagram illustrating the circuit thereof.

図４において、ＩＣ４０のＩＣチップ４１には、読出回路４２と書込回路４３が配置され、また外部接続用のボンディングパッドＰ１，Ｐ２がその周辺部に配置されている。そして、読出回路４２とボンディングパッドＰ１，Ｐ２との間が読出用配線Ｗｒ１，Ｗｒ２で接続され、書込回路４３とボンディングパッドＰ１，Ｐ２との間が書込用配線Ｗｗ１，Ｗｗ２で接続されている。   In FIG. 4, a read circuit 42 and a write circuit 43 are arranged on an IC chip 41 of an IC 40, and bonding pads P1 and P2 for external connection are arranged on the periphery thereof. The read circuit 42 and bonding pads P1 and P2 are connected by read wirings Wr1 and Wr2, and the write circuit 43 and bonding pads P1 and P2 are connected by write wirings Ww1 and Ww2. Yes.

このＩＣチップ４１のボンディングパッドＰ１，Ｐ２とリード電極４４，４５とが金属細線（ワイヤ）Ｗｂ１，Ｗｂ２によりワイヤボンディング接続され、さらにモールド等が施されてＩＣ４０が形成されている。   Bonding pads P1 and P2 of the IC chip 41 and lead electrodes 44 and 45 are wire-bonded and connected by metal thin wires (wires) Wb1 and Wb2, and further molded, etc., to form an IC 40.

ＩＣチップ４１の外部接続用端子であるボンディングパッドＰ１，Ｐ２はリード電極４４，４５を介して、図５に示されるように、磁気ディスク装置の磁気ヘッド５０と接続され、書込回路４３からの書込信号が磁気ヘッド５０によりデータが磁気ディスクに書き込まれ、また磁気ヘッド５０により、磁気ディスクに書き込まれているデータが読み出され読出回路４２でデータの増幅を行うようになっている。なお、読出回路４２は微弱な読出信号を判別するためにトランジスタ差動増幅回路で構成され、また書込回路はトランジスタ化されたＨブリッジ回路で構成されるが、これら回路の構成自体は周知のものであるので、説明は省略する。   Bonding pads P1 and P2 which are external connection terminals of the IC chip 41 are connected to the magnetic head 50 of the magnetic disk device via the lead electrodes 44 and 45 as shown in FIG. The write signal is written to the magnetic disk by the magnetic head 50, and the data written to the magnetic disk is read by the magnetic head 50, and the read circuit 42 amplifies the data. The read circuit 42 is composed of a transistor differential amplifier circuit to discriminate a weak read signal, and the write circuit is composed of a transistorized H bridge circuit. The structure of these circuits is well known. Since it is a thing, description is abbreviate | omitted.

従来のＩＣチップ４１では、読出回路４２と書込回路４３が、周辺に配置された同じボンディングパッドＰ１，Ｐ２に接続されているから、ＩＣチップ内の接続配線が長くなってしまう。図４の例のように、書込回路４３をボンディングパッドＰ１，Ｐ２に近づけて配置すると、読出回路４２は離れて配置されることになるから、その読出用配線Ｗｒ１，Ｗｒ２は、長くなってしまう。この長さは、回路の大きさにもよるが、通常、数１００μｍの長さになる。   In the conventional IC chip 41, since the read circuit 42 and the write circuit 43 are connected to the same bonding pads P1 and P2 arranged in the periphery, the connection wiring in the IC chip becomes long. When the write circuit 43 is arranged close to the bonding pads P1 and P2 as in the example of FIG. 4, the read circuit 42 is arranged apart from each other, so that the read wirings Wr1 and Wr2 become long. End up. This length depends on the size of the circuit, but is usually several hundreds of μm.

この長くなった読出用配線Ｗｒ１，Ｗｒ２により、寄生インダクタンス、寄生静電容量、寄生抵抗が大きくなる。図５に示されるように、これら寄生素子成分による等価回路４７，４８が読出用配線Ｗｒ１，Ｗｒ２に挿入されることになり、これら寄生素子成分による影響を避けられない。例えば、寄生素子成分による等価回路４７，４８が挿入されることにより、予定していない周波数特性の回路が付加されるから、読出回路４２の本来の動作に影響を受けるし、また、電圧降下が発生するから読出データの判定レベルに誤差が発生する。さらに、近接する他回路からの干渉（ノイズ）などの影響を受けることがある。   Due to the long read wirings Wr1 and Wr2, parasitic inductance, parasitic capacitance, and parasitic resistance increase. As shown in FIG. 5, equivalent circuits 47 and 48 based on these parasitic element components are inserted into the read wirings Wr1 and Wr2, and the influence of these parasitic element components cannot be avoided. For example, by inserting equivalent circuits 47 and 48 by parasitic element components, a circuit having an unscheduled frequency characteristic is added, so that the original operation of the read circuit 42 is affected, and the voltage drop is reduced. As a result, an error occurs in the determination level of the read data. Furthermore, it may be affected by interference (noise) from other adjacent circuits.

また、読出回路４２と書込回路４３との配置を逆にしたとしても、今度は書込回路４３の書込動作に、寄生素子成分による影響を受けることになってしまう。   Even if the arrangement of the read circuit 42 and the write circuit 43 is reversed, the write operation of the write circuit 43 is now affected by parasitic element components.

そこで、本発明は、入力回路ブロックと、出力回路ブロックと、これら両ブロックの入力配線及び出力配線が接続される外部接続用電極を有し、それらのレイアウトを工夫して、入力配線及び出力配線の長さを短くしたＩＣを提供することを目的とする。   Therefore, the present invention has an input circuit block, an output circuit block, and an external connection electrode to which the input wiring and output wiring of both blocks are connected. An object of the present invention is to provide an IC with a reduced length.

上記の目的を達成するために、本発明に係る半導体集積回路装置は、入力回路ブロックと、出力回路ブロックと、前記入力回路ブロックの入力配線が接続される第１の外部接続用電極と、前記出力回路ブロックの出力配線が接続される第２の外部接続用電極と、前記第１及び第２の外部接続用電極がそれぞれ金属細線を介して電気的に接続されるリード電極と、を有する半導体集積回路装置において、前記第１の外部接続用電極は、前記入力回路ブロックと前記出力回路ブロックとの間に複数配置されており、前記第２の外部接続用電極は、前記出力回路ブロックと前記リード電極との間に複数配置されており、前記リード電極は、前記入力回路ブロック、前記第１の外部接続用電極、前記出力回路ブロック、前記第２の外部接続用電極、前記リード電極の順に配置された方向と平行する方向に複数配置されている構成（第１の構成）とされている。   In order to achieve the above object, a semiconductor integrated circuit device according to the present invention includes an input circuit block, an output circuit block, a first external connection electrode to which an input wiring of the input circuit block is connected, A semiconductor having a second external connection electrode to which an output wiring of an output circuit block is connected, and a lead electrode to which the first and second external connection electrodes are electrically connected through a thin metal wire, respectively. In the integrated circuit device, a plurality of the first external connection electrodes are arranged between the input circuit block and the output circuit block, and the second external connection electrodes are connected to the output circuit block and the output circuit block. A plurality of lead electrodes are disposed between the input circuit block, the first external connection electrode, the output circuit block, the second external connection electrode, and the front electrode. It is configured arranged in plural and in a direction parallel to the arranged direction in the order of the lead electrode (first configuration).

なお、上記第１の構成から成る半導体集積回路装置において、前記第１及び第２の外部接続用電極は、前記入力回路ブロック、前記第１の外部接続用電極、前記出力回路ブロック、前記第２の外部接続用電極、前記リード電極の順に配置された方向と直交する方向において、互いの位置をずらして配置されている構成（第２の構成）にするとよい。   In the semiconductor integrated circuit device having the first configuration, the first and second external connection electrodes include the input circuit block, the first external connection electrode, the output circuit block, and the second circuit. The external connection electrode and the lead electrode may be arranged in a direction orthogonal to the direction in which the lead electrodes are arranged in this order (second configuration).

また、上記第２の構成から成る半導体集積回路装置において、前記金属細線の太さは、前記入力配線及び前記出力配線の太さに比して大きい構成（第３の構成）にするとよい。   In the semiconductor integrated circuit device having the second configuration, the thickness of the thin metal wire may be larger than the thickness of the input wiring and the output wiring (third configuration).

本発明によれば、入力回路ブロックの入力配線及び出力回路ブロックの出力配線はともに短くなり、配線の寄生素子成分による影響を小さくすることができる。   According to the present invention, both the input wiring of the input circuit block and the output wiring of the output circuit block are shortened, and the influence of the parasitic element component of the wiring can be reduced.

本発明の第１の実施の形態に係るＩＣの構成図。The block diagram of IC which concerns on the 1st Embodiment of this invention. 本発明の第２の実施の形態に係るＩＣの構成図。The block diagram of IC which concerns on the 2nd Embodiment of this invention. 本発明の第３の実施の形態に係るＩＣの構成図。The block diagram of IC which concerns on the 3rd Embodiment of this invention. 従来のＩＣの構成図。The block diagram of conventional IC. 従来のＩＣの回路を例示する図。The figure which illustrates the circuit of the conventional IC.

以下、本発明のＩＣを、同一ヘッドで読出／書込を行う磁気ディスク装置用の読出／書込機能を持ったＩＣに適用した場合の各実施の形態について、図を参照して説明する。   Hereinafter, each embodiment when the IC of the present invention is applied to an IC having a read / write function for a magnetic disk device that performs read / write with the same head will be described with reference to the drawings.

図１は、本発明の第１の実施の形態に係るＩＣの構成を示す図である。この図において、ＩＣチップ１１には、入力回路ブロックである読出回路ブロック（以下、読出回路）１２と、出力回路ブロックである書込回路ブロック（以下、書込回路）１３とが、互いに対向するように配置される。   FIG. 1 is a diagram showing a configuration of an IC according to the first embodiment of the present invention. In this figure, a read circuit block (hereinafter referred to as a read circuit) 12 as an input circuit block and a write circuit block (hereinafter referred to as a write circuit) 13 as an output circuit block are opposed to each other on the IC chip 11. Are arranged as follows.

読出回路１２と書込回路１３との間に挟まれるように、共通の外部接続用電極であるボンディングパッドＰ１，Ｐ２が配置される。   Bonding pads P1 and P2 that are common external connection electrodes are arranged so as to be sandwiched between the read circuit 12 and the write circuit 13.

読出回路１２とボンディングパッドＰ１，Ｐ２とは、読出用配線Ｗｒ１，Ｗｒ２で接続され、また、書込回路１３とボンディングパッドＰ１，Ｐ２とは、書込用配線Ｗｗ１，Ｗｗ２で接続される。   Read circuit 12 and bonding pads P1, P2 are connected by read wirings Wr1, Wr2, and write circuit 13 and bonding pads P1, P2 are connected by write wirings Ww1, Ww2.

リード電極１４，１５は、ボンディングパッドＰ１，Ｐ２に対して書込回路１３（或いは読出回路１２）の反対側に配置される。即ち、読出回路１２、ボンディングパッドＰ１，Ｐ２、書込回路１３、リード電極１４，１５の順に配置される。   The lead electrodes 14 and 15 are disposed on the opposite side of the write circuit 13 (or the read circuit 12) with respect to the bonding pads P1 and P2. That is, the reading circuit 12, the bonding pads P1 and P2, the writing circuit 13, and the lead electrodes 14 and 15 are arranged in this order.

そして、ボンディングパッドＰ１，Ｐ２は、金属細線Ｗｂ１，Ｗｂ２を介してリード電極１４，１５に接続され、さらにモールド等が施されてＩＣ１０が形成されている。   The bonding pads P1 and P2 are connected to the lead electrodes 14 and 15 through the fine metal wires Wb1 and Wb2, and are further molded to form the IC 10.

このように、読出回路１２と書込回路１３との間に挟まれるように、共通のボンディングパッドＰ１，Ｐ２が配置されるから、読出回路１２の読出用配線Ｗｒ１，Ｗｒ２の長さｄ１及び書込回路１３の書込用配線Ｗｗ１，Ｗｗ２の長さｄ２はともに短くなる。この長さｄ１，ｄ２は、ボンディングパッドＰ１，Ｐ２のレイアウトルールにもよるが、５０μｍ程度まで短縮することができるから、従来のもの（図４）に比べて、格段に短くなる。   Thus, since the common bonding pads P1 and P2 are disposed so as to be sandwiched between the read circuit 12 and the write circuit 13, the length d1 of the read wirings Wr1 and Wr2 of the read circuit 12 and the write The lengths d2 of the write wirings Ww1 and Ww2 of the insertion circuit 13 are both shortened. Although the lengths d1 and d2 depend on the layout rules of the bonding pads P1 and P2, the lengths d1 and d2 can be shortened to about 50 μm, so that they are much shorter than the conventional one (FIG. 4).

なお、金属細線Ｗｂ１，Ｗｂ２の長さは、従来のもの（図４）に比べて長くなる。しかし、この金属細線Ｗｂ１，Ｗｂ２の太さ（断面積）は、ＩＣ内の内部配線である読出用配線Ｗｒ１，Ｗｒ２、書込用配線Ｗｗ１，Ｗｗ２の太さ（断面積）に比して大きいし、さらに金属細線Ｗｂ１，Ｗｂ２の材質が通常金（Ａｕ）であり、材質がアルミ（Ａｌ）である内部配線に比して、インピーダンスが低いから、金属細線Ｗｂ１，Ｗｂ２が長くなることによる影響は極めて小さい。   Note that the lengths of the thin metal wires Wb1 and Wb2 are longer than those of the conventional one (FIG. 4). However, the thickness (cross-sectional area) of the thin metal wires Wb1 and Wb2 is larger than the thickness (cross-sectional area) of the read wirings Wr1 and Wr2 and the write wirings Ww1 and Ww2 which are internal wirings in the IC. Furthermore, the metal fine wires Wb1 and Wb2 are made of gold (Au), and the impedance is lower than that of the internal wiring made of aluminum (Al). Is extremely small.

したがって、本発明では、読出用配線Ｗｒ１，Ｗｒ２の長さｄ１及び書込用配線Ｗｗ１，Ｗｗ２の長さｄ２が短くなることに伴い、それら配線Ｗｒ１，Ｗｒ２，Ｗｗ１，Ｗｗ２の寄生素子成分が小さくなるから、その寄生素子成分による影響を小さくすることができる。また、近接する他回路からの干渉（ノイズ）などの影響も低減される。   Therefore, in the present invention, as the length d1 of the read wirings Wr1 and Wr2 and the length d2 of the write wirings Ww1 and Ww2 become shorter, the parasitic element components of the wirings Wr1, Wr2, Ww1, and Ww2 become smaller. Therefore, the influence of the parasitic element component can be reduced. Also, the influence of interference (noise) from other adjacent circuits is reduced.

なお、図１の第１の実施の形態において、読出回路１２と書込回路１３との位置関係を逆にしても、同様の効果を得ることができる。   In the first embodiment shown in FIG. 1, the same effect can be obtained even if the positional relationship between the read circuit 12 and the write circuit 13 is reversed.

図２は、本発明の第２の実施の形態に係るＩＣの構成を示す図である。この第２の実施の形態においても、ＩＣチップ２１には入力回路ブロックである読出回路２２と、出力回路ブロックである書込回路２３とが、互いに対向するように配置され、また、読出回路２２と書込回路２３との間に挟まれるように、共通の外部接続用電極であるボンディングパッドＰ１，Ｐ２が配置される。   FIG. 2 is a diagram showing a configuration of an IC according to the second embodiment of the present invention. Also in the second embodiment, a read circuit 22 that is an input circuit block and a write circuit 23 that is an output circuit block are arranged on the IC chip 21 so as to face each other. Bonding pads P1 and P2, which are common external connection electrodes, are arranged so as to be sandwiched between and the write circuit 23.

ただ、この実施の形態では、リード電極２４，２５が、読出回路２２、ボンディングパッドＰ１，Ｐ２、書込回路２３の順に配置された方向と直交する方向に配置される。このリード電極２４，２５の配置の点で、図１の第１の実施の形態と異なっている。   However, in this embodiment, the lead electrodes 24 and 25 are disposed in a direction orthogonal to the direction in which the read circuit 22, the bonding pads P1 and P2, and the write circuit 23 are disposed in this order. The arrangement of the lead electrodes 24 and 25 is different from that of the first embodiment shown in FIG.

このため、ボンディングパッドＰ１とボンディングパッドＰ２とは、一方は書込回路２３に近づき（距離ｄ１）、読出回路２２から隔たる（距離ｄ２）ように配置され、他方は読出回路２２に近づき（距離ｄ１）、書込回路２３から隔たる（距離ｄ２）ように配置され、その位置をずらして配置されている。この位置をずらせたことにより、パッドＰ１とリード電極２４とのワイヤボンディング及びパッドＰ２とリード電極２５とのワイヤボンディングが容易である。   For this reason, one of the bonding pad P1 and the bonding pad P2 is disposed so as to approach the writing circuit 23 (distance d1) and away from the reading circuit 22 (distance d2), and the other approaches the reading circuit 22 (distance). d1) is arranged so as to be separated from the writing circuit 23 (distance d2), and the positions thereof are shifted. By shifting this position, wire bonding between the pad P1 and the lead electrode 24 and wire bonding between the pad P2 and the lead electrode 25 are easy.

読出回路２２とボンディングパッドＰ１，Ｐ２とは、読出用配線Ｗｒ１，Ｗｒ２で接続され、また、書込回路２２とボンディングパッドＰ１，Ｐ２とは、書込用配線Ｗｗ１，Ｗｗ２で接続される。   Read circuit 22 and bonding pads P1, P2 are connected by read wirings Wr1, Wr2, and write circuit 22 and bonding pads P1, P2 are connected by write wirings Ww1, Ww2.

そして、ボンディングパッドＰ１，Ｐ２は、金属細線Ｗｂ１，Ｗｂ２を介してリード電極２４，２５に接続され、さらにモールド等が施されてＩＣ２０が形成されている。   The bonding pads P1 and P2 are connected to the lead electrodes 24 and 25 through the fine metal wires Wb1 and Wb2, and are further molded to form the IC 20.

この第２の実施の形態によれば、第１の実施の形態と同様の効果を得ることができるほか、各構成部の配置の自由度が得られる。   According to the second embodiment, the same effects as those of the first embodiment can be obtained, and the degree of freedom of arrangement of the respective components can be obtained.

図３は、本発明の第３の実施の形態に係るＩＣの構成を示す図である。この第３の実施の形態においても、ＩＣチップ３１には入力回路ブロックである読出回路３２と、出力回路ブロックである書込回路３３とが、互いに対向するように配置され、また、読出回路３２と書込回路３３のリード電極側に、外部接続用電極であるボンディングパッドＰ１〜Ｐ４が配置される。   FIG. 3 is a diagram showing a configuration of an IC according to the third embodiment of the present invention. Also in the third embodiment, a read circuit 32 that is an input circuit block and a write circuit 33 that is an output circuit block are arranged on the IC chip 31 so as to face each other. On the lead electrode side of the write circuit 33, bonding pads P1 to P4 which are external connection electrodes are arranged.

ただ、この実施の形態では、ボンディングパッドＰ２，Ｐ３が読出回路３２用に、また、ボンディングパッドＰ１，Ｐ４が書込回路３３用に、それぞれ専用に設けられている。このボンディングパッドＰ１〜Ｐ４の点で、図１の第１の実施の形態と異なっている。   However, in this embodiment, bonding pads P2 and P3 are provided exclusively for read circuit 32, and bonding pads P1 and P4 are provided exclusively for write circuit 33, respectively. The bonding pads P1 to P4 are different from the first embodiment shown in FIG.

読出回路３２とボンディングパッドＰ２，Ｐ３とは、読出用配線Ｗｒ１，Ｗｒ２で接続され、また、書込回路３３とボンディングパッドＰ１，Ｐ４とは、書込用配線Ｗｗ１，Ｗｗ２で接続される。   Read circuit 32 and bonding pads P2, P3 are connected by read wirings Wr1, Wr2, and write circuit 33 and bonding pads P1, P4 are connected by write wirings Ww1, Ww2.

リード電極３４，３５は、ボンディングパッドＰ１〜Ｐ４に対して書込回路３３（或いは読出回路３２）の外側に配置される。   The lead electrodes 34 and 35 are disposed outside the write circuit 33 (or the read circuit 32) with respect to the bonding pads P1 to P4.

そして、ボンディングパッドＰ１，Ｐ２は、金属細線Ｗｂ１，Ｗｂ２を介してリード電極３４に接続され、ボンディングパッドＰ３，Ｐ４は、金属細線Ｗｂ３，Ｗｂ４を介してリード電極３５に接続され、さらにモールド等が施されてＩＣ３０が形成されている。   The bonding pads P1 and P2 are connected to the lead electrode 34 via the fine metal wires Wb1 and Wb2. The bonding pads P3 and P4 are connected to the lead electrode 35 via the fine metal wires Wb3 and Wb4. As a result, an IC 30 is formed.

なお、ボンディングパッドＰ２，Ｐ３とボンディングパッドＰ１，Ｐ４とは、図のようにそれぞれ距離ｄだけずらせて配置してもよい。   The bonding pads P2 and P3 and the bonding pads P1 and P4 may be shifted by a distance d as shown in the figure.

この第３の実施の形態によれば、第１の実施の形態と同様の効果を得ることができるほか、読出回路３２，書込回路３３の配線上の自由度が得られる。   According to the third embodiment, the same effects as those of the first embodiment can be obtained, and the degree of freedom on the read circuit 32 and the write circuit 33 can be obtained.

なお、以上の各実施の形態では、ＩＣチップの外部接続電極であるボンディングパッドＰ１〜Ｐ４と外部との接続をリード電極へのワイヤボンディングにより行うこととして説明したが、これに限らず、ＩＣのボンディングパッドＰ１〜Ｐ４をフリップチップ方式やＴＡＢ方式によるワイヤレスボンディングにより、外部と接続することができる。この場合にも、各実施の形態におけると同様の効果を得ることができる。   In the above embodiments, the bonding pads P1 to P4, which are external connection electrodes of the IC chip, and the outside are described as being connected by wire bonding to the lead electrodes. The bonding pads P1 to P4 can be connected to the outside by wireless bonding using a flip chip method or a TAB method. Also in this case, the same effect as in each embodiment can be obtained.

１０、２０、３０ ＩＣ
１１、２１、３１ ＩＣチップ
１２、２２、３２ 読出回路
１３、２３、３３ 書込回路
１４、１５、２４、２５、３４、３５ リード電極
Ｐ１〜Ｐ４ ボンディングパッド
Ｗｒ１，Ｗｒ２ 読出用配線
Ｗｗ１，Ｗｗ２ 書込用配線
Ｗｂ１〜Ｗｂ４ 金属細線（ワイヤ） 10, 20, 30 IC
11, 21, 31 IC chip 12, 22, 32 Read circuit 13, 23, 33 Write circuit 14, 15, 24, 25, 34, 35 Lead electrodes P1-P4 Bonding pads Wr1, Wr2 Read wiring Ww1, Ww2 Embedded wiring Wb1 to Wb4 Fine metal wire (wire)

Claims (3)

入力回路ブロックと、
出力回路ブロックと、
前記入力回路ブロックの入力配線が接続される第１の外部接続用電極と、
前記出力回路ブロックの出力配線が接続される第２の外部接続用電極と、
前記第１及び第２の外部接続用電極がそれぞれ金属細線を介して電気的に接続されるリード電極と、
を有する半導体集積回路装置において、
前記第１の外部接続用電極は、前記入力回路ブロックと前記出力回路ブロックとの間に複数配置されており、
前記第２の外部接続用電極は、前記出力回路ブロックと前記リード電極との間に複数配置されており、
前記リード電極は、前記入力回路ブロック、前記第１の外部接続用電極、前記出力回路ブロック、前記第２の外部接続用電極、前記リード電極の順に配置された方向と平行する方向に複数配置されている、
ことを特徴とする半導体集積回路装置。 An input circuit block;
An output circuit block;
A first external connection electrode to which an input wiring of the input circuit block is connected;
A second external connection electrode to which the output wiring of the output circuit block is connected;
A lead electrode to which the first and second external connection electrodes are electrically connected via thin metal wires,
In a semiconductor integrated circuit device having
A plurality of the first external connection electrodes are arranged between the input circuit block and the output circuit block,
A plurality of the second external connection electrodes are arranged between the output circuit block and the lead electrode,
A plurality of the lead electrodes are arranged in a direction parallel to a direction in which the input circuit block, the first external connection electrode, the output circuit block, the second external connection electrode, and the lead electrode are arranged in this order. ing,
A semiconductor integrated circuit device. 前記第１及び第２の外部接続用電極は、前記入力回路ブロック、前記第１の外部接続用電極、前記出力回路ブロック、前記第２の外部接続用電極、前記リード電極の順に配置された方向と直交する方向において、互いの位置をずらして配置されていることを特徴とする請求項１に記載の半導体集積回路装置。   The first and second external connection electrodes are arranged in the order of the input circuit block, the first external connection electrode, the output circuit block, the second external connection electrode, and the lead electrode. 2. The semiconductor integrated circuit device according to claim 1, wherein the semiconductor integrated circuit devices are arranged so as to be shifted from each other in a direction perpendicular to the first direction. 前記金属細線の太さは、前記入力配線及び前記出力配線の太さに比して大きいことを特徴とする請求項２に記載の半導体集積回路装置。   3. The semiconductor integrated circuit device according to claim 2, wherein a thickness of the thin metal wire is larger than a thickness of the input wiring and the output wiring.
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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0250438A (en) * 1988-08-12 1990-02-20 Hitachi Ltd Semiconductor device
JPH02306650A (en) * 1989-05-22 1990-12-20 Seiko Epson Corp Semiconductor device
JPH04326575A (en) * 1991-04-26 1992-11-16 Nec Ic Microcomput Syst Ltd Integrated circuit device
JPH07263628A (en) * 1994-03-18 1995-10-13 Fujitsu Ltd Semiconductor device
JP2000003600A (en) * 1993-06-17 2000-01-07 Matsushita Electric Ind Co Ltd Semiconductor memory and semiconductor integrated circuit

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0250438A (en) * 1988-08-12 1990-02-20 Hitachi Ltd Semiconductor device
JPH02306650A (en) * 1989-05-22 1990-12-20 Seiko Epson Corp Semiconductor device
JPH04326575A (en) * 1991-04-26 1992-11-16 Nec Ic Microcomput Syst Ltd Integrated circuit device
JP2000003600A (en) * 1993-06-17 2000-01-07 Matsushita Electric Ind Co Ltd Semiconductor memory and semiconductor integrated circuit
JPH07263628A (en) * 1994-03-18 1995-10-13 Fujitsu Ltd Semiconductor device

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