JPS647628A - Semiconductor device and manufacture thereof - Google Patents

Semiconductor device and manufacture thereof

Info

Publication number
JPS647628A
JPS647628A JP62161333A JP16133387A JPS647628A JP S647628 A JPS647628 A JP S647628A JP 62161333 A JP62161333 A JP 62161333A JP 16133387 A JP16133387 A JP 16133387A JP S647628 A JPS647628 A JP S647628A
Authority
JP
Japan
Prior art keywords
chip
pads
leads
bonding
longitudinal direction
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP62161333A
Other languages
Japanese (ja)
Other versions
JPH0777226B2 (en
Inventor
Aizo Kaneda
Masao Mitani
Shozo Nakamura
Kunihiko Nishi
Hajime Murakami
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP62161333A priority Critical patent/JPH0777226B2/en
Priority to KR1019880007311A priority patent/KR960013778B1/en
Publication of JPS647628A publication Critical patent/JPS647628A/en
Priority to US07/640,584 priority patent/US5184208A/en
Priority to KR1019920012675A priority patent/KR970004216B1/en
Priority to US08/000,125 priority patent/US5365113A/en
Priority to US08/329,824 priority patent/US5514905A/en
Priority to US08/458,166 priority patent/US5742101A/en
Publication of JPH0777226B2 publication Critical patent/JPH0777226B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
    • H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
    • H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
    • H01L2224/02165—Reinforcing structures
    • H01L2224/02166—Collar structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05553—Shape in top view being rectangular
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/4826—Connecting between the body and an opposite side of the item with respect to the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73215—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE:To house a large chip in a small package, to reduce thermal stress of a wire bonded section, to obtain a lead burying length and to decrease the influence of a mechanical stress at the time of forming leads by arraying a bonding pad substantially at the center of an LSI chip on a linear line in the longitudinal direction of a chip. CONSTITUTION:A plurality of bonding pads 1 are provided on a rectangular LSI chip 5, leads 7 are radially arranged on the peripheral edge of the chip 5, and the pads 1 are electrically connected by wire bonding to one ends of the leads 7. The pads 1 of a semiconductor device having a resin sealing package 9 of such a structure are arrayed substantially at the center of the chip 5 on a linear line in the longitudinal direction of the chip 5. For example, the surface of the chip 5 except the pads 1 is covered with a heat resistant electric insulating film 10, the covered surface and the rear face of a lead frame 6 are bonded fixedly in such a manner that the pads 1 oppose the ends of the leads 7, and the pads 1 are wire bonded to the end surfaces of the leads 7.
JP62161333A 1987-06-30 1987-06-30 Semiconductor device and manufacturing method thereof Expired - Fee Related JPH0777226B2 (en)

Priority Applications (7)

Application Number Priority Date Filing Date Title
JP62161333A JPH0777226B2 (en) 1987-06-30 1987-06-30 Semiconductor device and manufacturing method thereof
KR1019880007311A KR960013778B1 (en) 1987-06-30 1988-06-17 Semiconductor memory device
US07/640,584 US5184208A (en) 1987-06-30 1991-01-14 Semiconductor device
KR1019920012675A KR970004216B1 (en) 1987-06-30 1992-07-16 Semiconductor memory device
US08/000,125 US5365113A (en) 1987-06-30 1993-01-04 Semiconductor device
US08/329,824 US5514905A (en) 1987-06-30 1994-10-27 Semiconductor device
US08/458,166 US5742101A (en) 1987-06-30 1995-06-02 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62161333A JPH0777226B2 (en) 1987-06-30 1987-06-30 Semiconductor device and manufacturing method thereof

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP8191868A Division JP2911409B2 (en) 1996-07-22 1996-07-22 Semiconductor device

Publications (2)

Publication Number Publication Date
JPS647628A true JPS647628A (en) 1989-01-11
JPH0777226B2 JPH0777226B2 (en) 1995-08-16

Family

ID=15733088

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62161333A Expired - Fee Related JPH0777226B2 (en) 1987-06-30 1987-06-30 Semiconductor device and manufacturing method thereof

Country Status (1)

Country Link
JP (1) JPH0777226B2 (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0433695A2 (en) * 1989-12-22 1991-06-26 Texas Instruments Incorporated Integrated circuit device and method to prevent cracking during surface mount
JPH08241937A (en) * 1996-03-21 1996-09-17 Hitachi Ltd Semiconductor device
JPH08255854A (en) * 1996-03-21 1996-10-01 Hitachi Ltd Semiconductor device and manufacture thereof
US6194779B1 (en) 1989-11-28 2001-02-27 Kabushiki Kaisha Toshiba Plastic mold type semiconductor device
JP2006286688A (en) * 2005-03-31 2006-10-19 Elpida Memory Inc Semiconductor device

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5773954A (en) * 1980-10-25 1982-05-08 Toshiba Corp Integrated circuit
JPS58124251A (en) * 1982-01-20 1983-07-23 Mitsubishi Electric Corp Resin-sealed type semiconductor device
JPS6150355A (en) * 1984-08-20 1986-03-12 Toshiba Corp Semiconductor device
JPS61241959A (en) * 1985-04-18 1986-10-28 インタ−ナショナル　ビジネス　マシ−ンズ　コ−ポレ−ション Semiconductor module
JPS6216022A (en) * 1985-07-12 1987-01-24 株式会社東芝 Semiconductor type current compensator
JPS62296528A (en) * 1986-06-17 1987-12-23 Matsushita Electronics Corp Resin-sealed semiconductor device

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5773954A (en) * 1980-10-25 1982-05-08 Toshiba Corp Integrated circuit
JPS58124251A (en) * 1982-01-20 1983-07-23 Mitsubishi Electric Corp Resin-sealed type semiconductor device
JPS6150355A (en) * 1984-08-20 1986-03-12 Toshiba Corp Semiconductor device
JPS61241959A (en) * 1985-04-18 1986-10-28 インタ−ナショナル　ビジネス　マシ−ンズ　コ−ポレ−ション Semiconductor module
JPS6216022A (en) * 1985-07-12 1987-01-24 株式会社東芝 Semiconductor type current compensator
JPS62296528A (en) * 1986-06-17 1987-12-23 Matsushita Electronics Corp Resin-sealed semiconductor device

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6194779B1 (en) 1989-11-28 2001-02-27 Kabushiki Kaisha Toshiba Plastic mold type semiconductor device
EP0433695A2 (en) * 1989-12-22 1991-06-26 Texas Instruments Incorporated Integrated circuit device and method to prevent cracking during surface mount
EP0433695A3 (en) * 1989-12-22 1991-10-02 Texas Instruments Incorporated Integrated circuit device and method to prevent cracking during surface mount
JPH08241937A (en) * 1996-03-21 1996-09-17 Hitachi Ltd Semiconductor device
JPH08255854A (en) * 1996-03-21 1996-10-01 Hitachi Ltd Semiconductor device and manufacture thereof
JP2006286688A (en) * 2005-03-31 2006-10-19 Elpida Memory Inc Semiconductor device

Also Published As

Publication number Publication date
JPH0777226B2 (en) 1995-08-16

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