JPS6455291A - Integrated circuit device - Google Patents

Integrated circuit device

Info

Publication number
JPS6455291A
JPS6455291A JP62212085A JP21208587A JPS6455291A JP S6455291 A JPS6455291 A JP S6455291A JP 62212085 A JP62212085 A JP 62212085A JP 21208587 A JP21208587 A JP 21208587A JP S6455291 A JPS6455291 A JP S6455291A
Authority
JP
Japan
Prior art keywords
integrated device
lead frame
face
unit
sealing resin
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62212085A
Other languages
Japanese (ja)
Inventor
Kenji Uenishi
Tatsuo Kikuchi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP62212085A priority Critical patent/JPS6455291A/en
Priority to KR1019890700727A priority patent/KR920008509B1/en
Priority to US07/586,392 priority patent/US5122860A/en
Priority to AU23093/88A priority patent/AU2309388A/en
Priority to PCT/JP1988/000842 priority patent/WO1989001873A1/en
Publication of JPS6455291A publication Critical patent/JPS6455291A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

Landscapes

  • Lead Frames For Integrated Circuits (AREA)
  • Credit Cards Or The Like (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Static Random-Access Memory (AREA)

Abstract

PURPOSE: To enable inexpensive production of thickness as an IC unit by mounting and bonding an integrated device on the face opposite to a lead frame fabricated in a desired shape, and by covering a part of the lead frame with sealing resin for this integrated device. CONSTITUTION: For a lead frame 40 that has been formed in a prescribed shape, its one face is used as external connection terminals 40a and the integrated device 50 is die-bonded on the other face 40b, and the other face 40b and connecting pad portion of the integrated device 50 are connected with wire bonding 60 of such materials as gold, aluminum and copper. After required connection between the integrated device 50 and the lead frame 40 are conducted, the integrated device 50 is protected with transfer molding technique using sealing resin 70. An IC unit 100 is obtained in this manner. This structure eliminates necessity of precision circuit substrate with a high accuracy, enables use of general lead frame that is inexpensive, and allows easy manufacture of products as IC unit with arbitrary thickness.
JP62212085A 1987-08-26 1987-08-26 Integrated circuit device Pending JPS6455291A (en)

Priority Applications (5)

Application Number Priority Date Filing Date Title
JP62212085A JPS6455291A (en) 1987-08-26 1987-08-26 Integrated circuit device
KR1019890700727A KR920008509B1 (en) 1987-08-26 1988-08-25 Integration circuits apparatus and manufacturing method
US07/586,392 US5122860A (en) 1987-08-26 1988-08-25 Integrated circuit device and manufacturing method thereof
AU23093/88A AU2309388A (en) 1987-08-26 1988-08-25 Integrated circuit device and method of producing the same
PCT/JP1988/000842 WO1989001873A1 (en) 1987-08-26 1988-08-25 Integrated circuit device and method of producing the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62212085A JPS6455291A (en) 1987-08-26 1987-08-26 Integrated circuit device

Publications (1)

Publication Number Publication Date
JPS6455291A true JPS6455291A (en) 1989-03-02

Family

ID=16616623

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62212085A Pending JPS6455291A (en) 1987-08-26 1987-08-26 Integrated circuit device

Country Status (1)

Country Link
JP (1) JPS6455291A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10116935A (en) * 1996-10-08 1998-05-06 Fujitsu Ltd Semiconductor device and its manufacturing method
JPH11297750A (en) * 1998-04-08 1999-10-29 Matsushita Electron Corp Semiconductor device, manufacture thereof, and mounting of the semiconductor device
JP2006140265A (en) * 2004-11-11 2006-06-01 Denso Corp Semiconductor device and manufacturing method of lead frame used therefor
JP2011171770A (en) * 2011-06-06 2011-09-01 Dainippon Printing Co Ltd Circuit member, manufacturing method of the same, semiconductor device and multilayer structure of surface of circuit member

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10116935A (en) * 1996-10-08 1998-05-06 Fujitsu Ltd Semiconductor device and its manufacturing method
JPH11297750A (en) * 1998-04-08 1999-10-29 Matsushita Electron Corp Semiconductor device, manufacture thereof, and mounting of the semiconductor device
JP2006140265A (en) * 2004-11-11 2006-06-01 Denso Corp Semiconductor device and manufacturing method of lead frame used therefor
JP2011171770A (en) * 2011-06-06 2011-09-01 Dainippon Printing Co Ltd Circuit member, manufacturing method of the same, semiconductor device and multilayer structure of surface of circuit member

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