JPS5769765A - Sealed body of semiconductor device - Google Patents

Sealed body of semiconductor device

Info

Publication number
JPS5769765A
JPS5769765A JP55146137A JP14613780A JPS5769765A JP S5769765 A JPS5769765 A JP S5769765A JP 55146137 A JP55146137 A JP 55146137A JP 14613780 A JP14613780 A JP 14613780A JP S5769765 A JPS5769765 A JP S5769765A
Authority
JP
Japan
Prior art keywords
semiconductor device
substrate
wiring
film
conductors
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP55146137A
Other languages
Japanese (ja)
Other versions
JPS6042620B2 (en
Inventor
Kenji Higashiyama
Hisashi Nakamura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP55146137A priority Critical patent/JPS6042620B2/en
Publication of JPS5769765A publication Critical patent/JPS5769765A/en
Publication of JPS6042620B2 publication Critical patent/JPS6042620B2/en
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/4985—Flexible insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE:To enhance heat radiability and to miniaturize a semiconductor device by a method wherein the semiconductor chip and a flexible film being formed with conductors for wiring are joined on a substrate having favorable thermal conductivity, and after wire bonding of the chip and the conductors for wiring is performed, the device is sealed with resin. CONSTITUTION:The semiconductor device 9 is joined on the substrate 8 consisting of a copper plate having favorable thermal radiability, while the conductors 12 for wiring are formed on the surface of the polyimide film 11, a part 13 to insert the semiconductor device 9 therein is dug in the film 11, and the film is adhered on the surface of the substrate 8 with an adhesive 14 as the semiconductor device 9 is to be placed at the center of the part thereof. Bonding pads on the semiconductor device and the conductors 12 for wiring are connected by wire bonding of gold wires 15, the epoxy resin 16 is covered thereon as to cover the semiconductor device 9 and the gold wires 15, and the outside circumferential parts of the film 11 formed with conductor wiring are made to protrude from the substrate 8. Accordingly radiation of heat from the copper substrate is favorable, the device can be formed thinly and can be miniaturized, and is suitable for mass production.
JP55146137A 1980-10-17 1980-10-17 Semiconductor device encapsulation Expired JPS6042620B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55146137A JPS6042620B2 (en) 1980-10-17 1980-10-17 Semiconductor device encapsulation

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55146137A JPS6042620B2 (en) 1980-10-17 1980-10-17 Semiconductor device encapsulation

Publications (2)

Publication Number Publication Date
JPS5769765A true JPS5769765A (en) 1982-04-28
JPS6042620B2 JPS6042620B2 (en) 1985-09-24

Family

ID=15400971

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55146137A Expired JPS6042620B2 (en) 1980-10-17 1980-10-17 Semiconductor device encapsulation

Country Status (1)

Country Link
JP (1) JPS6042620B2 (en)

Cited By (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61237663A (en) * 1985-04-15 1986-10-22 Toshiba Corp Thermal printer head
JPS6248571A (en) * 1985-08-28 1987-03-03 Toshiba Corp Thermal printing head
JPS6437042A (en) * 1987-07-31 1989-02-07 Ibiden Co Ltd Substrate for carrying electronic component
JPH01146529U (en) * 1988-03-31 1989-10-09
FR2651923A1 (en) * 1989-09-14 1991-03-15 Peugeot Power integrated circuit
US5012322A (en) * 1987-05-18 1991-04-30 Allegro Microsystems, Inc. Semiconductor die and mounting assembly
US5139973A (en) * 1990-12-17 1992-08-18 Allegro Microsystems, Inc. Method for making a semiconductor package with the distance between a lead frame die pad and heat spreader determined by the thickness of an intermediary insulating sheet
JPH05211204A (en) * 1991-11-29 1993-08-20 Akira Kitahara Surface mount electronic part
US5616958A (en) * 1995-01-25 1997-04-01 International Business Machines Corporation Electronic package
JPH0997857A (en) * 1995-09-28 1997-04-08 Nec Kyushu Ltd Semiconductor device and its manufacture
JPH09298251A (en) * 1996-04-30 1997-11-18 Yamaichi Electron Co Ltd Ic package
US6953991B2 (en) 2000-07-19 2005-10-11 Shindo Company, Ltd. Semiconductor device
US8159830B2 (en) * 2009-04-17 2012-04-17 Atmel Corporation Surface mounting chip carrier module

Cited By (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61237663A (en) * 1985-04-15 1986-10-22 Toshiba Corp Thermal printer head
JPS6248571A (en) * 1985-08-28 1987-03-03 Toshiba Corp Thermal printing head
US5012322A (en) * 1987-05-18 1991-04-30 Allegro Microsystems, Inc. Semiconductor die and mounting assembly
JPH0529146B2 (en) * 1987-07-31 1993-04-28 Ibiden Co Ltd
JPS6437042A (en) * 1987-07-31 1989-02-07 Ibiden Co Ltd Substrate for carrying electronic component
JPH01146529U (en) * 1988-03-31 1989-10-09
FR2651923A1 (en) * 1989-09-14 1991-03-15 Peugeot Power integrated circuit
US5139973A (en) * 1990-12-17 1992-08-18 Allegro Microsystems, Inc. Method for making a semiconductor package with the distance between a lead frame die pad and heat spreader determined by the thickness of an intermediary insulating sheet
JPH05211204A (en) * 1991-11-29 1993-08-20 Akira Kitahara Surface mount electronic part
US5616958A (en) * 1995-01-25 1997-04-01 International Business Machines Corporation Electronic package
US5728606A (en) * 1995-01-25 1998-03-17 International Business Machines Corporation Electronic Package
JPH0997857A (en) * 1995-09-28 1997-04-08 Nec Kyushu Ltd Semiconductor device and its manufacture
JPH09298251A (en) * 1996-04-30 1997-11-18 Yamaichi Electron Co Ltd Ic package
US6953991B2 (en) 2000-07-19 2005-10-11 Shindo Company, Ltd. Semiconductor device
US8159830B2 (en) * 2009-04-17 2012-04-17 Atmel Corporation Surface mounting chip carrier module

Also Published As

Publication number Publication date
JPS6042620B2 (en) 1985-09-24

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