JPS57166051A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS57166051A
JPS57166051A JP5344481A JP5344481A JPS57166051A JP S57166051 A JPS57166051 A JP S57166051A JP 5344481 A JP5344481 A JP 5344481A JP 5344481 A JP5344481 A JP 5344481A JP S57166051 A JPS57166051 A JP S57166051A
Authority
JP
Japan
Prior art keywords
chips
substrate
layers
wiring
mutually
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP5344481A
Other languages
Japanese (ja)
Other versions
JPS6220707B2 (en
Inventor
Miyoshi Yoshida
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP5344481A priority Critical patent/JPS57166051A/en
Publication of JPS57166051A publication Critical patent/JPS57166051A/en
Publication of JPS6220707B2 publication Critical patent/JPS6220707B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5385—Assembly of a plurality of insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE:To obtain a semiconductor device for large electric power consumption having high reliability receiving no influence of heat cycle and being easy to change the design by a method wherein IC chips are equipped directly to a metal cover, and wiring layers to connect them mutually are formed of substrates having the same quality of the material with the IC chips, etc. CONSTITUTION:Si IC chips 1 are fixed directly to a metal cover 3 provided with rugged part for cooling, and are connected mutually by an Si substrate 4. The substrate 4 is constituted of Si layers 4a covered with SiO2 films 4b, the layers thereof are connected mutually by a wiring layer 4c or by penetrating the Si layers 4a, or the layers thereof are sired in the multilayer type through insulating films 4d, and is connected to solder bumps 2 of the chips. A connector 7 in which metal wires 7b are buried in Si rubber 7a is arranged between the substrate 4 and a substrate 5 in which lead parts of wiring 5b connected to outside leads 6 are interposed between multilayer ceramic substrate 5a. When a cover 3 and the substrate 5 are fixed, the chips are sealed in inside space, and the electric faculty of the chips can be led out to the leads. Because the chips 1 and the substrate are constituted of the same material, and the connector 7 absorbs heat, influence of heat cycle is not applied.
JP5344481A 1981-04-06 1981-04-06 Semiconductor device Granted JPS57166051A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5344481A JPS57166051A (en) 1981-04-06 1981-04-06 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5344481A JPS57166051A (en) 1981-04-06 1981-04-06 Semiconductor device

Publications (2)

Publication Number Publication Date
JPS57166051A true JPS57166051A (en) 1982-10-13
JPS6220707B2 JPS6220707B2 (en) 1987-05-08

Family

ID=12943019

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5344481A Granted JPS57166051A (en) 1981-04-06 1981-04-06 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS57166051A (en)

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61139014U (en) * 1985-02-18 1986-08-28
US4628406A (en) * 1985-05-20 1986-12-09 Tektronix, Inc. Method of packaging integrated circuit chips, and integrated circuit package
JPS6332958A (en) * 1986-05-07 1988-02-12 デイジタル　イクイプメントコ−ポレ−シヨン System for attaching semiconductor onto conductor substrate so as to be detachable
US5014161A (en) * 1985-07-22 1991-05-07 Digital Equipment Corporation System for detachably mounting semiconductors on conductor substrate
JPH07297560A (en) * 1994-04-28 1995-11-10 Hitachi Ltd Multilayer printed wiring board and its mounting structure
EP0722186A2 (en) * 1995-01-13 1996-07-17 Murata Manufacturing Co., Ltd. Laminated electronic part
WO1998004000A1 (en) * 1996-07-22 1998-01-29 Honda Giken Kogyo Kabushiki Kaisha Plug-in type electronic control unit, connecting structure between wiring board and plug member, connecting unit between electronic parts and wiring board, and electronic parts mounting method
US8441118B2 (en) 2005-06-30 2013-05-14 Intel Corporation Electromigration-resistant and compliant wire interconnects, nano-sized solder compositions, systems made thereof, and methods of assembling soldered packages

Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61139014U (en) * 1985-02-18 1986-08-28
US4628406A (en) * 1985-05-20 1986-12-09 Tektronix, Inc. Method of packaging integrated circuit chips, and integrated circuit package
US5014161A (en) * 1985-07-22 1991-05-07 Digital Equipment Corporation System for detachably mounting semiconductors on conductor substrate
JPS6332958A (en) * 1986-05-07 1988-02-12 デイジタル　イクイプメントコ−ポレ−シヨン System for attaching semiconductor onto conductor substrate so as to be detachable
JPH07297560A (en) * 1994-04-28 1995-11-10 Hitachi Ltd Multilayer printed wiring board and its mounting structure
EP0722186A2 (en) * 1995-01-13 1996-07-17 Murata Manufacturing Co., Ltd. Laminated electronic part
EP0722186A3 (en) * 1995-01-13 1997-04-23 Murata Manufacturing Co Laminated electronic part
US6004657A (en) * 1995-01-13 1999-12-21 Murata Manufacturing Co., Ltd. Laminated electronic part
WO1998004000A1 (en) * 1996-07-22 1998-01-29 Honda Giken Kogyo Kabushiki Kaisha Plug-in type electronic control unit, connecting structure between wiring board and plug member, connecting unit between electronic parts and wiring board, and electronic parts mounting method
US6720500B1 (en) * 1996-07-22 2004-04-13 Honda Giken Kogyo Kabushiki Kaisha Plug-in type electronic control unit, structure of connection of wiring board with plug member, unit of connection of electronic part with wiring board, and process for mounting electronic part
US8441118B2 (en) 2005-06-30 2013-05-14 Intel Corporation Electromigration-resistant and compliant wire interconnects, nano-sized solder compositions, systems made thereof, and methods of assembling soldered packages
TWI470753B (en) * 2005-06-30 2015-01-21 Intel Corp Wire interconnect article and computing system comprising the same

Also Published As

Publication number Publication date
JPS6220707B2 (en) 1987-05-08

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