JPS57107059A - Semiconductor package - Google Patents

Semiconductor package

Info

Publication number
JPS57107059A
JPS57107059A JP18473780A JP18473780A JPS57107059A JP S57107059 A JPS57107059 A JP S57107059A JP 18473780 A JP18473780 A JP 18473780A JP 18473780 A JP18473780 A JP 18473780A JP S57107059 A JPS57107059 A JP S57107059A
Authority
JP
Japan
Prior art keywords
conductor
grounding
power supply
conductors
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP18473780A
Other languages
Japanese (ja)
Other versions
JPS6256664B2 (en
Inventor
Norikuni Azuma
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP18473780A priority Critical patent/JPS57107059A/en
Publication of JPS57107059A publication Critical patent/JPS57107059A/en
Publication of JPS6256664B2 publication Critical patent/JPS6256664B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5221—Crossover interconnections
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49822—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

PURPOSE:To improve reliability by minimizing the level variation for reduction in noise with a grounding conductor only or a grounding conductor and a power supply conductor provided at the bottom of and also around the sides of the chip inside the package. CONSTITUTION:In a package composed of ceramic, for example, the grounding conductor 10 consisting of a bottom conductor 11, side conductors 12 and exposed conductors 13 is provided at the cavity for accommodating the IC chip 1. A wide connecting conductor 14 is provided for connection between the ground conductor 10 and an external terminal by forming an underneath layer which is different from the bond wirings 2. On the exposed conductors 13, ground wire bonding is applied. Other than the layer of the ground conductor 10, an another conductor layers, the power supply conductor 15, may be provided in double layer construction with a ceramic sheet interlaid. This layer consists likewise of a bottom conductor 16, side conductors 17, exposed conductors 18 and connecting conductor 19. This construction gives higher reliability which can allow preventing variation of the grounding level or power supply level.
JP18473780A 1980-12-25 1980-12-25 Semiconductor package Granted JPS57107059A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18473780A JPS57107059A (en) 1980-12-25 1980-12-25 Semiconductor package

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18473780A JPS57107059A (en) 1980-12-25 1980-12-25 Semiconductor package

Publications (2)

Publication Number Publication Date
JPS57107059A true JPS57107059A (en) 1982-07-03
JPS6256664B2 JPS6256664B2 (en) 1987-11-26

Family

ID=16158474

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18473780A Granted JPS57107059A (en) 1980-12-25 1980-12-25 Semiconductor package

Country Status (1)

Country Link
JP (1) JPS57107059A (en)

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5839038A (en) * 1981-08-14 1983-03-07 アンプ・インコ−ポレ−テツド Semiconductor chip carrier
JPS596563A (en) * 1982-07-05 1984-01-13 Nec Corp Integrated circuit device
JPS6038841A (en) * 1983-08-12 1985-02-28 Hitachi Ltd Semiconductor device
JPS60148148A (en) * 1984-01-13 1985-08-05 Nec Corp Semiconductor device
JPS6122358U (en) * 1984-07-12 1986-02-08 株式会社東芝 Pin grid array package
JPH04133341A (en) * 1990-09-25 1992-05-07 Matsushita Electric Works Ltd Semiconductor chip carrier
US5225709A (en) * 1990-06-15 1993-07-06 Hitachi, Ltd. Package having a structure for stabilizing and/or impedance-matching a semiconductor IC device accommodated therein
JP2005244214A (en) * 2004-02-24 2005-09-08 Samsung Electronics Co Ltd Semiconductor element and method for preventing electrostatic discharge

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5185349A (en) * 1975-01-24 1976-07-26 Hitachi Ltd
JPS5272169A (en) * 1975-12-12 1977-06-16 Nec Corp Semiconductor device
JPS5415663A (en) * 1974-01-10 1979-02-05 Nec Corp Semiconductor device

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5415663A (en) * 1974-01-10 1979-02-05 Nec Corp Semiconductor device
JPS5185349A (en) * 1975-01-24 1976-07-26 Hitachi Ltd
JPS5272169A (en) * 1975-12-12 1977-06-16 Nec Corp Semiconductor device

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5839038A (en) * 1981-08-14 1983-03-07 アンプ・インコ−ポレ−テツド Semiconductor chip carrier
JPS6332263B2 (en) * 1981-08-14 1988-06-29 Amp Inc
JPS596563A (en) * 1982-07-05 1984-01-13 Nec Corp Integrated circuit device
JPS6038841A (en) * 1983-08-12 1985-02-28 Hitachi Ltd Semiconductor device
JPS60148148A (en) * 1984-01-13 1985-08-05 Nec Corp Semiconductor device
JPH0160941B2 (en) * 1984-01-13 1989-12-26 Nippon Electric Co
JPS6122358U (en) * 1984-07-12 1986-02-08 株式会社東芝 Pin grid array package
JPH0134355Y2 (en) * 1984-07-12 1989-10-19
US5225709A (en) * 1990-06-15 1993-07-06 Hitachi, Ltd. Package having a structure for stabilizing and/or impedance-matching a semiconductor IC device accommodated therein
JPH04133341A (en) * 1990-09-25 1992-05-07 Matsushita Electric Works Ltd Semiconductor chip carrier
JP2005244214A (en) * 2004-02-24 2005-09-08 Samsung Electronics Co Ltd Semiconductor element and method for preventing electrostatic discharge

Also Published As

Publication number Publication date
JPS6256664B2 (en) 1987-11-26

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