JPS5651851A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS5651851A
JPS5651851A JP12790879A JP12790879A JPS5651851A JP S5651851 A JPS5651851 A JP S5651851A JP 12790879 A JP12790879 A JP 12790879A JP 12790879 A JP12790879 A JP 12790879A JP S5651851 A JPS5651851 A JP S5651851A
Authority
JP
Japan
Prior art keywords
package
wires
lead
stage
fixed
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12790879A
Other languages
Japanese (ja)
Inventor
Tamotsu Usami
Kanji Otsuka
Mitsuyasu Nishizono
Takashi Araki
Mutsuo Fuda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NITSUKAN DENSHI KK
Hitachi Ltd
Original Assignee
NITSUKAN DENSHI KK
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NITSUKAN DENSHI KK, Hitachi Ltd filed Critical NITSUKAN DENSHI KK
Priority to JP12790879A priority Critical patent/JPS5651851A/en
Publication of JPS5651851A publication Critical patent/JPS5651851A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49537—Plurality of lead frames mounted in one device
    • H—ELECTRICITY
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
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    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
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    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
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    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
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    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/49105—Connecting at different heights
    • H01L2224/49109—Connecting at different heights outside the semiconductor or solid-state body
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49175—Parallel arrangements
    • H—ELECTRICITY
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/494—Connecting portions
    • H01L2224/4943—Connecting portions the connecting portions being staggered
    • H01L2224/49431—Connecting portions the connecting portions being staggered on the semiconductor or solid-state body
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/494—Connecting portions
    • H01L2224/4943—Connecting portions the connecting portions being staggered
    • H01L2224/49433—Connecting portions the connecting portions being staggered outside the semiconductor or solid-state body
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    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H—ELECTRICITY
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/15165—Monolayer substrate
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    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE:To prevent the occurrence of shortcircuit between wires, by arranging joints of the wires on package side in a multistage configuration and in shifted positions. CONSTITUTION:A semiconductor pellet 11 is fixed onto bottom of a ceramic base 121. A lead 13A is fixed to a ceramic package 12, one end of which is exposed on the second stage on side surface of a base indentation 124, and other end is led to outside of the package. By providing a metalized layer 13b which is exposed the first stage and led to outside of the package, a lead 13B is fixed to the layer 13b. The lead 13A, the metalized layer 13b an the pellet 11 are connected by a wire 14. It is possible, by doing so, to increase by approximately double the intervals between wires to be connected on the same stage and also to prevent the occurrence of shortcircuit.
JP12790879A 1979-10-05 1979-10-05 Semiconductor device Pending JPS5651851A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12790879A JPS5651851A (en) 1979-10-05 1979-10-05 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12790879A JPS5651851A (en) 1979-10-05 1979-10-05 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS5651851A true JPS5651851A (en) 1981-05-09

Family

ID=14971624

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12790879A Pending JPS5651851A (en) 1979-10-05 1979-10-05 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS5651851A (en)

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2557366A1 (en) * 1983-12-27 1985-06-28 Mitsubishi Electric Corp Integrated circuit semiconductor connection pattern
JPS6448039U (en) * 1987-09-21 1989-03-24
US4860087A (en) * 1986-03-26 1989-08-22 Hitachi, Ltd. Semiconductor device and process for producing the same
US5117275A (en) * 1990-10-24 1992-05-26 International Business Machines Corporation Electronic substrate multiple location conductor attachment technology
US5229328A (en) * 1990-10-24 1993-07-20 International Business Machines Corporation Method for bonding dielectric mounted conductors to semiconductor chip contact pads
US5233221A (en) * 1990-10-24 1993-08-03 International Business Machines Corporation Electronic substrate multiple location conductor attachment technology
US5468999A (en) * 1994-05-26 1995-11-21 Motorola, Inc. Liquid encapsulated ball grid array semiconductor device with fine pitch wire bonding
US5569955A (en) * 1994-09-16 1996-10-29 National Semiconductor Corporation High density integrated circuit assembly combining leadframe leads with conductive traces

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS519681A (en) * 1974-07-15 1976-01-26 Seiko Instr & Electronics
JPS5299769A (en) * 1976-02-18 1977-08-22 Toshiba Corp Pellet for semiconductor device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS519681A (en) * 1974-07-15 1976-01-26 Seiko Instr & Electronics
JPS5299769A (en) * 1976-02-18 1977-08-22 Toshiba Corp Pellet for semiconductor device

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2557366A1 (en) * 1983-12-27 1985-06-28 Mitsubishi Electric Corp Integrated circuit semiconductor connection pattern
US4860087A (en) * 1986-03-26 1989-08-22 Hitachi, Ltd. Semiconductor device and process for producing the same
JPS6448039U (en) * 1987-09-21 1989-03-24
US5117275A (en) * 1990-10-24 1992-05-26 International Business Machines Corporation Electronic substrate multiple location conductor attachment technology
US5229328A (en) * 1990-10-24 1993-07-20 International Business Machines Corporation Method for bonding dielectric mounted conductors to semiconductor chip contact pads
US5233221A (en) * 1990-10-24 1993-08-03 International Business Machines Corporation Electronic substrate multiple location conductor attachment technology
US5468999A (en) * 1994-05-26 1995-11-21 Motorola, Inc. Liquid encapsulated ball grid array semiconductor device with fine pitch wire bonding
US5569955A (en) * 1994-09-16 1996-10-29 National Semiconductor Corporation High density integrated circuit assembly combining leadframe leads with conductive traces

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