JPS55157254A - Digital-to-analog converter - Google Patents

Digital-to-analog converter

Info

Publication number
JPS55157254A
JPS55157254A JP6518579A JP6518579A JPS55157254A JP S55157254 A JPS55157254 A JP S55157254A JP 6518579 A JP6518579 A JP 6518579A JP 6518579 A JP6518579 A JP 6518579A JP S55157254 A JPS55157254 A JP S55157254A
Authority
JP
Japan
Prior art keywords
substrate
side main
resistor network
main face
digital
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6518579A
Other languages
Japanese (ja)
Inventor
Hiroshi Kitazaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP6518579A priority Critical patent/JPS55157254A/en
Publication of JPS55157254A publication Critical patent/JPS55157254A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0688—Integrated circuits having a three-dimensional layout
    • H01L27/0694—Integrated circuits having a three-dimensional layout comprising components formed on opposite sides of a semiconductor substrate

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Analogue/Digital Conversion (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

PURPOSE:To attempt to miniaturize a digital-to-analog converter by a method wherein a semiconductor integrated circuit is formed on one side main face of an Si substrate, and a weight resistor network is formed on another side main face of the substrate. CONSTITUTION:A semiconductor integrated circuit 12 is formed on one side main face of an Si substrate 11, and a weight resistor network 13 is formed on another side main face of the substrate. A wiring conductor 16 is formed on a ceramic package 15 and a bump processed circuit element 12 is bonded with face down on it. The weight resistor network 13 is bonded with wires 18. Therefore, as the integrated circuit 12 and the weight resistor network 13 are made in one body, the ceramic package can be miniaturized.
JP6518579A 1979-05-26 1979-05-26 Digital-to-analog converter Pending JPS55157254A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6518579A JPS55157254A (en) 1979-05-26 1979-05-26 Digital-to-analog converter

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6518579A JPS55157254A (en) 1979-05-26 1979-05-26 Digital-to-analog converter

Publications (1)

Publication Number Publication Date
JPS55157254A true JPS55157254A (en) 1980-12-06

Family

ID=13279602

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6518579A Pending JPS55157254A (en) 1979-05-26 1979-05-26 Digital-to-analog converter

Country Status (1)

Country Link
JP (1) JPS55157254A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007096017A (en) * 2005-09-29 2007-04-12 Seiko Epson Corp Trimming method, semiconductor device and chip component for trimming

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007096017A (en) * 2005-09-29 2007-04-12 Seiko Epson Corp Trimming method, semiconductor device and chip component for trimming

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