JPS56114361A - Semiconductor container - Google Patents

Semiconductor container

Info

Publication number
JPS56114361A
JPS56114361A JP1693180A JP1693180A JPS56114361A JP S56114361 A JPS56114361 A JP S56114361A JP 1693180 A JP1693180 A JP 1693180A JP 1693180 A JP1693180 A JP 1693180A JP S56114361 A JPS56114361 A JP S56114361A
Authority
JP
Grant status
Application
Patent type
Prior art keywords
part
usage
container
formed
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1693180A
Other versions
JPS6041859B2 (en )
Inventor
Takashi Kondo
Isao Okura
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date

Links

Classifications

    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5383Multilayer substrates
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15312Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a pin array, e.g. PGA

Abstract

PURPOSE:To enable the semiconductor container in wide usage and in high precision to be obtained by a method wherein the container is composed of two parts, one is made to a common shape without depending on the usage and the other is formed fitted to the usage at low temperature and in high precision. CONSTITUTION:The semiconductor container 2 is constructed by an insulator layer 211, conductor layer 212, connecting means 213 constituting one layer and a module substrate part 21 by external lead terminals 214 and a multilayer wiring part 22 by a connecting means 223 through an insulator layer 221, conductor layer 222 and through hole. The semiconductor device 1 is arranged connected to the conductor layer 222 on the part 22. The part 21 has patterns common over, e.g., several kinds of the usages without being limited to the particular usage. On the other hand, the part 22 is formed in higher precision at low temperature than those of the part 21 and formed with a peculiar pattern fitted to the usage with respect to the comparatively smooth module substrate surface. Whereby the semiconducdor container rich in usability and high in precision can be attained.
JP1693180A 1980-02-13 1980-02-13 Expired JPS6041859B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1693180A JPS6041859B2 (en) 1980-02-13 1980-02-13

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1693180A JPS6041859B2 (en) 1980-02-13 1980-02-13

Publications (2)

Publication Number Publication Date
JPS56114361A true true JPS56114361A (en) 1981-09-08
JPS6041859B2 JPS6041859B2 (en) 1985-09-19

Family

ID=11929862

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1693180A Expired JPS6041859B2 (en) 1980-02-13 1980-02-13

Country Status (1)

Country Link
JP (1) JPS6041859B2 (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5842263A (en) * 1981-09-04 1983-03-11 Nec Corp Multichip package
JPS5958848A (en) * 1982-09-29 1984-04-04 Nec Corp Manufacture of ceramic wiring board
JPS6077452A (en) * 1983-09-22 1985-05-02 Ibm Device for supplying plural integrated circuit operating voltage
JPS60183746A (en) * 1984-03-02 1985-09-19 Hitachi Ltd Semiconductor device
JPS6231146A (en) * 1985-08-02 1987-02-10 Nec Corp Multilayer wiring substrate
WO1998011605A1 (en) * 1995-06-19 1998-03-19 Ibiden Co., Ltd. Circuit board for mounting electronic parts

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6281450B1 (en) * 1997-06-26 2001-08-28 Hitachi Chemical Company, Ltd. Substrate for mounting semiconductor chips

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5842263A (en) * 1981-09-04 1983-03-11 Nec Corp Multichip package
JPS5958848A (en) * 1982-09-29 1984-04-04 Nec Corp Manufacture of ceramic wiring board
JPS6077452A (en) * 1983-09-22 1985-05-02 Ibm Device for supplying plural integrated circuit operating voltage
JPS60183746A (en) * 1984-03-02 1985-09-19 Hitachi Ltd Semiconductor device
JPS6231146A (en) * 1985-08-02 1987-02-10 Nec Corp Multilayer wiring substrate
WO1998011605A1 (en) * 1995-06-19 1998-03-19 Ibiden Co., Ltd. Circuit board for mounting electronic parts
USRE44251E1 (en) 1996-09-12 2013-06-04 Ibiden Co., Ltd. Circuit board for mounting electronic parts

Also Published As

Publication number Publication date Type
JPS6041859B2 (en) 1985-09-19 grant

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