JPS5958848A - Manufacture of ceramic wiring board - Google Patents

Manufacture of ceramic wiring board

Info

Publication number
JPS5958848A
JPS5958848A JP16840282A JP16840282A JPS5958848A JP S5958848 A JPS5958848 A JP S5958848A JP 16840282 A JP16840282 A JP 16840282A JP 16840282 A JP16840282 A JP 16840282A JP S5958848 A JPS5958848 A JP S5958848A
Authority
JP
Japan
Prior art keywords
gold
wiring board
electrodes
ceramic wiring
base metal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP16840282A
Other languages
Japanese (ja)
Other versions
JPS641057B2 (en
Inventor
Mitsuru Nitta
満 新田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP16840282A priority Critical patent/JPS5958848A/en
Publication of JPS5958848A publication Critical patent/JPS5958848A/en
Publication of JPS641057B2 publication Critical patent/JPS641057B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5383—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/09—Use of materials for the conductive, e.g. metallic pattern
    • H05K1/092—Dispersed materials, e.g. conductive pastes or inks
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • H05K3/4664—Adding a circuit layer by thick film methods, e.g. printing techniques or by other techniques for making conductive patterns by using pastes, inks or powders
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • H05K3/4673—Application methods or materials of intermediate insulating layers not specially adapted to any one of the previous methods of adding a circuit layer
    • H05K3/4676—Single layer compositions

Abstract

PURPOSE:To obtain the high-reliability ceramic wiring board, cost thereof is low, by forming a main wiring pattern by a base metal and setting up an electrode made of gold to a necessary section. CONSTITUTION:Three layers of main wirings 2, 4, 6 on the ceramic wiring board 1 made of alumina, an enameled iron plate or the like are formed through thick- film printing, plating or the like by using the base metal such as copper, and insulating layers 3, 5 are formed among layers. The electrodes 7, 8 are manufactured in such a manner that gold bases are printed and baked at 500 deg.C or more and the melting point (889 deg.C on copper) or less of an alloy with gold in N2. According to the constitution, the electrodes of excellent adhesive strength and bonding property are obtained, gold wires 12 are bonded, and the electrodes are completed. According to the constitution, the high-reliability substrate, cost thereof is low and bonding property and adhesive strength thereof are excellent, is obtained.

Description

【発明の詳細な説明】 本発明は、セラミック配線基板の製造方法に関し、特に
卑金属導体パターンの所要部に金電極を形成する方法に
関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of manufacturing a ceramic wiring board, and more particularly to a method of forming gold electrodes at desired portions of a base metal conductor pattern.

セラミック配線基板には、接続導体パターンおよびボン
ディングやコンタクトのための電極部などすべての導体
を金で形成したもの：′ある。このような配線基板は、
ボンディングやコンタクトが容易でかつ信頼性も高いが
高価である。一方、すべての導体を銅ペースト等の卑金
属を用いて窒素雰囲気中で焼成して形成した配線基板は
、ボンディングやコンタクトが困難である、このような
配線基板には、一般にＩＣリードや端子は半田付けして
接続するが接続部の信頼性が低いという欠点がある。Some ceramic wiring boards have all conductors, including connection conductor patterns and electrode parts for bonding and contacts, made of gold. This kind of wiring board is
Bonding and contact are easy and reliable, but it is expensive. On the other hand, wiring boards in which all conductors are made of base metals such as copper paste and fired in a nitrogen atmosphere are difficult to bond and contact.In such wiring boards, IC leads and terminals are generally soldered. However, there is a drawback that the reliability of the connection part is low.

本発明の目的は、上述の従来の欠点を解決し、主配線パ
ターンを卑金属で形成し１、所要部に金の電極を形成さ
せた安価高信頼度のセラミック配線基板の製造方法を提
供することにある。An object of the present invention is to solve the above-mentioned conventional drawbacks, and to provide a method for manufacturing an inexpensive and highly reliable ceramic wiring board in which the main wiring pattern is formed of base metal (1) and gold electrodes are formed in required parts. It is in.

本発明の製造方法は、基板上に銅、ニッケル等の卑金属
によって主配線パターンを形成し、該主配線パターン上
の所要部分に、窒素雰囲気中で焼成可能な金ペーストを
塗布した後乾燥し、前記主配線パターンを形成した卑金
属と金の合金の融点以下でかつ５００℃以上の温度恥１
囲の窒素雰囲気中で焼成して前記主配耐パターンの所要
部に金の電極を形成することを特徴とする特 次に、本発明シこついて、図面を参照して詳細に説明す
る。The manufacturing method of the present invention includes forming a main wiring pattern on a substrate using a base metal such as copper or nickel, applying a gold paste that can be fired in a nitrogen atmosphere to required parts of the main wiring pattern, and then drying it. Temperature 1 below the melting point of the alloy of base metal and gold that formed the main wiring pattern and above 500°C
The present invention will be described in detail with reference to the drawings, in which the present invention is characterized in that gold electrodes are formed in required portions of the main resistive pattern by firing in a surrounding nitrogen atmosphere.

第１図は、本発明の製造方法によって製造されたセラミ
ック配線基板の一例を示す平面図であシ、第２図ｔ」、
そのＡ−Ａ断面図である。該セラミック配線基板は、ア
ルミナやホーロー引き鉄板から成る基板１の上に主配線
パターン２，４．６が３層に形成される。願主ｌ！ｄ　
線パターンは、銅等の卑金属を用い公知の厚膜印刷技術
やメッキ技術等によって形成さｒＬる。勿論各層の間に
は、絶縁層３゜５が形成される。そして、ボンディング
電極７およびコンタクト電極８には、窒素雰囲気中で焼
成可能な台ペーストを印刷技術等によって塗布し、オー
ブンやベルト炉などで乾燥する。これを５００Ｃ以上で
かつ金ペーストと接触している卑金属る。これによりボ
ンティング性が良好で密着強贋が強いボンディング電極
７およびコンタクト電極８が形成される。該配線基板上
に搭載される集積回路チップ１０は、金の細線１２によ
り容易にボンディング電極７にボンディングすることが
可能である。ｔ−た、コンタクト電極８のコンタクト信
頼性は大である。FIG. 1 is a plan view showing an example of a ceramic wiring board manufactured by the manufacturing method of the present invention, and FIG.
It is the AA sectional view. In this ceramic wiring board, main wiring patterns 2, 4, and 6 are formed in three layers on a substrate 1 made of alumina or enameled iron plate. Requester l! d
The line pattern is formed by a known thick film printing technique, plating technique, etc. using a base metal such as copper. Of course, an insulating layer 3.5 is formed between each layer. Then, a base paste that can be fired in a nitrogen atmosphere is applied to the bonding electrode 7 and the contact electrode 8 by a printing technique or the like, and then dried in an oven, a belt furnace, or the like. The base metal is heated to 500C or higher and is in contact with the gold paste. As a result, a bonding electrode 7 and a contact electrode 8 having good bonding properties and strong adhesion are formed. The integrated circuit chip 10 mounted on the wiring board can be easily bonded to the bonding electrode 7 using a thin gold wire 12. Furthermore, the contact reliability of the contact electrode 8 is high.

本発明は、配線暴動の配線パターンの層数や搭載部品の
個数、■類等に関係なく適用されることは勿論である。It goes without saying that the present invention can be applied regardless of the number of layers of the wiring pattern, the number of mounted components, type (2), etc. of the wiring riot.

要するに、主配線パターンを卑金属で形成し必要部分に
金ペーストの焼成によって金電極を形成させることによ
り安価でかつボンディング等が容易で接続信頼性の高い
配線基板を製造することができる効果がある。In short, by forming the main wiring pattern with a base metal and forming gold electrodes in necessary parts by firing gold paste, it is possible to manufacture a wiring board that is inexpensive, easy to bond, etc., and has high connection reliability.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は本発明の製造方法によって製造されたセラミッ
ク配線基板の一例を示す平面図、第２図はそのＡ−Ａ断
面図である。 図において、１・・・基板、２，４．６・・・主配線パ
ターン、３，５・・・絶縁層、７・・・ボンディング電
極、８・・・コンタクト電極、１０・・・集積回路チッ
プ、１２・・・細線。 代理人弁理士　住　１）俊　宗FIG. 1 is a plan view showing an example of a ceramic wiring board manufactured by the manufacturing method of the present invention, and FIG. 2 is a sectional view taken along line A-A. In the figure, 1...substrate, 2, 4.6... main wiring pattern, 3, 5... insulating layer, 7... bonding electrode, 8... contact electrode, 10... integrated circuit Chip, 12...thin line. Representative Patent Attorney Sumi 1) Sou Toshi

Claims (1)

【特許請求の範囲】[Claims] 基板上に銅、ニッケル等の卑金属によって主配線パター
ンを形成し、該主配線パターン上の所要部分に窒素雰囲
気中で焼成可能な金ペーストを塗布した後乾燥し、前記
主配線パターンを形成した卑金属と金の合金の融点以下
でかつ５００℃以上の温度範囲の窒素雰囲気中で焼成し
て前記主配線パターンの所要部に金の電極を形成するこ
とを特徴とするセラミック配線基板の製造方法。A main wiring pattern is formed on a substrate using a base metal such as copper or nickel, and a gold paste that can be fired in a nitrogen atmosphere is applied to required parts of the main wiring pattern and then dried to form the main wiring pattern. A method for manufacturing a ceramic wiring board, characterized in that gold electrodes are formed in required parts of the main wiring pattern by firing in a nitrogen atmosphere at a temperature below the melting point of an alloy of gold and gold and above 500°C.
JP16840282A 1982-09-29 1982-09-29 Manufacture of ceramic wiring board Granted JPS5958848A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16840282A JPS5958848A (en) 1982-09-29 1982-09-29 Manufacture of ceramic wiring board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16840282A JPS5958848A (en) 1982-09-29 1982-09-29 Manufacture of ceramic wiring board

Publications (2)

Publication Number Publication Date
JPS5958848A true JPS5958848A (en) 1984-04-04
JPS641057B2 JPS641057B2 (en) 1989-01-10

Family

ID=15867450

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16840282A Granted JPS5958848A (en) 1982-09-29 1982-09-29 Manufacture of ceramic wiring board

Country Status (1)

Country Link
JP (1) JPS5958848A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6020048A (en) * 1996-10-02 2000-02-01 Denso Corporation Thick film circuit board and method of forming wire bonding electrode thereon

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4940867A (en) * 1972-08-25 1974-04-17
JPS56114361A (en) * 1980-02-13 1981-09-08 Mitsubishi Electric Corp Semiconductor container
JPS57130443A (en) * 1981-02-06 1982-08-12 Nec Corp Substrate for hybrid integrated circuit

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4940867A (en) * 1972-08-25 1974-04-17
JPS56114361A (en) * 1980-02-13 1981-09-08 Mitsubishi Electric Corp Semiconductor container
JPS57130443A (en) * 1981-02-06 1982-08-12 Nec Corp Substrate for hybrid integrated circuit

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6020048A (en) * 1996-10-02 2000-02-01 Denso Corporation Thick film circuit board and method of forming wire bonding electrode thereon
DE19743737B4 (en) * 1996-10-02 2009-07-30 Denso Corporation, Kariya Method of forming a wire bonding electrode on a thick film board

Also Published As

Publication number Publication date
JPS641057B2 (en) 1989-01-10

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