JPH0344945A - Mounting of semiconductor device - Google Patents
Mounting of semiconductor deviceInfo
- Publication number
- JPH0344945A JPH0344945A JP1181133A JP18113389A JPH0344945A JP H0344945 A JPH0344945 A JP H0344945A JP 1181133 A JP1181133 A JP 1181133A JP 18113389 A JP18113389 A JP 18113389A JP H0344945 A JPH0344945 A JP H0344945A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor device
- electrode
- circuit board
- mounting
- alloy
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 44
- 239000000853 adhesive Substances 0.000 claims abstract description 25
- 230000001070 adhesive effect Effects 0.000 claims abstract description 25
- 238000000034 method Methods 0.000 claims abstract description 24
- 239000011231 conductive filler Substances 0.000 claims abstract description 17
- 229910001252 Pd alloy Inorganic materials 0.000 claims abstract description 9
- 229910052751 metal Inorganic materials 0.000 claims abstract description 8
- 239000002184 metal Substances 0.000 claims abstract description 8
- 239000000843 powder Substances 0.000 claims abstract description 8
- 229910045601 alloy Inorganic materials 0.000 claims abstract description 7
- 239000000956 alloy Substances 0.000 claims abstract description 7
- 150000002739 metals Chemical class 0.000 claims description 4
- 238000010438 heat treatment Methods 0.000 abstract description 5
- 230000008646 thermal stress Effects 0.000 abstract description 5
- 239000000758 substrate Substances 0.000 abstract description 4
- 229910000679 solder Inorganic materials 0.000 description 16
- 238000005476 soldering Methods 0.000 description 6
- 238000010586 diagram Methods 0.000 description 4
- 238000007796 conventional method Methods 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 238000007747 plating Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 239000000945 filler Substances 0.000 description 2
- 230000008018 melting Effects 0.000 description 2
- 238000002844 melting Methods 0.000 description 2
- 238000013508 migration Methods 0.000 description 2
- 230000005012 migration Effects 0.000 description 2
- 239000011295 pitch Substances 0.000 description 2
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 229910052804 chromium Inorganic materials 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 238000004377 microelectronic Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 230000035882 stress Effects 0.000 description 1
- 238000005486 sulfidation Methods 0.000 description 1
- 229920001187 thermosetting polymer Polymers 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/321—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by conductive adhesives
Landscapes
- Wire Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は、半導体装置と回路基板」二の端子電極部との
電気的接続に関するものであり、特に、導電性接着剤を
用いたフェースダウンボンディング法に係る半導体装置
の実装方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to electrical connection between a semiconductor device and a terminal electrode portion of a circuit board, and in particular, a face-down bonding method using a conductive adhesive. The present invention relates to a method for mounting a semiconductor device according to the present invention.
従来の技術
従来、電子部品の接続端子と回路基板上の回路パターン
端子との接続には半田付けがよく利用されていたが、近
年、例えばＩＣフラントパッケージ等の小型化と、接続
端子の増加により、接続端子間、いわゆるピッチ間隔が
次第に狭くなり、従来の半田付は技術で対処することが
次第に困難になって来た。Conventional technology In the past, soldering was often used to connect the connection terminals of electronic components and the circuit pattern terminals on the circuit board, but in recent years, soldering has become more popular due to the miniaturization of IC flat packages and the increase in the number of connection terminals. As the so-called pitch distance between connecting terminals becomes narrower and narrower, conventional soldering technology becomes increasingly difficult to overcome.
そこで、最近では裸の半導体装置を回路基板上の端子電
極部に直付けして実装面積の効率的使用を図ろうとする
方法が考案されてきた。Therefore, recently, a method has been devised in which a bare semiconductor device is directly attached to a terminal electrode portion on a circuit board in order to efficiently use the mounting area.
なかでも、半導体装置を回路基板上に接続するに際し、
半導体装置を下向きにして、あらかしめ半導体装置の電
極バンド上にＣｒ、ＣｕおよびＡｕの３層の金属舊着膜
部を形威し、更にレジストをかけて半田メンキや蒸着に
よって金属草着膜部上に形威し、余分なレジストと金属
薄着膜を除去して形成した半田バンプ電極を高温に加熱
して融着する方法が、接続後の機械的強度が強く、接続
が一括にできることなどから有効な方法であるとされて
いる。（例えば、工業調査会、１９８０年１月１５日発
行、日本マイクロエレクトロニクス協会編、ｆＩｃ化実
装技術Ｊ）
以下図面を参照しながら、上述した従来の半田バンプに
よる半導体装置の実装方法の一例について説明する。Among these, when connecting semiconductor devices to circuit boards,
With the semiconductor device facing downward, a three-layer metal film of Cr, Cu, and Au is formed on the electrode band of the semiconductor device, and then a resist is applied and the metal grass-deposited film is formed by soldering or vapor deposition. The method of heating and fusing solder bump electrodes, which are formed by removing excess resist and a thin metal film, has strong mechanical strength after connection and allows connections to be made all at once. It is said to be an effective method. (For example, Kogyo Kenkyukai, January 15, 1980, edited by Japan Microelectronics Association, fIc Mounting Technology J) An example of the above-mentioned conventional method for mounting semiconductor devices using solder bumps will be explained below with reference to the drawings. do.
第３図は従来の半田バンプによる半導体装置の実装方法
の概略説明図である。第３図において、７は半導体装置
であり、８は半田バンプ電極である。９は端子電極部で
あり、１０は回路基板である。FIG. 3 is a schematic explanatory diagram of a conventional method for mounting a semiconductor device using solder bumps. In FIG. 3, 7 is a semiconductor device, and 8 is a solder bump electrode. 9 is a terminal electrode portion, and 10 is a circuit board.
以上のように構成された半田バンプによる半導体装置の
実装方法について、以下その概略について説明する。A method for mounting a semiconductor device using solder bumps configured as described above will be briefly described below.
まず、半導体装置７のＡ２からなる電極バンド部にあら
かしめ半田バンプ電極８をメツキ等により形成しておき
、この半導体装置７をフェースダウンで回路基板１０の
端子電極部９に位置合せを行った後、２００〜３００
’Ｃの高温に加熱して半田バンプ電極８を溶融し、回路
基板１０の端子電極部９に融着させることによって半導
体装置の実装を行うものである。First, solder bump electrodes 8 were formed on the electrode band portion of A2 of the semiconductor device 7 by plating or the like, and the semiconductor device 7 was aligned face down to the terminal electrode portion 9 of the circuit board 10. After, 200-300
The semiconductor device is mounted by heating the solder bump electrodes 8 to a high temperature of 'C' and melting the solder bump electrodes 8 and fusing them to the terminal electrode portions 9 of the circuit board 10.
発明が解決しようとする課題
しかしながら上記のような半田バンプ′Ｒ，極による半
導体装置の実装方法においては、
（１）半田を溶融する際に高温に加熱する必要があり、
熱応力の影響を受は易い。Problems to be Solved by the Invention However, in the method of mounting a semiconductor device using solder bumps and poles as described above, (1) it is necessary to heat the solder to a high temperature when melting it;
Easily affected by thermal stress.
（２）半田による接続のために回路基板側の端子電極部
が半田接続可・能なものである必要があり、凡用性に欠
ける。(2) Since the connection is made by soldering, the terminal electrode portion on the circuit board side needs to be able to be connected by soldering, which results in a lack of versatility.
（３）半田バンプ電極を形成する半田が加熱溶融する際
に拡がり、隣接とショートが発生する危険がある。(3) When the solder forming the solder bump electrode is heated and melted, it spreads and there is a risk of short-circuiting with the adjacent electrode.
（４）熱膨張係数の異なるＳｌと回路基板とを硬度の高
い半田のみで接続しているため、熱応力に対して非常に
脆い。(4) Since the circuit board and the SI having different coefficients of thermal expansion are connected only by hard solder, the circuit board is extremely fragile against thermal stress.
などといった課題を有していた。There were issues such as these.
本発明は上記の課題に鑑みでなされたものであり、その
目的とする所は、半導体装置と回路基板とを経時変化の
ない信頼性の良い電気的な接続を行うことのできる半導
体装置の実装方法を提供するものである。The present invention has been made in view of the above-mentioned problems, and its purpose is to provide a mounting method for a semiconductor device that can provide a reliable electrical connection between a semiconductor device and a circuit board without deterioration over time. The present invention provides a method.
課題を解決するための手段
本発明は上記の課題を解決するため、半導体装置の回路
基板上の端子電極部への実装構造において、半導体装置
の電極パッド部上にバンプ電極を備え、該バンプ電極を
導電フィラーとして２種類以上の金属の合金からなるも
のを含む導電性接着剤を介して回路基板上の端子電極部
に電気的に接続することを特徴として、信頼性の高い半
導体装置の電気的接続を実現しようとするものである。Means for Solving the Problems In order to solve the above problems, the present invention provides a structure for mounting a semiconductor device on a terminal electrode portion on a circuit board, in which a bump electrode is provided on an electrode pad portion of the semiconductor device, and the bump electrode is mounted on a terminal electrode portion of a circuit board. It is characterized in that it is electrically connected to a terminal electrode part on a circuit board through a conductive adhesive containing an alloy of two or more metals as a conductive filler. This is an attempt to realize connectivity.
作用
本発明は上記した方法によって、半導体装置の電極パッ
ド部にあらかしめ形成したバンプ電極を導電フィラーと
して合金からなる導電性接着剤を介して回路基板上の端
子電極に接続することにより、応力に対して安定で、か
つ、経時変化がなく信頼性の高い半導体装置の電気的な
接続が実現できる。Effect The present invention uses the method described above to connect bump electrodes formed on the electrode pads of semiconductor devices to terminal electrodes on a circuit board via a conductive adhesive made of an alloy as a conductive filler. In contrast, it is possible to realize electrical connections of semiconductor devices that are stable, do not change over time, and are highly reliable.
実施例
以下、本発明の一実施例の半導体装置の実装方法につい
て、図面を参照しながら説明する。EXAMPLE Hereinafter, a method for mounting a semiconductor device according to an example of the present invention will be described with reference to the drawings.
第１図は本発明の一実施例における半導体装置の実装方
法による接続部の拡大図であり、第２図は、本発明の一
実施例における半導体装置の実装方法の概略説明図であ
る。FIG. 1 is an enlarged view of a connection portion according to a method for mounting a semiconductor device according to an embodiment of the present invention, and FIG. 2 is a schematic explanatory diagram of a method for mounting a semiconductor device according to an embodiment of the present invention.
第１図および第２図において、１は半導体装置であり、
２は電極パッド部である。３はＡｕからなるバンプ電極
であり、４はＡｇ−Ｐｄ合金の微粉を導電フィラーとす
る導電性接着剤である。５は端子電極部であり、６は回
路基板である。In FIG. 1 and FIG. 2, 1 is a semiconductor device,
2 is an electrode pad section. 3 is a bump electrode made of Au, and 4 is a conductive adhesive containing Ag-Pd alloy fine powder as a conductive filler. 5 is a terminal electrode portion, and 6 is a circuit board.
以上のように構成された半導体装置の実装方法について
、以下図面を用いて説明する。A method for mounting a semiconductor device configured as described above will be described below with reference to the drawings.
まず、半導体装置１の電極パッド部２上にあらかしめメ
ツキ等によりバンプ電極３を形成しておき、このバンプ
電極３に転写や印刷によってＡｇ−Ｐｄ合金の微粉を導
電フィラーとする導電性接着剤４を形成する。First, a bump electrode 3 is formed on the electrode pad portion 2 of the semiconductor device 1 by rough plating or the like, and a conductive adhesive containing Ag-Pd alloy fine powder as a conductive filler is applied to the bump electrode 3 by transfer or printing. form 4.
その後、この半導体装置１をフェースダウンで回路基板
６の端子電極部５に位置合せを行い、回路基板６上に半
導体装置１をマウントした後、加熱により導電性接着剤
４を硬化させることによって、第１図および第２図に示
す様に、半導体装置１がバンプ電極３およびＡｇ−ｐｄ
合金の微粉を導電フィラーとする導電性接着剤４を介し
て回路基板６の端子電極５に電気的に接続される。After that, this semiconductor device 1 is aligned face-down with the terminal electrode part 5 of the circuit board 6, and after mounting the semiconductor device 1 on the circuit board 6, the conductive adhesive 4 is cured by heating. As shown in FIGS. 1 and 2, a semiconductor device 1 has a bump electrode 3 and an Ag-pd
It is electrically connected to a terminal electrode 5 of a circuit board 6 via a conductive adhesive 4 containing alloy fine powder as a conductive filler.
このとき、半導体装置１の回路基板６への接続に導電性
接着剤４を用いているため、半導体素子１を構成するＳ
ｉ基板と回路基板６を構成するたとえばアルミナ基板や
ガラス基板との熱膨張係数の差から起因する熱応力を緩
和することができ、接続部の安定性が向上できる。At this time, since the conductive adhesive 4 is used to connect the semiconductor device 1 to the circuit board 6, S
Thermal stress caused by the difference in thermal expansion coefficient between the i-substrate and the alumina substrate or glass substrate constituting the circuit board 6, for example, can be alleviated, and the stability of the connection portion can be improved.
また、導電性接着剤４の硬化のための加熱は、従来例の
半田バンプによる接続に比べて低温で行えるため、熱硬
化時の熱応力による影響を軽減することができ、極めて
安定な接続が得られる。In addition, since the heating for curing the conductive adhesive 4 can be performed at a lower temperature than in the conventional connection using solder bumps, the influence of thermal stress during thermosetting can be reduced, resulting in an extremely stable connection. can get.
さらに、バンプ電極３と回路基板６の端子電極部５の電
気的接続は導電性接着剤４による接着によって行うため
、回路基板６の端子電極部５の材質は配線材料であれば
いかなるものでもよい。Further, since the electrical connection between the bump electrode 3 and the terminal electrode section 5 of the circuit board 6 is performed by adhesion using the conductive adhesive 4, the material of the terminal electrode section 5 of the circuit board 6 may be any wiring material. .
しかも、導電性接着剤４の導電フィラーとしてＡｇ−Ｐ
ｄ合金の微粉を用いるため、熱的にも安定であり、経時
変化もなく、従来のＡｇフィラーに見られるような酸化
、硫化やヨウ化等による劣化がない。Moreover, Ag-P is used as the conductive filler of the conductive adhesive 4.
Since fine powder of d alloy is used, it is thermally stable, does not change over time, and does not deteriorate due to oxidation, sulfidation, iodization, etc. as seen in conventional Ag fillers.
また、微小間隔に電界を加える所にＡｇフィラーからな
る導電性接着剤を用いた場合には、高温高湿下において
マイグレーション（Ａｇの移行）が発生して信頼性が低
下するが、本発明においては、Ａｇ−Ｐｄ合金を導電フ
ィラーとして用いるためイオン化することもなく安定で
ある。Furthermore, if a conductive adhesive made of Ag filler is used where an electric field is applied at minute intervals, migration (migration of Ag) will occur under high temperature and high humidity conditions, reducing reliability. Since it uses an Ag-Pd alloy as a conductive filler, it is stable without being ionized.
以上のようにして、半導体装置１と回路基板６を極めて
安定で信頼性よく、かつ、高密度に実装することが可能
となる。In the manner described above, it becomes possible to mount the semiconductor device 1 and the circuit board 6 extremely stably, reliably, and with high density.
なお、実施例においてバンプ電極３をＡｕよりなるもの
としたが、その材質はＡｕに限られるものでなく、たと
えば、Ｃｕなどの他の金属によって形成してもよい。In the embodiment, the bump electrode 3 is made of Au, but its material is not limited to Au, and may be made of other metals such as Cu.
また、バンプ電極３の形成は、従来のメツキによる形成
方法によるものに限られたものでなく、いかなる方法に
よる形成を行ったものでもよい。Further, the formation of the bump electrodes 3 is not limited to the conventional method of forming by plating, but may be formed by any method.
さらに、導電性接着剤４の導電フィラーとしては、Ａｇ
−Ｐｄ合金に限られたものでなく、２種類以上の金属の
合金からなる導電フィラーを用いることもできる。Furthermore, as the conductive filler of the conductive adhesive 4, Ag
The conductive filler is not limited to the -Pd alloy, and a conductive filler made of an alloy of two or more metals can also be used.
また、本実施例において導電性接着剤４をバンプ電極３
上に形成するとしたが、導電性接着剤４を回路基板６上
の端子電極部５側に印刷や転写１ｇなどを用いて形成し
てもよい。In addition, in this embodiment, the conductive adhesive 4 is applied to the bump electrode 3.
Although the conductive adhesive 4 is formed on the terminal electrode portion 5 side of the circuit board 6, the conductive adhesive 4 may be formed on the terminal electrode portion 5 side of the circuit board 6 using printing, transfer 1g, or the like.
発明の効果
以上に説明したように、本発明の半導体装置の実装方法
によれば、導電フィラーとしてＡｇ−Ｐｄ合金の微粉を
用いた導電性接着剤によって半導体装置の電極バッド部
上に形成したバンプ電極と回路基板上の端子電極とを接
着によって電気的な接続を行うため、経時変化のない、
かつ、応力に対して極めて安定な接続ができ、微細ピッ
チでの接続においても信頼性の高い接続が実現できるた
め、極めて実用上価値の高いものである。Effects of the Invention As explained above, according to the semiconductor device mounting method of the present invention, bumps are formed on the electrode pads of a semiconductor device using a conductive adhesive using Ag-Pd alloy fine powder as a conductive filler. Electrical connection is made between the electrode and the terminal electrode on the circuit board by adhesive, so there is no change over time.
In addition, it is extremely valuable in practical terms because it allows extremely stable connections against stress and allows for highly reliable connections even at fine pitches.
第１図は本発明の一実施例における半導体装置の実装方
法による接続部の拡大図、第２図は、本発明の一実施例
における半導体装置の実装方法の概略説明図、第３図は
従来の半田ハンプによる半導体装置の実装方法の概略説
明図である。
１．７・・・・・・半導体装置、２・・・・・・電極パ
ッド部、３・・・・・・バンプ電極、４・・・・・・Ａ
ｇ−Ｐｄ合金を導電フィラーとする導電性接着剤、５，
９・・・・・端子電極部、６，１０・・・・・・回路基
板、８・・・・・・半田ハンプ電極。FIG. 1 is an enlarged view of a connection part according to a semiconductor device mounting method according to an embodiment of the present invention, FIG. 2 is a schematic explanatory diagram of a semiconductor device mounting method according to an embodiment of the present invention, and FIG. 3 is a conventional FIG. 2 is a schematic explanatory diagram of a method for mounting a semiconductor device using a solder hump. 1.7...Semiconductor device, 2...Electrode pad portion, 3...Bump electrode, 4...A
Conductive adhesive containing g-Pd alloy as conductive filler, 5,
9...Terminal electrode part, 6,10...Circuit board, 8...Solder hump electrode.
Claims (3)
法において、半導体装置の電極パッド部上にバンプ電極
を備え、前記バンプ電極を導電フィラーとして２種類以
上の金属の合金からなるものを含む導電性接着剤を介し
て回路基板上の端子電極部に電気的に接続することを特
徴とする半導体装置の実装方法。(1) In a method for mounting a semiconductor device on a terminal electrode portion on a circuit board, a bump electrode is provided on the electrode pad portion of the semiconductor device, and the bump electrode is made of an alloy of two or more metals as a conductive filler. 1. A method for mounting a semiconductor device, comprising electrically connecting to a terminal electrode portion on a circuit board via a conductive adhesive.
ｇ−Ｐｄ合金の微粉を用いることを特徴とする請求項（
１）記載の半導体装置の実装方法。(2) As a conductive filler contained in a conductive adhesive, A
Claim characterized in that fine powder of g-Pd alloy is used (
1) Method for mounting the semiconductor device described above.
求項（１）記載の半導体装置の実装方法。(3) The method for mounting a semiconductor device according to claim (1), wherein the bump electrode is made of Au.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1181133A JPH0744199B2 (en) | 1989-07-12 | 1989-07-12 | Semiconductor device mounting body and mounting method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1181133A JPH0744199B2 (en) | 1989-07-12 | 1989-07-12 | Semiconductor device mounting body and mounting method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0344945A true JPH0344945A (en) | 1991-02-26 |
| JPH0744199B2 JPH0744199B2 (en) | 1995-05-15 |
Family
ID=16095456
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1181133A Expired - Lifetime JPH0744199B2 (en) | 1989-07-12 | 1989-07-12 | Semiconductor device mounting body and mounting method thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0744199B2 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100287393B1 (en) * | 1997-03-12 | 2001-04-16 | 포만 제프리 엘 | Substrate structure and method for improving attachment reliability of semiconductor chips and modules |
| EP1187210A3 (en) * | 2000-09-07 | 2005-03-02 | Matsushita Electric Industrial Co., Ltd. | Semiconductor device |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4946673A (en) * | 1972-09-07 | 1974-05-04 | ||
| JPS6289177U (en) * | 1985-11-22 | 1987-06-08 |
-
1989
- 1989-07-12 JP JP1181133A patent/JPH0744199B2/en not_active Expired - Lifetime
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4946673A (en) * | 1972-09-07 | 1974-05-04 | ||
| JPS6289177U (en) * | 1985-11-22 | 1987-06-08 |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100287393B1 (en) * | 1997-03-12 | 2001-04-16 | 포만 제프리 엘 | Substrate structure and method for improving attachment reliability of semiconductor chips and modules |
| EP1187210A3 (en) * | 2000-09-07 | 2005-03-02 | Matsushita Electric Industrial Co., Ltd. | Semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0744199B2 (en) | 1995-05-15 |
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