JPH09102517A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH09102517A JPH09102517A JP7258669A JP25866995A JPH09102517A JP H09102517 A JPH09102517 A JP H09102517A JP 7258669 A JP7258669 A JP 7258669A JP 25866995 A JP25866995 A JP 25866995A JP H09102517 A JPH09102517 A JP H09102517A
- Authority
- JP
- Japan
- Prior art keywords
- electrode pad
- solder
- semiconductor element
- elliptical shape
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/061—Disposition
- H01L2224/0612—Layout
- H01L2224/0614—Circular array, i.e. array with radial symmetry
- H01L2224/06141—Circular array, i.e. array with radial symmetry being uniform, i.e. having a uniform pitch across the array
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/061—Disposition
- H01L2224/0612—Layout
- H01L2224/0614—Circular array, i.e. array with radial symmetry
- H01L2224/06144—Circular array, i.e. array with radial symmetry covering only portions of the surface to be connected
- H01L2224/06145—Covering only the peripheral area of the surface to be connected, i.e. peripheral arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/1301—Shape
- H01L2224/13012—Shape in top view
- H01L2224/13014—Shape in top view being circular or elliptic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
- H01L2224/141—Disposition
- H01L2224/1412—Layout
- H01L2224/1414—Circular array, i.e. array with radial symmetry
- H01L2224/14141—Circular array, i.e. array with radial symmetry being uniform, i.e. having a uniform pitch across the array
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
- H01L2224/141—Disposition
- H01L2224/1412—Layout
- H01L2224/1414—Circular array, i.e. array with radial symmetry
- H01L2224/14143—Circular array, i.e. array with radial symmetry with a staggered arrangement, e.g. depopulated array
- H01L2224/14145—Covering only the peripheral area of the surface to be connected, i.e. peripheral arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/3457—Solder materials or compositions; Methods of application thereof
- H05K3/3478—Applying solder preforms; Transferring prefabricated solder patterns
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、半導体装置に関
し、特にバンプを有する半導体装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a semiconductor device having bumps.
【０００２】[0002]
【従来の技術】従来、共晶半田等の金属ロー材でなるバ
ンプ状の外部端子（以下、半田バンプという）を有する
構造の半導体装置では、半導体装置基体であるフレキシ
ブルな配線フィルムの電極パッドに金属ロー材を仮付け
し、その後金属ロー材の融点以上の温度で金属ロー材を
リフローし、半田バンプを形成し接続していた。2. Description of the Related Art Conventionally, in a semiconductor device having a structure having a bump-shaped external terminal (hereinafter referred to as a solder bump) made of a metal brazing material such as eutectic solder, an electrode pad of a flexible wiring film, which is a semiconductor device base, is used. The metal brazing material is temporarily attached, and then the metal brazing material is reflowed at a temperature equal to or higher than the melting point of the metal brazing material to form solder bumps for connection.
【０００３】従来の配線フィルム１は、図４（ｂ）に示
すように銅配線の両面をポリイミドフィルムで電気的絶
縁にした構造となり、半導体素子５と接続された銅配線
に外部端子を形成するため、カバーポリイミド４にエッ
チングにより図４（ａ）に示すような円形の開孔部を開
け、電極パッド２を設けていた。As shown in FIG. 4B, the conventional wiring film 1 has a structure in which both sides of a copper wiring are electrically insulated by a polyimide film, and external terminals are formed on the copper wiring connected to the semiconductor element 5. Therefore, the electrode opening 2 is provided by forming a circular opening in the cover polyimide 4 by etching as shown in FIG.
【０００４】外部端子用の半田バンプ３を形成するため
には、配線フィルム１の表面にロジン系フラックス等の
比較的粘着力の高いフラックスをディスペンサ、スピン
コートあるいは印刷等により塗布し、半田を球状にした
半田ボールを真空ピンセットを用いて電極パッドに搭載
する。その後、加熱処理を行い、半田ボールを電極パッ
ドに接続し、球状の半田バンプ３を形成する。また、微
細な半田バンプを形成するため、リボン状の半田からポ
ンチ、ダイスを用いて打ち抜いた円筒状の半田片をフラ
ックスの粘着力により電極パッドに仮付けし、加熱処理
を行い半田を電極パッドに接続し、球状の半田バンプ３
を形成する方法をとる。In order to form the solder bumps 3 for external terminals, a flux having a relatively high adhesive force such as rosin flux is applied to the surface of the wiring film 1 by a dispenser, spin coating, printing or the like, and the solder is spherically shaped. The solder balls thus prepared are mounted on the electrode pads by using vacuum tweezers. After that, heat treatment is performed to connect the solder balls to the electrode pads to form the spherical solder bumps 3. In addition, in order to form fine solder bumps, a cylindrical solder piece punched from ribbon-shaped solder using a punch or die is temporarily attached to the electrode pad by the adhesive force of the flux, and heat treatment is performed to solder the electrode pad. Connect to the spherical solder bump 3
Take the method of forming.
【０００５】[0005]
【発明が解決しようとする課題】この従来の半田バンプ
では、図５に示されるように、プリント基板に実装した
時、半導体素子５とプリント基板８の熱膨張の差によ
り、半田バンプ３の根元に応力が集中するためクラック
１０が発生するという問題点があった。In this conventional solder bump, as shown in FIG. 5, when mounted on a printed circuit board, the root of the solder bump 3 is affected by a difference in thermal expansion between the semiconductor element 5 and the printed circuit board 8. There is a problem that the crack 10 is generated because the stress is concentrated on the surface.
【０００６】この問題を解決する対策として、半田バン
プの接合面積を大きくし、強度を上げることが考えられ
るが、電子部品の高密度化に伴い、微細ピッチの電極に
対応することが要求され、配線パターン等の設計上電極
パッド径を単に大きくすることが困難となっている。As a measure to solve this problem, it is conceivable to increase the bonding area of the solder bumps to increase the strength. However, as the density of electronic parts increases, it is required to cope with electrodes having a fine pitch. Due to the design of the wiring pattern and the like, it is difficult to simply increase the electrode pad diameter.
【０００７】また、半田バンプのクラック対策をして、
特開平３−２２２３３４号公報に記載されているよう
に、半導体チップ等の電気部品表面に形成されたパッド
上に、半田に対して融点が高くかつヤング率が小さい材
料による導電層が所定のメタル層を挟んで形成され、そ
の導電層上にバンプ上の半田を形成する方法が考えられ
ている。Also, as a measure against cracking of solder bumps,
As described in Japanese Patent Application Laid-Open No. 3-222334, on a pad formed on the surface of an electric component such as a semiconductor chip, a conductive layer made of a material having a high melting point and a small Young's modulus with respect to solder is a predetermined metal. A method of forming a solder on a bump on the conductive layer is considered.
【０００８】しかし、この方法は、フリップチップのバ
ンプ構造に関するものであり、配線フィルムに適用する
のは困難であり、また、製造工程数が増えるため、コス
トが高くなってしまう。However, this method relates to the flip chip bump structure and is difficult to apply to a wiring film, and the number of manufacturing steps increases, resulting in high cost.
【０００９】本発明の目的は、低コストで実装後の半田
バンプに発生するクラックを容易に防止する半導体装置
を提供することにある。An object of the present invention is to provide a semiconductor device which can easily prevent cracks occurring in solder bumps after mounting at low cost.
【００１０】[0010]
【課題を解決するための手段】本発明による半導体装置
は、配線パターンの両面が絶縁膜に覆われた配線フィル
ム、上記配線フィルムの一主表面に搭載された半導体素
子、上記配線フィルムの他主表面の上記絶縁膜の一部を
切り欠いて上記配線パターンを露出する電極パッド、及
び上記電極パッドに設けられたバンプを有する半導体装
置であって、上記電極パッドは上記半導体素子の中心方
向に長い楕円形状であることを特徴とする。A semiconductor device according to the present invention is a wiring film in which both sides of a wiring pattern are covered with an insulating film, a semiconductor element mounted on one main surface of the wiring film, and another main portion of the wiring film. A semiconductor device having an electrode pad exposing a part of the insulating film on the surface to expose the wiring pattern, and a bump provided on the electrode pad, wherein the electrode pad is long in the center direction of the semiconductor element. It is characterized by having an elliptical shape.
【００１１】好ましくは、上記電極パッドは互いに離間
して環状に複数個設けられ、上記バンプが上記複数個の
電極パッドに対してそれぞれ設けられていることを特徴
とする。Preferably, a plurality of the electrode pads are provided in an annular shape spaced apart from each other, and the bumps are provided for the plurality of electrode pads, respectively.
【００１２】[0012]
【作用】半導体素子の中心方向に長い楕円形状の電極パ
ッドが、この電極パッドに形成されたバンプの接合面積
を半導体素子の膨張方向に大きくするので、プリント基
板実装時に、半導体素子とプリント基板との熱膨張率の
差によって発生する応力を緩和することができ、従来と
同様のコストでバンプのクラック発生を低減することが
できる。The elliptical electrode pad elongated in the center direction of the semiconductor element increases the bonding area of the bump formed on the electrode pad in the expansion direction of the semiconductor element. The stress generated due to the difference in the coefficient of thermal expansion can be relaxed, and the occurrence of cracks in the bumps can be reduced at the same cost as the conventional one.
【００１３】[0013]
【発明の実施の形態】次に、本発明の上記及びその他の
目的、特徴を明瞭にすべく本発明について図面を参照し
て説明する。BEST MODE FOR CARRYING OUT THE INVENTION Next, the present invention will be described with reference to the drawings in order to clarify the above and other objects and features of the present invention.
【００１４】図１は、本発明の実施形態の一例を示す平
面図である。図２（ａ）は、図１に示される実施形態の
うち１つの電極パッド２部分の部分拡大図である。図２
（ｂ）は、図２（ａ）のＡ−Ａ線に沿った断面図であ
る。FIG. 1 is a plan view showing an example of an embodiment of the present invention. FIG. 2A is a partially enlarged view of one electrode pad 2 portion of the embodiment shown in FIG. FIG.
2B is a sectional view taken along the line AA of FIG.
【００１５】本発明の半導体装置は、図２（ｂ）に示す
ように、半導体素子５と配線フィルム１と半田バンプ３
とを有する半導体装置であって、半導体素子５は、配線
フィルム１の配線パターンと電気的に接続されて、配線
フィルム１に搭載されたものであり、配線フィルム１
は、配線パターンの両面が絶縁膜により絶縁されたもの
であって、複数の半田バンプ３を有し、半田バンプ３
は、絶縁膜（カバーポリイミド４）の一部を切り欠いて
配線パターンを露出して形成された複数の電極パッド２
に設けられたものである。電極パッド２は、それぞれ図
１、図２（ａ）に示すように半導体素子の略中心方向に
長い楕円形状であり、互いに離間して環状に配置されて
いる。As shown in FIG. 2B, the semiconductor device of the present invention has a semiconductor element 5, a wiring film 1, and solder bumps 3.
And a semiconductor element 5 is electrically connected to a wiring pattern of the wiring film 1 and mounted on the wiring film 1.
Is a wiring pattern whose both surfaces are insulated by insulating films, and has a plurality of solder bumps 3.
Is a plurality of electrode pads 2 formed by cutting out a part of the insulating film (cover polyimide 4) to expose the wiring pattern.
It is provided in. As shown in FIGS. 1 and 2A, the electrode pads 2 have an elliptical shape that is long in the approximate center direction of the semiconductor element, and are arranged in an annular shape so as to be separated from each other.
【００１６】図３は、本実施形態の半田バンプの形成方
法を示す拡大図である。FIG. 3 is an enlarged view showing the solder bump forming method of this embodiment.
【００１７】外部端子用の半田バンプ３を形成するた
め、カバーポリイミド膜の一部を切り欠いて楕円形状の
電極パッド２を形成する。さらに配線フィルム１の表面
にロジン系フラックス等の比較的粘着力の高いフラック
ス７をスピンコートあるいは印刷等により塗布し、リボ
ン状の半田からポンチ、ダイスを用いて打ち抜いた半田
片６をフラックス７の粘着力により楕円形状の電極パッ
ド２に仮付けする。その後、図３（ｃ）に示すように加
熱処理を行い、半田を電極パッド２に接続し、楕円球状
の半田バンプ３を形成する。In order to form the solder bumps 3 for external terminals, a part of the cover polyimide film is cut out to form the elliptical electrode pad 2. Further, a flux 7 having a relatively high adhesive strength such as a rosin flux is applied to the surface of the wiring film 1 by spin coating or printing, and a solder piece 6 punched from a ribbon-shaped solder with a punch or a die is used as a flux 7. It is temporarily attached to the elliptical electrode pad 2 by the adhesive force. Then, as shown in FIG. 3C, heat treatment is performed to connect the solder to the electrode pads 2 to form the elliptic spherical solder bumps 3.
【００１８】本実施例での半田片６の大きさは直径１５
０μｍ、厚さ１００μｍ、電極パッド２の大きさは短軸
方向８０μｍ、長軸方向１６０μｍである。The size of the solder piece 6 in this embodiment is 15 mm in diameter.
The thickness of the electrode pad 2 is 0 μm, the thickness is 100 μm, and the size of the electrode pad 2 is 80 μm in the minor axis direction and 160 μm in the major axis direction.
【００１９】この実施形態の半導体装置を厚さ１．５ｍ
ｍのガラス・エポキシ基板に実装し、温度サイクル試験
（−４０〜１２５℃）を行ったところ、従来１００サイ
クル程度から半田バンプと電極パッドの界面付近にクラ
ックが生じ不良となっていた（不良数１２／３０）が、
３００サイクルまで不良が発生しなくなった。The semiconductor device of this embodiment has a thickness of 1.5 m.
When it was mounted on a glass / epoxy board of m and subjected to a temperature cycle test (-40 to 125 ° C), cracks were generated around the interface between the solder bump and the electrode pad from about 100 cycles in the past, resulting in defects (number of defects). 12/30),
No defects occurred until 300 cycles.
【００２０】[0020]
【発明の効果】以上説明したように本発明は、半田バン
プの接合面積を半導体素子の膨張方向に大きくすること
により、せん断力に対して接合面積が大きくなるので、
単位面積あたりのせん断力は小さくなる。よって、プリ
ント基板に実装した時に、半導体素子とプリント基板の
熱膨張率の差により発生する応力を緩和することがで
き、半導体素子とプリント基板との接合強度を上げるこ
とができるので、半田バンプのクラック発生が減少し、
接続の信頼性が高い実装が実現できる。As described above, according to the present invention, since the bonding area of the solder bump is increased in the expansion direction of the semiconductor element, the bonding area is increased with respect to the shearing force.
The shearing force per unit area becomes smaller. Therefore, when mounted on a printed circuit board, the stress generated due to the difference in coefficient of thermal expansion between the semiconductor element and the printed circuit board can be relieved, and the bonding strength between the semiconductor element and the printed circuit board can be increased. The number of cracks is reduced,
A highly reliable implementation can be realized.
【図１】本発明の実施形態の一例を示す平面図。FIG. 1 is a plan view showing an example of an embodiment of the present invention.
【図２】図１に示される半導体装置の１つの電極パッド
部分の部分拡大図及びＡ−Ａ線に沿った部分断面図。2 is a partial enlarged view of one electrode pad portion of the semiconductor device shown in FIG. 1 and a partial cross-sectional view taken along the line AA.
【図３】本発明の半田バンプ製造方法を説明するための
部分拡大図及び部分断面図。FIG. 3 is a partial enlarged view and a partial cross-sectional view for explaining the solder bump manufacturing method of the present invention.
【図４】従来例の部分平面図及び部分断面図。FIG. 4 is a partial plan view and a partial cross-sectional view of a conventional example.
【図５】プリント基板に実装された状態の従来例の部分
断面図。FIG. 5 is a partial cross-sectional view of a conventional example mounted on a printed circuit board.
１ 配線フィルム ２ 電極パッド ３ 半田バンプ ４ カバーポリイミド ５ 半導体素子 ６ 半田片 ７ フラックス ８ プリント基板 ９ パッド １０ クラック 1 Wiring Film 2 Electrode Pad 3 Solder Bump 4 Cover Polyimide 5 Semiconductor Element 6 Solder Piece 7 Flux 8 Printed Circuit Board 9 Pad 10 Crack
Claims (3)
配線フィルム、前記配線フィルムの一主表面に搭載され
た半導体素子、前記配線フィルムの他主表面の前記絶縁
膜の一部を切り欠いて前記配線パターンを露出する電極
パッド、及び前記電極パッドに設けられたバンプを有す
る半導体装置であって、前記電極パッドは前記半導体素
子の中心方向に長い楕円形状であることを特徴とする半
導体装置。1. A wiring film in which both surfaces of a wiring pattern are covered with an insulating film, a semiconductor element mounted on one main surface of the wiring film, and a part of the insulating film on the other main surface of the wiring film is cut out. A semiconductor device having an electrode pad exposing the wiring pattern and a bump provided on the electrode pad, wherein the electrode pad has an elliptical shape elongated in the center direction of the semiconductor element. .
複数個設けられ、前記バンプが前記複数個の電極パッド
に対してそれぞれ設けられていることを特徴とする請求
項１記載の半導体装置。2. The semiconductor device according to claim 1, wherein a plurality of the electrode pads are provided in an annular shape so as to be separated from each other, and the bumps are provided for the plurality of electrode pads, respectively.
を特徴とする請求項１又は請求項２記載の半導体装置。3. The semiconductor device according to claim 1, wherein the bump is made of an alloy of lead and tin.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7258669A JPH09102517A (en) | 1995-10-05 | 1995-10-05 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7258669A JPH09102517A (en) | 1995-10-05 | 1995-10-05 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH09102517A true JPH09102517A (en) | 1997-04-15 |
Family
ID=17323460
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7258669A Pending JPH09102517A (en) | 1995-10-05 | 1995-10-05 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH09102517A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006513648A (en) * | 2003-01-20 | 2006-04-20 | エプコス アクチエンゲゼルシャフト | Small board surface electrical components |
| US7078629B2 (en) | 2003-10-22 | 2006-07-18 | International Business Machines Corporation | Multilayer wiring board |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6038839A (en) * | 1983-08-12 | 1985-02-28 | Hitachi Ltd | Flip-chip type semiconductor device |
| JPH03200343A (en) * | 1989-12-27 | 1991-09-02 | Tanaka Denshi Kogyo Kk | Method of forming solder bump |
| JPH05218042A (en) * | 1992-02-05 | 1993-08-27 | Toshiba Corp | Semiconductor device |
-
1995
- 1995-10-05 JP JP7258669A patent/JPH09102517A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6038839A (en) * | 1983-08-12 | 1985-02-28 | Hitachi Ltd | Flip-chip type semiconductor device |
| JPH03200343A (en) * | 1989-12-27 | 1991-09-02 | Tanaka Denshi Kogyo Kk | Method of forming solder bump |
| JPH05218042A (en) * | 1992-02-05 | 1993-08-27 | Toshiba Corp | Semiconductor device |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006513648A (en) * | 2003-01-20 | 2006-04-20 | エプコス アクチエンゲゼルシャフト | Small board surface electrical components |
| US8022556B2 (en) | 2003-01-20 | 2011-09-20 | Epcos Ag | Electrical component having a reduced substrate area |
| US7078629B2 (en) | 2003-10-22 | 2006-07-18 | International Business Machines Corporation | Multilayer wiring board |
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