JPH05218042A - Semiconductor device - Google Patents

Abstract

PURPOSE:To avoid damage, rupture, etc., of an electrode bump due to a later thermal stress even when a flip chip is connected to a mounting board having different thermal expansion coefficients by disposing a bonding pad on an insulating layer of a semiconductor device region and providing the bump thereon. CONSTITUTION:The semiconductor device comprises a semiconductor substrate 9', a semiconductor element region 9a formed on its main surface, first bonding pads 8 arranged on the outer periphery of the region 9a, and an insulating film 10 covering the surface of the region 9a. Further, the device comprises second bonding pads 11 formed inside from the pads 8 on the film 10, bump electrodes 13 provided on the surface of the pads 11, and wirings 12 connected at one ends to the pads 8 and at the other to the pads 11. The area of the pad 11 is formed larger than that of the pad 8.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a semiconductor device having bump electrodes provided on a semiconductor element region of the semiconductor device.

[0002]

2. Description of the Related Art As is well known, semiconductor devices are in the direction of high integration, and on the other hand, highly integrated semiconductor devices are mounted at high density to make circuits compact and increase the capacity of functions. Is also planned. For example, in a memory card equipped with a semiconductor memory device, an attempt has been made to increase the semiconductor memory capacity and simultaneously mount the semiconductor device on a substrate at a high density. When a packaged semiconductor element (device) is used as a high-density mounting means for this semiconductor device, surface mount components are used because of the card thickness limitation required by the product standard.

However, in the case of the above-mentioned surface mount component, it can be roughly classified into a gull wing type and a J lead type for the purpose of higher density mounting, depending on the constitution of the outer lead.
There is a limit to the high density in that package parts are used.
Therefore, a flip chip connection method is used, which enables higher density than surface mounting technology. In other words, according to the flip-chip connection method (flip-chip mounting technology), when mounting a semiconductor device (semiconductor element) on the substrate surface, the mounting area is about 1/2 to 1/3 of that when using package components. It can be implemented with.

The flip-chip connection to the mounting board is performed as shown in cross sections in FIGS. 14, 15 and 16. 14 and 15 are enlarged views showing the structure of the flip chip connection, in which 1 is a bonding pad which is pre-disposed on the surface of the semiconductor device 2 from the passivation film 3 and 4 is an exposed surface of the bonding pad 1. The barrier metal layer 5 formed on the surface of the barrier metal layer 4 is formed by electroplating, dipping,
The bump electrode is a straight wall-shaped or drum-shaped bump electrode made of solder formed by a vapor deposition method or the like. on the other hand,
Reference numeral 6 denotes a terminal electrode that is previously arranged on the surface of the mounting substrate (circuit board) 7 so as to be exposed from the passivation film 3'and 4'denotes a barrier metal layer formed on the exposed surface of the terminal electrode 6. Then, after the end face of the bump electrode 5 of the semiconductor device 2 is aligned and placed in contact with the barrier metal layer 4'of the mounting substrate 7, the bump electrode 5 is reflowed. Provide electrical and mechanical connections. FIG. 16 is a sectional view showing a structure when the semiconductor device 2 is flip-chip connected to the mounting substrate 7 as described above, and corresponds to the semiconductor element region 2a formed on the main surface of the semiconductor substrate 2 '. In the position corresponding to the surface of the bonding pad 1 arranged around the outer periphery of the semiconductor element region 2a, the surface of the mounting substrate 7 is connected through the bump-shaped bump electrodes 5. That is,
The connection (mounting) of the semiconductor device 2 to the mounting substrate 7 via the electrode bumps 5 is made outside the semiconductor element region 2a. Note that FIG. 17 is a plan view showing an arrangement state of the bonding pads 1 of the semiconductor device 2.

By the way, in the case of this type of flip-chip connection (mounting), the stress generated by the difference in the thermal expansion coefficient between the semiconductor device (semiconductor substrate) 2 and the mounting substrate 7 is concentrated on the bump electrode 5, and the bump There is a problem that the electrode 5 is easily damaged. That is, due to the thermal expansion of the mounting substrate 7 and the semiconductor device 2 flip-chip bonded (or mounted) to the mounting substrate 7, the semiconductor substrate 2 generates heat and expands with each other within the operating temperature range. Due to the difference in the coefficient of thermal expansion, thermal stress is intensively applied to the connection portions of the electrode bumps 5 involved in the connection integration. The way the thermal stress is applied increases as the distance between the electrode bumps 5 increases. In order to prevent the electrode bumps 5 from being damaged due to the difference in the thermal expansion coefficient, it has been attempted to fill the space between the mounted semiconductor device 2 and the surface of the mounting substrate 7 with resin. With this resin filling means, the inconvenience (fault) due to the difference in the thermal expansion coefficient is reduced to some extent, but it is not satisfactory in practice. In particular, the semiconductor device 2 and the mounting substrate 7
When the coefficient of thermal expansion is greatly different from that of the mounting substrate 7, stress concentrates on the interface between the mounting substrate 7 and the filling resin, and the electrode bumps 5 are likely to be broken. There is a problem in terms of sex. In this respect, for example, a silicon wafer is used as the mounting substrate 7, and the semiconductor device (semiconductor element) 2
Although it can be said that a means for arranging (Chip On Wafer) is preferable, there are problems in terms of complexity of manufacturing process and manufacturing cost.

[0006]

As described above, in the structure of a memory card, for example, if the semiconductor device is mounted by flip-chip mounting technology (connection technology), there are many advantages such as high-density mounting. However, there are problems in breakage of the electrode bumps 5 due to the difference in thermal expansion coefficient, functional reliability, and the like. In order to eliminate the damage of the electrode bumps 5, in other words, the occurrence of defective cutting at the bump connection portion, attempts have been made to make the structure of the electrode bumps 5 resistant to thermal stress. For example, a bump is formed in a laminated type with a polyimide resin film sandwiched (Technical Report of the Institute of Electronics, Information and Communication Engineers CPM-19 to 24 (1987),
Alternatively, it is known that the bumps are formed in a drum shape. However, when the electrode bumps are laminated as described above, the formation of a so-called bump sheet becomes complicated, which not only increases the cost but also increases the number of connection points due to the lamination, which leads to an electrical problem. There is also a problem with the reliability of the connection. Further, when the electrode bumps are formed in a drum shape, the distance between the semiconductor device 2 and the mounting substrate 7 is appropriately set with the electrode bumps 5 melted and once connected to the terminal electrodes 4'of the mounting substrate 7. In order to make the bumps have a drum-shape by separating them, it is said that if the separation is not properly performed according to the amount of solder forming the electrode bumps, connection failure may occur or a required drum-shape cannot be formed. There's a problem.

On the other hand, the flip-chip connection or mounting of the semiconductor device is so-called face-down mounting, and since the element region surface which generates heat due to the operation of the semiconductor device 2 faces the mounting substrate 7 surface, the amount of heat generation is semiconductor. There is also a problem that the function is likely to be accumulated in the device 2 and the function may be deteriorated or a failure may occur. Therefore, in the face-down mounted structure, for example, it is desirable to expose the outer peripheral surface of the semiconductor device 2 as much as possible to facilitate heat dissipation. As a measure against such heat dissipation, there is a means for disposing a heat dissipation fin on the back surface of the semiconductor device 2, but there is a disadvantage that the thinning is significantly impaired. Further, the electrode bump 5 has a two-layer structure in which a metal having good thermal conductivity such as Cu is used as a center and a solder layer is arranged on a peripheral surface of the metal, and a metal having a good thermal conductivity forming a central axis is formed. Although it has been attempted to dissipate heat by means of heat dissipation, it lacks reliability in terms of connection strength and electrical connectivity (increase in resistance, etc.).

The present invention has been made in consideration of the above circumstances, and even when flip-chip connection (mounting) is performed on a mounting substrate having a thermal expansion coefficient different from that of a semiconductor device, the subsequent thermal stress causes Damage at the electrode bumps,
An object of the present invention is to provide a semiconductor device in which breakage phenomenon and the like are completely avoided, excellent heat dissipation is exhibited, and highly reliable functions are retained and exhibited.

[0009]

The semiconductor device of the present invention comprises:
A semiconductor substrate; a semiconductor element region formed on a main surface of the semiconductor substrate; a first bonding pad arranged on the outer periphery of the semiconductor element region corresponding to each semiconductor element region; and a first bonding An insulating film that exposes the pad surface and covers at least the semiconductor element region surface; and a second bonding pad formed on the insulating film inside the first bonding pad corresponding to the first bonding pad. A bump electrode provided on the surface of the second bonding pad, and a wiring arranged in the insulating film region with one end connected to the first bonding pad and the other end connected to the second bonding pad. And the area of the second bonding pad is set to be larger than the area of the first bonding pad.

In the above structure, the number of the second bonding pads formed on the insulating film corresponds to the number of the first bonding pads, and the area inside the area where the first bonding pads are arranged. In addition, it is formed / arranged at an arbitrary pitch or position, but it is desirable that the shape / arrangement be a regular grid-like arrangement such as vertical and horizontal plural rows. In addition, in this lattice-shaped arrangement, it is preferable that the diagonal corners (re-peripheral corners) are excluded (the corners are the second bonding pad placement prohibited areas).

[0011]

In the semiconductor device according to the present invention, as shown in the cross-sectional view of the main part configuration example in FIG. 1, the required semiconductor element region 9a is located inside the region where the first bonding pad 8 is arranged. The exposed second bonding pad 11 is disposed on the insulating layer 10b on the formed region surface,
These are connected via the insulating layer 10b and the interlayer insulating layer 10a, for example, by a wiring 12 arranged in multiple layers. In other words, mounting face down on the mounting board 7
Since the electrode bumps 13 to be connected are arranged on the area surface of the semiconductor substrate 9'on which the semiconductor element area 9a is formed, the area surface (the area surface involved in the connection to the mounting board 7 surface ( The effective area required for connection is reduced. Therefore, since the effective thermal expansion applied to the semiconductor device 9 is also reduced, the stress applied to the electrode bumps 13 due to the difference in the thermal expansion coefficient between the mounting substrate 7 and the semiconductor device 9 is also reduced, and the reliability against the thermal stress is also reduced. Is improved. Moreover, in this configuration, heat generated in the semiconductor element 9a region of the semiconductor device 9 is easily dissipated to the mounting substrate 7 side through the electrode bumps 13 on the surface of the second bonding pad 11.

Further, the second bonding pad 11
Since the area of each is set to be larger than the area of the first bonding pad 8, the electrode bumps 13 can be formed to be relatively large, which facilitates alignment during flip connection (mounting). It can be achieved and the connection strength can be improved.

Further, the second bonding pad 11
, Is arranged in a lattice pattern excluding the corners on the diagonal line, it is mounted face down on the surface of the mounting substrate 7.
Upon connection, even if thermal cycle stress is applied to the mounting / connecting portion (connection portion of the electrode bump 13), the amount of displacement between the mounting substrate 7 and the semiconductor device 9 is maximized (hence, thermal stress is applied most). ) Since the electrode bumps 13 do not exist at the corners on the diagonal line, a substantially uniform stress is applied to the electrode bumps 13 as a whole, and the reliability of the connection portion is not impaired.

[0014]

Embodiments of the present invention will be described below with reference to FIGS. 2 to 12 and 13.

FIG. 2 is a plan view showing a structural example of a semiconductor device 9 according to the present invention. 9'is a semiconductor substrate, 9a is a semiconductor element region formed on the surface of the semiconductor substrate 9 ', and 8 is a semiconductor element region. A first bonding pad, which is arranged outside the region where the semiconductor element region 9a is formed on the surface of the semiconductor substrate 9 ', 13 is an insulating layer (not shown) having wirings 12 on the surface of the semiconductor element region 9a. The electrode bumps are laminated and arranged on the surface of the second bonding pad 11 provided on the surface of the electrode bump. As can be seen from this figure, the first bonding pads 8 correspond to the second bonding pads 11, respectively, and are formed by the wirings 12 arranged in the insulating layer in a single-layer or multi-layer insulation manner. It is configured to be electrically connected.

Next, with respect to a method of manufacturing the semiconductor device 9 having such a structure, FIG.
This will be described with reference to FIG.

First, a semiconductor substrate 9'on which a required semiconductor region 9a is formed on a predetermined surface is prepared, and required wiring for connecting each semiconductor element in the semiconductor region 9a and correspondence to the outer peripheral portion of the semiconductor region 9a are prepared. Then, the first bonding pad 8 and the passivation film 14 are formed. Then, on the passivation film 14, for example, a polyimide precursor UR-3140.
After spin-coating (trade name, manufactured by Toray), selective exposure, and developing treatment with a developing solution DV-505 (trade name, manufactured by Toray) to expose and expose the first bonding pad 8 surface, 400 The polyimide precursor UR-3140 film is heated at ℃ to imidize to form the first insulating layer 10a (FIG. 3).

Next, an Al / Ti layer is entirely deposited on the surface of the formed first insulating layer 10a by, for example, a vapor deposition method.
After formation, etching resist O is formed on this Al / Ti layer.
FPR-800 (trade name, manufactured by Tokyo Ohka Co., Ltd.) is spin-coated, pre-baked, selectively exposed, and developed to form an etching resist pattern connected to the first bonding pad 8. After forming the required etching resist pattern in this way, use a mixed solution of phosphoric acid / acetic acid / nitric acid.
The Al layer and the Ti layer are sequentially etched with EDTA / NH ₃ / H ₂ O ₂ , and then the etching resist is peeled and removed to form the wiring 12 (FIG. 4).

The second insulating layer 10b is formed according to the above-mentioned means for forming the first insulating layer 10a on the wiring 12.
To form. In forming the second insulating layer 10b,
Required through-holes are formed so as to be connected to the wirings 12, respectively. Then, on this second insulating layer 10b surface,
In accordance with the method for forming the wiring 12, the deposition of Al / Ti layer
Forming and etching the Al / Ti layer selectively
A wiring pattern 12 'is formed (FIG. 5).

Then, a third insulating layer 10c is formed on the surface on which the second wiring pattern 12 'is formed, according to the means for forming the first insulating layer 10a. This third insulating layer 1
In forming 0c, through holes (forming second bonding pads 11) are formed so that at least a part of second wiring pattern 12 'is exposed in a region located on the surface of semiconductor region 9a (see FIG. 6).

After exposing the surface of the second bonding pad 11 to, for example, about 100 μm ^□ to provide a third insulating layer 10c, a Cu / Ti layer 15 is vapor-deposited on the surface of the third insulating layer 10c. After being completely deposited and formed by the method (Fig. 7),
Thick film resist AZ4903 (trade name, manufactured by Hoechst Japan)
Is spun-coated to form a resist layer having a film thickness of about 50 μm, and the resist layer 16 is subjected to selective exposure and development to form a Cu film corresponding to the second bonding pad 11 surface.
The / Ti layer 15 region is exposed, for example, by about 60 μm ^□ (FIG. 8).

In this way, the second bonding pad
A semiconductor substrate 9'having an opening (60 μm ^□ ) in the resist layer 16 having a size smaller than the opening area (100 μm ^□ ) corresponding to 11 was copper sulfate 250 g / l, sulfuric acid (specific gravity 1.84) under non-ultraviolet light.
Immerse in a solution consisting of 50 g / l, set the bath temperature to 25 ° C,
Using the Cu / Ti layer 15 as a cathode and a high-purity copper plate as an anode, a current density of 5 A / dm ^{2 is} applied and copper is plated to a thickness of about 35 μm with gentle stirring (formation of a barrier metal layer).

After that, the plating bath was set to a total Sn content of 40 g / l and the first Sn content.
35 g / l, Pb 44 g / l, free boric acid 40 g / l, boric acid 25 g / l, glue 3.0 g / l, instead of the Cu / Ti layer 15 as the cathode, 40% Sn as the anode And the current density is 5 A / dm ²
Electrode bumps by continuously plating Pb / Sn = 40/60 alloy (solder) to a thickness of about 35 μm while applying and gently stirring.
13 is formed (FIG. 9).

After forming the Pb / Sn-based electrode bumps 13 on the surface of the second bonding pad (region) 11 as described above,
The surface of the semiconductor substrate 9'is washed with acetone to remove the resist layer 16 (FIG. 10), and then a mixed solution of ammonium persulfate / sulfuric acid / ethanol is used with the Pb / Sn based electrode bumps 13 as a mask. First, the Ti / Cu layer 15
After the Cu layer in the inside is removed by etching, the Ti layer is removed by etching with a mixed solution of EDTA / ammonia / hydrogen peroxide to obtain the desired semiconductor device 9 (FIG.
11).

FIG. 12 is a sectional view showing a main part of a structure in which the semiconductor device 9 having the above structure is connected and mounted face down on a surface of a mounting circuit board, for example, an alumina substrate 7.
Connection and mounting can be easily achieved by the following means. That is, it is placed on the stage surface equipped with a heating mechanism in advance, and Cu
The semiconductor device 9 is held in a face-down positional relationship with respect to the surface of the alumina substrate 7 that has been preheated to a temperature lower than the melting point of, for example, 280 ° C. The terminal electrodes 6 on the surface of the alumina substrate 7 and the electrode bumps 13 of the semiconductor device 9
Align and contact each other. In this state, the temperature of the collet holding the semiconductor device 9 is heated in a nitrogen atmosphere so as to be maintained at the same temperature as the stage, for example, 280 ° C., and the solder forming the electrode bumps 13 is melted. By doing so, the semiconductor device 9 is electrically connected and mounted on the surface of the alumina substrate 7.

Next, another configuration example of the semiconductor device according to the present invention will be described.

FIG. 13 is a plan view showing a semiconductor device according to the present invention. In the second bonding pads 11 (group) arranged on the surface of the semiconductor element region 9a, the mutual distance / interval is maximum. The semiconductor device shown in FIG. 2 has a basic configuration except that the second bonding pad 11 is not arranged / formed on at least a part of a diagonal corner (corner). This is similar to the case of the device 9. Therefore, its manufacture can be easily configured according to the above-mentioned manufacturing means.

In this way, the second bonding pad 11
When the structure is arranged in a lattice shape excluding the corners on the diagonal line, the following peculiar actions and effects are further recognized. That is, even when thermal cycle stress is applied to the mounting / connecting portion (the connecting portion of the electrode bump 13) when the mounting / connecting is performed face down on the surface of the mounting substrate 7, the mounting substrate 7 and the semiconductor device 9 are connected to each other. Since the electrode bumps 13 do not exist at the corners on the diagonal line where the amount of displacement is maximum (therefore, the heat stress is most applied), almost uniform stress is applied to the electrode bumps 13 as a whole, and Reliability will not be lost.

For example, the coefficient of thermal expansion is almost twice that of Si.
Alumina substrate 7 (7.5 x 7.5 cm) at 6.0 to 6.5 x 10 ^-6 / ° C
2) shows the arrangement of the second bonding pad 11 on the surface of FIG.
(Example 1) and FIG. 13 (Example 2), and for comparison, semiconductor devices 9 and 2 having the configurations shown in FIG. 17 (conventional example).
(7.0 x 7.0 cm) ... The thermal expansion coefficient of Si is 3.5 x 10 ^-6 / ° C.
Were each flip-chip connected and mounted to form a mounted circuit device. Then, for these mounted circuit devices, a temperature cycle test {-55 ° C (30 min) to 25 ° C (5 min)
When the reliability was evaluated at ~ 150 ° C (30 min) to 25 ° C (5 min)}, the defect rate in this reliability test 1000 times was 53/100 in the comparative example. Examples 1 and 2
In the case of, it was 0/100. In addition, the reliability test
The defect rate after 100 times was 100/10 in the comparative example.
However, compared with the conventional semiconductor device for flip-chip mounting (connection), the mounting (connection) portion is 78/100 in the first embodiment and 0/100 in the second embodiment. It is possible to greatly reduce or avoid the occurrence of breakage or breakage phenomenon due to thermal stress on the. That is, when the semiconductor device according to the present invention is used for the configuration of the mounted circuit device, it greatly contributes to the reliability of the configured mounted circuit device.

The present invention is not limited to the above embodiment, and various modifications can be made without departing from the spirit of the present invention. For example, the structure of the electrode bump 13 is Pb / Sn.
Besides, Pb / Sn may be added with In, Sb, Bi, Zn, Ag, or the like, or may be an alloy system containing In, Sb, Bi, Zn, Ag, or the like as a main component. Further, the kind of metal forming the barrier metal layer, the thickness of the film, other means for forming the metal layer, the kind of plating resist or etching resist, the means for forming the resist layer (film), etc. are all limited to the above-mentioned examples. Not something.

[0031]

In the semiconductor device according to the present invention, it is exposed inside the region where the first bonding pad is arranged and on the insulating layer on the region surface where the required semiconductor element region is formed. Then, the second bonding pad is arranged, and these are connected to each other through the insulating layer and the interlayer insulating layer, for example, by a wiring arranged in multiple layers. That is, the electrode bumps mounted / connected face down on the mounting substrate surface are arranged on the surface of the area where the semiconductor element area is formed. Therefore, the area surface (effective area required for connection) involved in the connection to the mounting substrate surface is reduced. In other words, since the effective thermal expansion applied to the semiconductor device is also reduced, the stress applied to the electrode bumps due to the difference in the thermal expansion coefficient between the mounting substrate and the semiconductor device is also reduced, thus improving the reliability against thermal stress. Planned.

Moreover, in this structure, the heat generated in the semiconductor element region of the semiconductor device is easily dissipated to the mounting substrate side through the electrode bumps on the second bonding pad surface. In addition, since the area of each of the second bonding pads is set to be larger than the area of the first bonding pad, the electrode bumps can be formed to be relatively large. Can be easily aligned and the connection strength can be improved.

Further, in the case where the second bonding pads are arranged in a lattice pattern excluding the corners on the diagonal line, when the second bonding pads are mounted and connected face down on the mounting substrate surface, the mounting Connection part (connection part of electrode bump)
In addition, even if thermal cycle stress is applied, the amount of displacement between the mounting substrate and the semiconductor device is maximum (thus, thermal stress is most applied). Such stress is applied to the electrode bumps, so that the reliability of the connection portion is not impaired. Thus, it can be said that the flip-chip connection type semiconductor device according to the present invention greatly contributes to the configuration of a highly reliable mounted circuit device.

[Brief description of drawings]

FIG. 1 is a sectional view showing a main part of a structure in which a semiconductor device according to the present invention is mounted and connected to a mounting substrate surface.

FIG. 2 is a plan view showing a configuration example of a semiconductor device according to the present invention.

FIG. 3 is a sectional view schematically showing a state in which a first insulating layer is provided in an embodiment of a semiconductor device manufacturing example according to the present invention.

FIG. 4 is a cross-sectional view schematically showing a state in which wiring is provided in the embodiment of the manufacturing example of the semiconductor device according to the present invention.

FIG. 5 is a cross-sectional view schematically showing a state in which a metal layer forming a part of the second bonding pad is provided in the embodiment of the manufacturing example of the semiconductor device according to the invention.

FIG. 6 is a cross-sectional view schematically showing a state in which a resist mask is provided by opening and exposing the second bonding pad region in the embodiment of the manufacturing example of the semiconductor device according to the invention.

FIG. 7 is a sectional view schematically showing a state in which a metal layer forming a barrier metal layer on the second bonding pad region surface is provided in the embodiment of the manufacturing example of the semiconductor device according to the invention.

FIG. 8 is a cross-sectional view schematically showing a state in which a resist mask is provided by opening / exposing an electrode bump forming region in an embodiment of a semiconductor device manufacturing example according to the present invention.

FIG. 9 is a cross-sectional view schematically showing a state in which electrode bumps are electroplated in an embodiment of a semiconductor device manufacturing example according to the present invention.

FIG. 10 is a cross-sectional view schematically showing a state in which the resist mask is removed and the electrode bumps are exposed in the embodiment of the manufacturing example of the semiconductor device according to the invention.

FIG. 11 is a sectional view schematically showing a state in which an unnecessary portion of the metal layer forming the barrier metal layer is removed in the embodiment of the manufacturing example of the semiconductor device according to the invention.

FIG. 12 is a cross-sectional view showing the main parts of another structure in which the semiconductor device according to the present invention is mounted and connected to the mounting substrate surface.

FIG. 13 is a plan view showing another configuration example of the semiconductor device according to the present invention.

FIG. 14 is a sectional view showing a mounting / connecting structure for a mounting substrate surface of a conventional semiconductor device.

FIG. 15 is a sectional view showing another mounting / connecting structure for a mounting substrate surface of a conventional semiconductor device.

FIG. 16 is a cross-sectional view showing a main part of a structure in which a conventional semiconductor device is mounted and connected to a mounting substrate surface.

FIG. 17 is a plan view showing a configuration example of a conventional semiconductor device.

[Explanation of symbols]

1 ... Bonding pad 2, 9 ... Semiconductor device
2 ', 9' ... semiconductor substrate 2a, 9a ... semiconductor element region
3, 3 ', 14 ... Passivation film 4, 4', 15
Barrier metal layers 5, 13 Electrode bumps 6 Terminal electrodes 7 Mounting substrate 8 First bonding pads 10a, 10b, 10c Insulating layer 11 Second bonding pads 12, 12 'Wiring 16 Resist layer

Claims (1)

[Claims] 1. A semiconductor substrate, a semiconductor element region formed on a main surface of the semiconductor substrate, and first bonding pads arranged around the outer periphery of the semiconductor element region corresponding to the respective semiconductor element regions. An insulating film that exposes the first bonding pad surface and covers at least the semiconductor element region surface, and a first insulating film formed inside the first bonding pad corresponding to the first bonding pad on the insulating film. A second bonding pad, a bump electrode provided on the surface of the second bonding pad, one end connected to the first bonding pad and the other end connected to the second bonding pad, and the second bonding pad disposed in the insulating film region. And an area of the second bonding pad is set to be larger than an area of the first bonding pad. Semiconductor device.