JP2008053313A - Semiconductor integrated circuit device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a small semiconductor integrated circuit device capable of restraining a heating element formation region from having a thermal effect on a circuit formation region without disposing a thermal buffer region and utilizing a chip area effectively. <P>SOLUTION: The semiconductor integrated circuit device is equipped with a circuit formation region 31 and heating element formation regions 21a to 21c on a semiconductor chip. In the semiconductor integrated circuit devices 100 to 108; the circuit formation region 31 is disposed adjacent to the heating element formation regions 21a to 21c, and on-chip pads 61w, 61o, 61od, 62w, 62o, and 62od are arranged in the heating element formation regions 21a to 21c and/or the circuit formation region 31, along a boundary between the heating element formation regions 21a to 21c and circuit formation region 31 so as to surround the boundary. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a semiconductor integrated circuit device having a heating element formation region and a circuit formation region.

  Semiconductor integrated circuit devices (ICs) having a heating element forming region are disclosed in, for example, Japanese Patent Application Laid-Open Nos. 2004-22651 (Patent Document 1) and 2006-5325 (Patent Document 2). Has been.

  FIG. 10 is a diagram showing the semiconductor integrated circuit device disclosed in Patent Document 2, and FIG. 10A is a schematic top view showing a mounting form of the power composite integrated semiconductor device H1 using wire bonding. FIG. 10B is a diagram showing a schematic cross-sectional structure of the power composite integrated semiconductor device H1.

  In the power composite integrated semiconductor device H1, as shown in FIG. 10A, a power element portion 2 surrounded by a two-dot chain line and a control circuit portion 3 surrounded by a broken line are formed on one semiconductor chip. As shown in FIG. 10B, in the power composite integrated semiconductor device H1, by using the thick copper electrode 8 for the current collecting electrodes D1 and D2 of the power element portion 2, wiring resistance necessary for reducing the on-resistance is obtained. Is reduced. In addition, wire bonding bondability with the copper electrode 8 is ensured, and deterioration with time is suppressed at a high temperature due to copper diffusion and copper corrosion. Further, the power element unit 2 can be directly connected to the current collecting electrodes D1 and D2 and the control circuit unit 3 can be bonded to a bonding pad P1 formed on the control circuit unit 3. As a result, the pad area in the peripheral portion of the element, which has been conventionally required, is reduced, and the manufacturing cost is reduced.

  FIG. 11 is a generalized view of a conventional semiconductor integrated circuit device having a heating element forming region and a circuit forming region, and is a schematic top view of the semiconductor integrated circuit device 90. FIG. 12 is a diagram showing a mounting state of the semiconductor chip on which the semiconductor integrated circuit device is formed by wire bonding. FIGS. 12A and 12B show the semiconductor chip on the heat sink and the lead frame plate, respectively. It is typical sectional drawing at the time of mounting in.

  A semiconductor integrated circuit device 90 shown in FIG. 11 has heating element formation regions 20 a and 20 b and a circuit formation region 30. A circuit formation region 30 in the semiconductor integrated circuit device 90 of FIG. 11 is a region where a circuit using active elements is formed, and corresponds to the control circuit unit 3 in the power composite integrated semiconductor device H1 of FIG. The heating element formation regions 20a and 20b in the semiconductor integrated circuit device 90 of FIG. 11 are regions in which power active elements having a heat generation amount larger than the heat generation amount of the active elements in the peripheral circuit formation region 30 are formed. This corresponds to the power element portion 2 in the power composite integrated semiconductor device H1 of FIG.

In the heat generating element forming region 20a in the semiconductor integrated circuit device 90 of FIG. 11, a pad 50 is formed above the power active element, which is connected to the power active element inside and exposes a metal layer for wire bonding to the lead frame pin. An external pad that is not provided is disposed outside the heating element formation region 20a. On the other hand, in the heating element forming region 20b, a pad 60 that is connected to an internal power active element and exposes a metal layer for wire bonding with a lead frame pin is formed on the element formed above the power active element. As a pad, it is arranged inside the heating element formation region 20b. As shown in FIG. 11, both the external pad 50 and the element upper pad 60 are arranged near the outer periphery of the semiconductor chip in order to facilitate wire bonding with the lead frame pins.
JP 2004-22651 A JP 2006-5325 A

  In the semiconductor integrated circuit device 90 of FIG. 11, thermal buffer regions 40a and 40b are disposed between the heating element forming regions 20a and 20b and the circuit forming region 30 around them. The heat generated in the heat generating element forming regions 20a and 20b is generally radiated to the outside through a substrate, an aluminum wiring, a bonding wire, and the like. However, when the amount of heat generated in the heating element formation regions 20a and 20b is large, the temperature of the surrounding circuit formation region 30 also rises, causing a problem in the circuit operation of the circuit formation region 30. In particular, when a semiconductor chip is mounted on the lead frame plate of FIG. 12B, there is no heat dissipation from the back surface of the substrate as compared with the case of mounting a semiconductor chip on the heat sink of FIG. The probability that the circuit operation in the formation region 30 will malfunction is also increased. The thermal buffer regions 40a and 40b in the semiconductor integrated circuit device 90 of FIG. 11 are regions where only passive elements that are not easily affected by heat are formed, or regions where only wirings where no passive elements are formed are formed. By disposing the heat buffer regions 40a and 40b, the influence of heat from the heating element forming regions 20a and 20b to the circuit forming region 30 can be suppressed.

  On the other hand, when the heat buffer regions 40a and 40b are disposed between the heat generating element forming regions 20a and 20b and the circuit forming region 30 as shown in FIG. 11, the chip area naturally increases. Although the heat buffer region is not shown in the power composite integrated semiconductor device H1 in FIG. 10A, the heat buffer region is necessary when the heat generation amount of the power element unit 2 is large. As shown in the semiconductor integrated circuit device 90 of FIG. 11, the heat generating element forming region 20 b having the upper pad 60 has better heat dissipation than the heat generating element forming region 20 a having the external pad 50. For this reason, as shown in FIG. 11, the occupation area of the thermal buffer region 40b arranged around the heating element formation region 20b is smaller than the occupation area of the thermal buffer region 40a arranged around the heating element formation region 20a. I'll do it. Further, when the heat generation amount in the heat generating element forming region 20b is small, the heat buffering region 40b may not be arranged. However, in a semiconductor integrated circuit device having a heating element formation region and a circuit formation region, even if the heating element formation region is a heating element formation region having a pad on the element, generally a heat buffer region And the chip area increases accordingly.

  Accordingly, the present invention is a semiconductor integrated circuit device having a heating element formation region and a circuit formation region, and suppresses the influence of heat from the heating element formation region to the circuit formation region without disposing a thermal buffer region. An object of the present invention is to provide a small-sized semiconductor integrated circuit device that can effectively use the chip area.

  According to another aspect of the semiconductor integrated circuit device of the present invention, the heat generation amount of the active element in the circuit formation region, which is a region where a circuit using active elements is formed on one semiconductor chip, and the peripheral circuit formation region is compared. A semiconductor integrated circuit device having a heat generating element forming region, which is a region where a power active element having a large heat generation amount is formed, wherein the circuit forming region is disposed adjacent to the heat generating element forming region. And an element pad formed above the active element or the power active element surrounds the boundary along the boundary between the heating element formation region and the circuit formation region. Thus, a plurality of heat generating element formation regions and / or circuit formation regions are arranged.

  In the semiconductor integrated circuit device, a circuit forming region is arranged adjacent to the heat generating element forming region, and only a region where only passive elements that are not easily affected by heat are formed or wirings where no passive elements are also formed are provided. The heat buffering region, which is a region where is formed, is not disposed between the heating element forming region and the circuit forming region. Therefore, the semiconductor integrated circuit device is a semiconductor integrated circuit device in which an increase in chip area due to the arrangement of the thermal buffer region is eliminated.

  On the other hand, in the semiconductor integrated circuit device, instead of disposing the thermal buffer region between the heat generating element forming region and the circuit forming region, the element upper pad extends along the boundary between the heat generating element forming region and the circuit forming region. Are arranged in the heat generating element formation region and / or the circuit formation region. The element upper pad is a terminal exposed from a metal layer used for wire bonding or the like, and is a pad formed above the active element or the power active element. The pad on the element can be used for heat dissipation because the metal layer is exposed. Accordingly, a plurality of pads on the element are arranged in the heating element formation region and / or the circuit formation region so as to surround the boundary between the heating element formation region and the circuit formation region, thereby forming the heating element. Heat transfer from the region to the circuit formation region can be efficiently suppressed.

  As described above, the semiconductor integrated circuit device is a semiconductor integrated circuit device having a heat generating element forming region and a circuit forming region, and the circuit forming region is changed from the heat generating element forming region without disposing the heat buffer region. The effect of heat on the surface of the semiconductor integrated circuit device can be suppressed, and an increase in the chip area due to the arrangement of the thermal buffer region is eliminated, and a small semiconductor integrated circuit device that effectively uses the chip area is obtained.

  In the semiconductor integrated circuit device, as described in claim 2, the pad on the element is disposed over the entire surface from the boundary with the circuit formation region to the central portion in the heating element formation region. It is preferable to become.

  As described above, the element upper pad can be used for heat dissipation. Therefore, the element upper pad is not only arranged at the boundary between the heating element formation region and the circuit formation region, but also in the heating element formation region from the boundary with the circuit formation region. By disposing it over the entire surface up to the part, it is possible to efficiently dissipate heat generated in the heating element formation region.

  In the semiconductor integrated circuit device, it is preferable that the element pads are arranged at lattice points of lattice stripes. As a result, the on-element pads are arranged at equal intervals in a predetermined direction, and wire bonding to the on-element pads is facilitated.

  In the semiconductor integrated circuit device, as described in claim 4, at least one element upper pad among the element upper pads arranged in the heat generating element formation region and / or the circuit formation region is provided. It may be an open pad that is not connected to other terminals. That is, in the semiconductor integrated circuit device, at least one, preferably not only an element pad used for connection to another terminal but also an element pad as an open pad (dummy pad) that is not connected to another terminal. Are arranged in large numbers, and these open pads are used for heat dissipation. Thus, in the semiconductor integrated circuit device, heat transfer from the heating element formation region to the circuit formation region can be efficiently suppressed.

  According to a fifth aspect of the present invention, it is preferable that the open pads are connected to each other by an integral wiring pattern in the heating element formation region and / or the circuit formation region. According to this, the heat generated in the heat generating element formation region and / or the heat transmitted to the circuit formation region can be accumulated by the integrated wiring pattern and efficiently radiated from the open pad.

  According to a sixth aspect of the present invention, the open pad is preferably subjected to other end open wire bonding in which the other end of the wire is not connected to another terminal. According to this, heat can be dissipated not only from the metal layer exposed on the surface of the semiconductor chip but also from the wire in which the other end bonded to the open pad with a dummy is open (not connected to other terminals). it can.

  The semiconductor integrated circuit device is suitable for a case where the semiconductor chip is mounted on a lead frame plate as described in claim 7. In the semiconductor integrated circuit device, since heat dissipation from the main surface side of the semiconductor chip is improved by the pad on the element, heat dissipation from the back surface side of the substrate cannot be expected, especially when the semiconductor chip is mounted on the lead frame plate. Is suitable.

  The best mode for carrying out the present invention will be described below with reference to the drawings.

  1 to 3 are schematic top views of semiconductor integrated circuit devices 100 to 102, respectively, which are examples of the semiconductor integrated circuit device of the present invention.

  Each of the semiconductor integrated circuit devices 100 to 102 shown in FIGS. 1 to 3 is a semiconductor integrated circuit device having heating element forming regions 21 a to 21 c and a circuit forming region 31 in one semiconductor chip. The circuit formation region 31 is a region where a circuit using active elements is formed. The heating element forming regions 21a to 21c are regions where a power active element having a heat generation amount larger than the heat generation amount of the active element in the peripheral circuit formation region 31 is formed. In each of the semiconductor integrated circuit devices 100 to 102 of FIGS. 1 to 3, the circuit forming region 31 is disposed adjacent to the heating element forming regions 21 a to 21 c.

  Further, in each of the semiconductor integrated circuit devices 100 to 102 shown in FIGS. 1 to 3, the plurality of element pads 61w, 61o, 62w, and 62o are formed by heating element forming regions 21a to 21c indicated by broken lines in the drawings. And the circuit forming region 31 are arranged so as to surround the boundary. In the semiconductor integrated circuit device 100 of FIG. 1, a plurality of element upper pads 61w and 61o are arranged in the heating element forming regions 21a to 21c so as to surround the boundary. In the semiconductor integrated circuit device 101 of FIG. 2, a plurality of element pads 62w and 62o are arranged in the circuit formation region 31 so as to surround the boundary. In the semiconductor integrated circuit device 100 of FIG. 3, a plurality of element pads 61w, 61o, 62w, 62o are arranged in the heating element formation regions 21a to 21c and the circuit formation region 31 so as to surround the boundary. Yes.

  In the semiconductor integrated circuit devices 100 to 102 of FIGS. 1 to 3, the element pads 61w, 61o, 62w, and 62o are terminals with exposed metal layers, and the active elements or heating element formation regions 21a to 21c in the circuit formation region 31. Is formed above the power active element. 1 to 3, the connection pads connected to the lead frame pins (other terminals) among the element pads 61w, 61o, 62w, 62o are represented by the letter w. Reference numerals 61w and 62w are attached, and open pads (dummy pads) that are not connected to other terminals are identified as reference numerals 61o and 62o with the letter o. Among the element upper pads 61w, 61o, 62w, 62o, the element upper pads arranged in the heat generating element formation regions 21a to 21c are denoted by reference numerals 61w, 61o with numerals 61 and arranged in the circuit formation region 31. The element upper pads are identified as reference numerals 62w and 62o with numerals 62.

  The semiconductor integrated circuit devices 100 to 102 shown in FIGS. 1 to 3 are different from the semiconductor integrated circuit device 90 shown in FIG. 11 in that the circuit forming region 31 is arranged adjacent to the heating element forming regions 21a to 21c. ing. Therefore, the heat buffer regions 40a and 40b shown in FIG. 11 which are regions where only passive elements that are hardly affected by heat are formed, or regions where only wirings where no passive elements are formed are formed are shown in FIGS. In the semiconductor integrated circuit devices 100 to 102 of FIG. 3, they are not arranged between the heat generating element forming regions 21 a to 21 c and the circuit forming region 31. Therefore, the semiconductor integrated circuit devices 100 to 102 in FIGS. 1 to 3 are semiconductor integrated circuit devices in which an increase in chip area due to the arrangement of the thermal buffer regions 40a and 40b in FIG. 11 is eliminated.

  On the other hand, in the semiconductor integrated circuit devices 100 to 102 of FIGS. 1 to 3, instead of disposing the heat buffer regions 40 a and 40 b of FIG. 11 between the heating element forming regions 21 a to 21 c and the circuit forming region 31, A plurality of pads 61w, 61o, 62w, and 62o are arranged along the boundary between the heat generating element forming regions 21a to 21c and the circuit forming region 31 so as to surround the boundary. The element upper pads 61w, 61o, 62w, and 62o are terminals exposed from the metal layer used for wire bonding or the like as described above, and are pads formed above the active element or the power active element. The element upper pads 61w, 61o, 62w, and 62o can be used for heat dissipation because the metal layer is exposed. Accordingly, the element pads 61w, 61o, 62w, and 62o are surrounded by the heat generating element forming regions 21a to 21c and the circuit forming region 31 so as to surround the boundary. By disposing a plurality in the at least one region 31, heat transfer from the heating element formation regions 21 a to 21 c to the circuit formation region 31 can be efficiently suppressed.

  As described above, each of the semiconductor integrated circuit devices 100 to 102 shown in FIGS. 1 to 3 is a semiconductor integrated circuit device having the heating element forming regions 21 a to 21 c and the circuit forming region 31. It is possible to suppress the influence of heat from the heating element formation regions 21a to 21c to the circuit formation region 31 without disposing the heat buffer region, and to eliminate the increase in chip area due to the disposition of the heat buffer region. It is a small semiconductor integrated circuit device that is effectively utilized.

  FIGS. 4 and 5 are schematic top views of the semiconductor integrated circuit devices 103 and 104, respectively, as other examples of the semiconductor integrated circuit device. In the semiconductor integrated circuit devices 103 and 104 shown in FIGS. 4 and 5, the same reference numerals are given to the same parts as those of the semiconductor integrated circuit devices 100 to 102 shown in FIGS.

  The semiconductor integrated circuit devices 103 and 104 shown in FIG. 4 and FIG. 5 are, in comparison with the semiconductor integrated circuit devices 100 and 101 shown in FIG. 1 and FIG. 2, respectively, in the heating element forming regions 21a to 21c. 61o is additionally arranged. Accordingly, in the semiconductor integrated circuit devices 103 and 104 of FIGS. 4 and 5, the element pads 61w and 61o are not only in the vicinity of the boundary with the circuit formation region 31 in the heating element formation regions 21a to 21c, but also in the circuit. It is arranged over the entire surface from the boundary with the formation region 31 to the central portion.

  As described above, the element pads 61w, 61o, 62w, and 62o can be used for heat dissipation. Therefore, as in the semiconductor integrated circuit devices 100 to 102 shown in FIGS. 1 to 3, the element pads 61 w, 61 o, 62 w, and 62 o are only arranged at the boundaries between the heating element formation regions 21 a to 21 c and the circuit formation region 31. Instead, as in the semiconductor integrated circuit devices 103 and 104 of FIGS. 4 and 5, the heat generating element formation regions 21 a to 21 c are arranged over the entire surface from the boundary with the circuit formation region 31 to the central portion. The heat generated in the heating element forming regions 21a to 21c can be efficiently radiated. In the semiconductor integrated circuit device 102 shown in FIG. 3, the element pads 61w and 61o are arranged over the entire surface from the boundary with the circuit formation region 31 to the central portion in the heating element formation regions 21a to 21c. Needless to say, the same effect can be obtained.

  As described above, in the semiconductor integrated circuit devices 100 to 104 described above, all of the element upper pads among the element upper pads arranged in the heat generating element formation regions 21a to 21c and / or the circuit formation region 31 are used. Is not required to be the connection pads 61w and 62w connected to the other terminals, and at least one on-element pad may be the open pads 61o and 62o not connected to the other terminals. That is, in the semiconductor integrated circuit devices 100 to 104, not only the element pads 61w and 62w used for connection to other terminals, but also the open pads (dummy pads) 61o that do not connect the element pads to other terminals. As 62o, at least one or more, preferably many, are arranged, and these open pads 61o, 62o are used for heat dissipation. Thus, in the semiconductor integrated circuit devices 100 to 104, heat transfer from the heating element forming regions 21a to 21c to the circuit forming region 31 can be efficiently suppressed.

  In the semiconductor integrated circuit devices 100 to 104, the element pads 61w, 61o, 62w, and 62o are preferably arranged at lattice points of lattice stripes. Thereby, the element pads 61w, 61o, 62w, 62o are arranged at equal intervals in a predetermined direction, and wire bonding to the element pads 61w, 62w is facilitated.

  6 to 8 are schematic top views of the semiconductor integrated circuit devices 105 to 107, respectively, as other examples of the semiconductor integrated circuit device. In addition, in the semiconductor integrated circuit devices 105 to 107 of FIGS. 6 to 8, the same reference numerals are given to the same parts as those of the semiconductor integrated circuit devices 100 to 104 described above.

  In the semiconductor integrated circuit device 105 shown in FIG. 6, as can be seen from the semiconductor integrated circuit device 103 shown in FIG. 4, the open pad 61o is formed by the integrated wiring pattern 71 in the heating element forming regions 21a to 21c. Are connected to each other. In the semiconductor integrated circuit device 106 shown in FIG. 7, as can be seen from the semiconductor integrated circuit device 101 shown in FIG. 2, the open pads 62 o are connected to each other by an integral wiring pattern 72 in the circuit formation region 31. ing. Further, in the semiconductor integrated circuit device 107 shown in FIG. 8, the open pads 61o and 62o are connected to each other by the integrated wiring patterns 71 and 72 in the heating element forming regions 21a to 21c and the circuit forming region 31. In the semiconductor integrated circuit devices 105 to 107 shown in FIGS. 6 to 8, the heating element forming regions 21 a to 21 c are formed by the integrated wiring patterns 71 and 72 in the heating element forming regions 21 a to 21 c and / or the circuit forming region 31. The heat generated inside and / or the heat transmitted to the circuit formation region 31 can be integrated by the integrated wiring patterns 71 and 72 and efficiently radiated from the open pads 61o and 62o. In addition, in the semiconductor integrated circuit devices 105 to 107 shown in FIGS. 6 to 8, all the open pads 61o in the heating element formation regions 21a to 21c are connected by the wiring pattern 71, and all in the circuit formation region 31 are connected. The open pads 62 o are connected by the wiring pattern 72. However, the present invention is not limited thereto, and wiring patterns 71 and 72 that connect two or more open pads 61o and 62o may be used.

  FIG. 9 is a schematic top view of another semiconductor integrated circuit device 108. In the semiconductor integrated circuit device 108 of FIG. 9, the same parts as those of the semiconductor integrated circuit devices 100 to 107 described above are denoted by the same reference numerals.

  In the semiconductor integrated circuit device 108 of FIG. 9, as can be seen in comparison with the semiconductor integrated circuit device 104 shown in FIG. 5, the other end of the wire is connected to the open pad indicated by reference numerals 61 od and 62 od. The other end open wire bonding is applied. According to this, heat is radiated not only from the metal layer exposed on the surface of the semiconductor chip but also from the wire in which the other end bonded to the open pads 61od and 62od by a dummy is open (not connected to other terminals). can do. Needless to say, the other semiconductor integrated circuit devices 100 to 103 and 105 to 107 are also similarly improved in heat dissipation by subjecting arbitrary open pads 61o and 62o to open wire bonding at the other end.

  As described above, each of the semiconductor integrated circuit devices 100 to 108 described above is a semiconductor integrated circuit device including the heat generating element forming regions 21a to 21c and the circuit forming region 31, and includes a heat buffer region. It is possible to suppress the influence of heat from the heating element formation regions 21a to 21c to the circuit formation region 31 without arranging them, and the semiconductor integrated circuit device is a small-sized semiconductor device that effectively utilizes the chip area.

  Therefore, the semiconductor integrated circuit devices 100 to 108 described above are suitable for mounting a semiconductor chip on which the semiconductor device is formed on a lead frame plate. In the semiconductor integrated circuit devices 100 to 108, since the heat radiation from the main surface side of the semiconductor chip is improved by the element pads 61w, 61o, 61od, 62w, 62o, and 62od, the heat radiation from the back surface side of the substrate cannot be expected. Particularly suitable for mounting a semiconductor chip on a lead frame plate.

1 is a schematic top view of a semiconductor integrated circuit device 100 as an example of the semiconductor integrated circuit device of the present invention. FIG. 6 is a schematic top view of a semiconductor integrated circuit device 101 as another example of the semiconductor integrated circuit device. FIG. 6 is a schematic top view of a semiconductor integrated circuit device 102 as another example of the semiconductor integrated circuit device. FIG. 11 is a schematic top view of a semiconductor integrated circuit device 103 as another example of the semiconductor integrated circuit device. FIG. 10 is a schematic top view of a semiconductor integrated circuit device 104 as another example of the semiconductor integrated circuit device. 10 is a schematic top view of a semiconductor integrated circuit device 105 as another example of the semiconductor integrated circuit device. FIG. FIG. 6 is a schematic top view of a semiconductor integrated circuit device 106 as another example of the semiconductor integrated circuit device. FIG. 11 is a schematic top view of a semiconductor integrated circuit device 107 as another example of the semiconductor integrated circuit device. FIG. 11 is a schematic top view of a semiconductor integrated circuit device 108 as another example of the semiconductor integrated circuit device. FIG. 7 is a diagram illustrating a semiconductor integrated circuit device disclosed in Patent Document 2, wherein (a) is a schematic top view illustrating a mounting form of a power composite integrated semiconductor device H1 using wire bonding, and (b) is a power diagram. It is a figure which shows the typical cross-section of composite integrated semiconductor device H1. FIG. 2 is a generalized view of a conventional semiconductor integrated circuit device having a heating element formation region and a circuit formation region, and is a schematic top view of a semiconductor integrated circuit device 90. FIG. FIGS. 5A and 5B are diagrams showing a mounting state of a semiconductor chip on which a semiconductor integrated circuit device is formed by wire bonding, and FIGS. 5A and 5B are schematic views when the semiconductor chip is mounted on a heat sink and a lead frame plate, respectively. It is sectional drawing.

Explanation of symbols

H1, 90, 100 to 108 Semiconductor integrated circuit device 2, 20a, 20b, 21a to 21c Heating element formation region 3, 30, 31 Circuit formation region 61w, 61o, 61od, 62w, 62o, 62od Element upper pad 71, 72 ( Wiring pattern 40a, 40b for connecting open pads 61o, 62o)

Claims (7)

A circuit formation region, which is a region where a circuit using active elements is formed on one semiconductor chip, and a region where a power active element having a larger calorific value than that of the active element in the peripheral circuit formation region is formed. A semiconductor integrated circuit device having a heating element forming region,
The circuit forming region is disposed adjacent to the heating element forming region,
In the terminal where the metal layer is exposed, an element pad formed above the active element or the power active element surrounds the boundary along the boundary between the heating element forming region and the circuit forming region, A semiconductor integrated circuit device comprising a plurality of heating element formation regions and / or circuit formation regions.   2. The semiconductor integrated circuit device according to claim 1, wherein the element upper pad is arranged over the entire surface from the boundary with the circuit formation region to the center portion in the heating element formation region.   3. The semiconductor integrated circuit device according to claim 1, wherein the element upper pads are arranged at lattice points of lattice stripes.   The at least one element upper pad among the element upper pads arranged in the heat generating element formation region and / or the circuit formation region is an open pad not connected to another terminal. Item 4. The semiconductor integrated circuit device according to any one of Items 1 to 3.   5. The semiconductor integrated circuit device according to claim 4, wherein the open pads are connected to each other by an integral wiring pattern in the heating element formation region and / or the circuit formation region.   6. The semiconductor integrated circuit device according to claim 4, wherein the open pad is provided with open wire bonding at the other end where the other end of the wire is not connected to another terminal.   The semiconductor integrated circuit device according to claim 1, wherein the semiconductor chip is mounted on a lead frame plate.

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