JP6301763B2 - Semiconductor device and manufacturing method of semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device, and is a technique applicable to, for example, a semiconductor device including a bonding pad.

  Various studies have been conducted on technologies related to semiconductor devices having bonding pads. As such a technique, the thing of patent documents 1-6 is mentioned, for example.

  Patent Document 1 describes a semiconductor device in which an end portion of an interlayer insulating film surrounding an outer periphery of a bonding pad is covered with a metal film made of the same material as the bonding pad without contacting the bonding pad. Patent Document 2 includes a bonding pad portion and a wiring portion that are provided adjacent to each other, and a void region that extends in the same direction as the outer peripheral edge of the bonding pad is provided in a region on the wiring portion side of the bonding pad. The described semiconductor device is described.

  In Patent Document 3, the uppermost metal wiring layer is formed in the opening formed in the uppermost interlayer insulating film to form a bonding pad portion, and a part of the metal wiring layer is formed on the side surface portion of the opening. A semiconductor device formed in a ring shape so as to cover is described. The technique described in Patent Document 4 is to provide a hole penetrating from the upper surface to the lower surface of the bonding pad in the connection region to which the bonding wire of the bonding pad is connected.

  Patent Document 5 describes a semiconductor integrated circuit having a bonding pad formed on a semiconductor substrate and having a concave cross section. In Patent Document 6, a metal wire is electrically connected to a first pad via a metal ball, and the above-described metal ball and a second pad arranged adjacent to the first pad in a plan view. A semiconductor device is described in which a groove is formed in a part of the surface of the first pad sandwiched between.

JP-A-5-29376 International Publication No. 2006/046302 Pamphlet JP-A-4-192333 JP 2003-243443 A Japanese Patent Laid-Open No. 5-90327 JP 2013-187373 A

The semiconductor device may include a bonding pad containing Al. In this case, since a difference in thermal expansion coefficient can occur between the bonding pad and the insulating layer adjacent to the bonding pad, there is a concern that cracks due to the temperature cycle may occur in the insulating layer. For this reason, it is required to improve the temperature cycle resistance of the semiconductor device.
Other problems and novel features will become apparent from the description of the specification and the accompanying drawings.

  According to one embodiment, the pad containing Al is provided with a recess that does not penetrate the pad. An embedding member is embedded in the recess.

  According to the embodiment, the temperature cycle resistance of the semiconductor device can be improved.

1 is a diagram illustrating a semiconductor device according to a first embodiment. 1 is a cross-sectional view showing a semiconductor device according to a first embodiment. It is a top view which shows the example of the planar structure of the pad which concerns on 1st Embodiment. It is a top view which shows the example of planar arrangement | positioning of a pad. 1 is a cross-sectional view showing a semiconductor device according to a first embodiment. It is a top view which shows the structure of the pad shown in FIG. FIG. 3 is a cross-sectional view showing a method for manufacturing the semiconductor device shown in FIG. 1. FIG. 3 is a cross-sectional view showing a method for manufacturing the semiconductor device shown in FIG. 1. FIG. 3 is a cross-sectional view showing a method for manufacturing the semiconductor device shown in FIG. 1. FIG. 3 is a cross-sectional view showing a method for manufacturing the semiconductor device shown in FIG. 1. It is sectional drawing which shows the semiconductor device which concerns on 2nd Embodiment. It is a top view which shows the example of the plane structure of the pad which concerns on 2nd Embodiment. FIG. 8 is a cross-sectional view showing a modification of the semiconductor device shown in FIG. 1.

  Hereinafter, embodiments will be described with reference to the drawings. In all the drawings, the same reference numerals are given to the same components, and the description will be omitted as appropriate.

(First embodiment)
FIG. 1 is a diagram showing a semiconductor device SD1 according to this embodiment. FIG. 1A is a plan view of the semiconductor device SD1, and FIG. 1B is a cross-sectional view showing an AA ′ cross section in FIG. In FIG. 1A, the sealing resin ER1 and the bonding wire BW1 are omitted.
The semiconductor device SD1 includes an insulating layer IL1, a pad PD1, an embedded member BM1, an insulating layer IL2, a bonding wire BW1, and a sealing resin ER1. The pad PD1 is provided on the insulating layer IL1, includes Al, and has a recess RC1 that does not penetrate. The embedded member BM1 is embedded in the recess RC1. The insulating layer IL2 is provided on the insulating layer IL1 and the pad PD1, and has an opening OP1 that exposes a region including the recess RC1 in the pad PD1. The bonding wire BW1 is in contact with the pad PD1 exposed from the opening OP1. The sealing resin ER1 is provided on the insulating layer IL2 and seals the bonding wire BW1.

  As described above, there may be a difference in thermal expansion coefficient between the bonding pad containing Al and the insulating layer adjacent to the bonding pad. In this case, stress is applied to the insulating layer due to expansion and contraction of the bonding pad due to the temperature cycle. However, there is a concern that cracks may occur in the insulating layer when the stress increases due to, for example, increasing the thickness of the wiring layer constituting the bonding pad. Therefore, it has been required to realize a semiconductor device having a bonding pad that can improve temperature cycle resistance.

  According to the present embodiment, the pad PD1 is provided with the recess RC1 that does not penetrate the pad PD1. Thereby, the volume of pad PD1 can be reduced and expansion and contraction at the time of a temperature cycle can be suppressed. Further, by embedding the embedded member BM1 in the recess RC1, the expansion and contraction of the pad PD1 during the temperature cycle can be more effectively suppressed. Thus, according to the present embodiment, it is possible to suppress the occurrence of cracks in the insulating layer adjacent to the pad PD1 by suppressing the expansion and contraction of the pad PD1 due to the temperature cycle. Accordingly, it is possible to improve the temperature cycle resistance of the semiconductor device.

  Hereinafter, the semiconductor device SD1 according to the present embodiment will be described in detail.

FIG. 2 is a sectional view showing the semiconductor device SD1 according to this embodiment.
The semiconductor device SD1 according to the present embodiment seals, for example, the substrate SUB, the semiconductor chip SC1 mounted on the substrate SUB, the bonding wire BW1 connecting the substrate SUB and the semiconductor chip SC1, and the semiconductor chip SC1 and the bonding wire BW1. And a sealing resin ER1 to be stopped.

FIG. 2A illustrates a case where the substrate SUB is an interposer. In this case, the semiconductor chip SC1 is mounted on one surface of the substrate SUB. Further, on the other surface opposite to the one surface of the substrate SUB, an external terminal composed of, for example, solder balls is provided.
FIG. 2B illustrates a case where the substrate SUB is a lead frame. In this case, the semiconductor chip SC1 is mounted on the die pad DP1 of the substrate SUB. Further, the semiconductor element SE1 and the outer lead OL1 of the substrate SUB are electrically connected to each other by a bonding wire BW1.
The configuration of the semiconductor device SD1 is not limited to that illustrated in FIGS. 2A and 2B, and various semiconductor package structures can be employed.

  The semiconductor chip SC1 includes a plurality of pads PD1 that are bonding pads. For example, the pad PD1 is provided on the other surface of the semiconductor chip SC1 opposite to the surface facing the substrate SUB. The bonding wire BW1 is in contact with the pad PD1 provided on the semiconductor chip SC1 to electrically connect the semiconductor chip SC1 and the substrate SUB.

As shown in FIG. 1B, the pad PD1 is provided on the insulating layer IL1.
Insulating layer IL1 forms, for example, an interlayer insulating film, an etching stopper film, and a protective film in a multilayer wiring structure of a semiconductor chip. Insulating layer IL1 is formed of, for example, an inorganic insulating film. The inorganic insulating film constituting the insulating layer IL1 is made of one or more selected from, for example, SiO ₂ , SiN, and SiON. In this embodiment, the inorganic insulating film is formed by laminating a single layer structure composed of any one selected from SiO ₂ film, SiN film, and SiON film, or two or more selected from these. It can be set as the laminated structure formed.

  The pad PD1 contains Al (aluminum). Thereby, pad PD1 excellent in adhesiveness etc. with an adjacent insulating film can be realized at low cost. In the present embodiment, the pad PD1 may contain other metal elements together with, for example, Al. Other metal elements can include one or more of Cu (copper), Ag (silver), Au (gold), and Ti (titanium). Thereby, it is possible to improve the balance of various characteristics such as resistance in the pad PD1. Further, another metal layer containing, for example, Ti may be provided on the pad PD1. In this case, the other metal layer is provided, for example, on a region of the pad PD1 where the recess RC1 is not provided, and is not provided in the recess RC1.

The thickness _{T P} of the pad PD1, for example is preferably at least 1300 nm, and more preferably 1500nm or more. Thereby, for example, it is possible to reduce the resistance of the I / O buffer and contribute to the performance improvement of the semiconductor device SD1. On the other hand, when the pad PD1 having such a thick film is employed, since the volume of the pad PD1 increases, the expansion and contraction of the pad PD1 due to the temperature cycle increases. In this case, there is a concern about the generation of cracks in the insulating layer adjacent to the pad PD1. According to the present embodiment, the recess PD1 is provided in the pad PD1 and the embedded member BM1 is embedded in the recess RC1, so that even if the pad PD1 having the thick film as described above is employed, Expansion and contraction can be suppressed. For this reason, it is possible to improve the temperature cycle performance while reducing the resistance value of the I / O buffer. Upper limit of the thickness _{T P} of the pad PD1 is not particularly limited, it can be set to 3000 nm. The thickness _{T P} of the pad PD1 refers to the thickness of the portion where the recess RC1 is not provided within the pads PD1.

  The pad PD1 is provided with a recess RC1 that does not penetrate the pad PD1. Thereby, as above-mentioned, the volume of pad PD1 can be reduced compared with the case where the recessed part RC1 is not formed. For this reason, it becomes possible to suppress the expansion and contraction of the pad PD1 during the temperature cycle. Recess RC1 is provided, for example, on the surface of pad PD1 that contacts bonding wire BW1. Further, the recess RC1 is not provided on a surface other than the surface in contact with the bonding wire BW1 of the pad PD1, for example.

  The pad PD1 can be provided with, for example, a plurality of recesses RC1 spaced apart from each other. Thereby, the freedom degree in design of the recessed part RC1 can be improved. For this reason, it becomes easy for the pad PD1 to improve the balance between temperature cycle resistance and low resistance. The plurality of recesses RC1 preferably have the same depth from the viewpoint of manufacturability, but may have different depths. Note that only one recess RC1 may be provided in the pad PD1.

  The planar shape of the recess RC1 is not particularly limited, and various shapes can be adopted.

FIG. 3 is a plan view showing an example of a planar structure of the pad PD1 according to the present embodiment.
FIG. 3A illustrates a case where the recesses RC1 are provided in a lattice shape. The length of the unit cell is not particularly limited, but can be, for example, 0.1 μm or more and 3.0 μm or less.
FIG. 3B illustrates a case where a plurality of recesses RC1 are provided in the pad PD1 so as to extend in the first direction, respectively. Moreover, in FIG.3 (b), each recessed part RC1 is arranged in the 2nd direction orthogonal to the said 1st direction and pad PD1 plane. The interval between the adjacent recesses RC1 in the second direction is not particularly limited, but may be, for example, 0.05 μm or more and 3.0 μm or less.
FIG. 3C illustrates a case where a plurality of concave portions RC1 are arranged in an array on the pad PD1. Although the space | interval of adjacent recessed part RC1 is not specifically limited, For example, it can be 0.05 micrometer or more and 3.0 micrometers or less. Moreover, in FIG.3 (c), several recessed part RC1 may be arranged in zigzag form.
In FIG. 3, the vertical direction in the figure coincides with the first direction, and the horizontal direction in the figure coincides with the second direction. Further, the planar shape of the recess RC1 and the number of the recesses RC1 are not limited to those shown in FIG.

FIG. 4 is a plan view showing an example of a planar arrangement of the pad PD1.
The plurality of pads PD1 are arranged along the outer peripheral edge of the semiconductor chip SC1, for example. In FIG. 4, for example, recesses RC1 are provided for all pads PD1 provided in semiconductor chip SC1. On the other hand, among the plurality of pads PD1 provided on the semiconductor chip SC1, it is also possible to adopt a mode in which the recess RC1 is provided in only some of the pads PD1 and the recess RC1 is not provided in the other pads PD1. is there.

In the present embodiment, for example, the planar shape of the recess RC1 formed in the pad PD1 can be selected according to the place where the pad PD1 is disposed. For this reason, the planar shape of the recess RC1 provided in one pad PD1 and the planar shape of the recess RC1 provided in another pad PD1 can be different from each other. Thereby, for example, the strength of the pad PD1 against a probe test or wire bonding can be improved.
In the example shown in FIG. 4, one pad PD1 is provided with a recess RC1 extending in the first direction, and the other pad PD1 is a recess RC1 extending in a second direction orthogonal to the first direction. Is provided. As a result, as shown in FIG. 4, the pad PD1 arranged along one side of the rectangular semiconductor chip SC1 is formed so that the recess RC1 extends in a direction perpendicular to the one side. be able to. By forming the recess RC1 in this manner, for example, in a probe test in which a probe needle is brought into contact with the pad PD1 arranged along the one side in a direction orthogonal to the one side, the pad PD1 It becomes possible to suppress the occurrence of damage.

  In the present embodiment, the recess RC1 is formed in a contact region in contact with the bonding wire BW1 in the pad PD1. Thereby, the area of the recess RC1 occupying the pad PD1 can be increased more efficiently. For this reason, the expansion and contraction of the pad PD1 during the temperature cycle can be more effectively suppressed. FIG. 1 illustrates a case where only a part of the recess RC1 provided on the pad PD1 is located in a contact region in contact with the bonding wire BW1. On the other hand, all of the recesses RC1 provided on the pad PD1 may be located in the contact area.

The depth D of the recess RC1 may be, for example, _{1/3 × T P ≦ D} ≦ 2/3 × T P. By setting the depth D to be equal to or greater than the lower limit, the volume of the pad PD1 can be efficiently reduced, and the expansion and contraction of the pad PD1 during the temperature cycle can be effectively suppressed. Further, by setting the depth D to be equal to or less than the above upper limit value, the thickness of the pad PD1 under the recess RC1 can be sufficiently left, and the strength of the pad PD1 with respect to wire bonding and a probe test can be ensured. In the present embodiment, the depth D of the recess RC1 is preferably 450 nm or more, for example, and more preferably 600 nm or more. On the other hand, the depth D of the recess RC1 is preferably 1500 nm or less, and more preferably 1200 nm or less.

Further, the width W of the recess RC1 can be, for example, 1/10 × D ≦ W ≦ 1/2 × D. By setting the width W to be equal to or greater than the above lower limit value, the volume of the pad PD1 can be efficiently reduced, and the expansion and contraction of the pad PD1 during the temperature cycle can be effectively suppressed. On the other hand, by setting the width W to be equal to or less than the above upper limit value, the aspect ratio of the recess RC1 can be sufficiently increased. For this reason, as will be described later, it is easy to form the recess RC1 using an ARDE (Aspect Ratio Dependent Etch) effect. In the present embodiment, the width W of the recess RC1 is preferably 0.05 μm or more and 1 μm or less, for example.
Note that the width W of the recess RC1 refers to the length of the recess RC1 in a direction orthogonal to the extending direction of the recess RC1. When the planar shape of the recess RC1 is rectangular, the width W of the recess RC1 indicates the length of the short side of the recess RC1 in plan view.

  An embedded member BM1 is embedded in the recess RC1. Thereby, as described above, the expansion and contraction of the pad PD1 during the temperature cycle can be suppressed.

  As a material constituting the embedded member BM1, for example, a material having a lower thermal expansion coefficient than the material constituting the pad PD1 can be adopted. Thereby, the expansion and contraction of the pad PD1 during the temperature cycle can be effectively suppressed by the embedded member BM1. In addition, it is preferable that the material constituting the embedded member BM1 has a higher elastic modulus than the material constituting the pad PD1, for example, from the viewpoint of suppressing expansion and contraction of the pad PD1.

In the present embodiment, the embedded member BM1 can be made of, for example, an inorganic insulating film. Thereby, the thermal expansion coefficient of the embedded member BM1 can be made sufficiently lower than that of the pad PD1. Further, the elastic modulus of the embedded member BM1 can be made sufficiently higher than that of the pad PD1. Furthermore, the adhesion between the pad PD1 containing Al and the embedded member BM1 can be improved. The inorganic insulating film is composed of one or more selected from, for example, SiO ₂ , SiN, and SiON. In this embodiment, the inorganic insulating film is formed by laminating a single layer structure composed of any one selected from SiO ₂ film, SiN film, and SiON film, or two or more selected from these. It can be set as the laminated structure formed.

  FIG. 1 illustrates the case where the embedded member BM1 is provided so as to embed only a part of the recess RC1 in the thickness direction. Here, the embedding member BM1 embeds only the lower side of the recess RC1. In this case, the upper end side of the inner wall of the recess RC1 is exposed without being covered by the embedded member BM1. For this reason, it is possible to secure a sufficient contact area of the bonding wire BW1 with respect to the pad PD1 and to reduce the contact resistance. On the other hand, the embedding member BM1 may embed the entire recess RC1. Thereby, it is possible to more effectively suppress the expansion and contraction of the pad PD1 during the temperature cycle.

The thickness _{T B} of the embedded members BM1 may be, for example, a _{1/3 × D ≦ T B} ≦ 2/3 × D. The thickness T _B by the above-described lower limit, it is possible to more effectively suppress the expansion and contraction of the pad PD1 during temperature cycling. On the other hand, by setting the thickness T _B and than the above upper limit, it is possible to the contact area with the pads PD1 bonding wires BW1 and sufficient to reduce the contact resistance more effectively. In the present embodiment, the thickness _{T B} of the embedded members BM1 is preferably set to 150nm or more, and more preferably to 300nm or more. On the other hand, the thickness _{T B} of the embedded members BM1 is preferably set to 1000nm or less, and more preferably to 600nm or less.

In the present embodiment, it is more preferable that the recess RC1 and the embedded member BM1 are formed so as to satisfy (D−T _B ) ≧ 2 × W. As a result, the contact area of the bonding wire BW1 with respect to the pad PD1 can be made equal to or greater than when the recess RC1 is not formed. Therefore, it is possible to improve the temperature cycle resistance while reducing the contact resistance of the pad PD1.

FIG. 13 is a cross-sectional view showing a modification of the semiconductor device SD1 shown in FIG.
In FIG. 1, the case where the upper surface of embedding member BM1 is flat is illustrated. On the other hand, the upper surface of the embedded member BM1 may be, for example, convex or concave. As shown in FIG. 13A, by making the upper surface of the embedded member BM1 concave, the contact area between the embedded member BM1 and the recessed portion RC1 can be efficiently increased. For this reason, it becomes possible to more effectively suppress the expansion and contraction of the pad PD1 during the temperature cycle. On the other hand, as shown in FIG. 13B, the contact area between the bonding wire BW1 and the recess RC1 can be efficiently increased by making the upper surface of the embedded member BM1 convex. For this reason, the contact resistance of the pad PD1 can be more effectively reduced. Note that the convexity of the upper surface of the embedded member BM1 refers to the case where the central portion of the upper surface is located above the outer peripheral portion that contacts the pad PD1. Further, that the upper surface of the embedded member BM1 is concave refers to the case where the central portion of the upper surface is located below the outer peripheral portion that contacts the pad PD1. The shape of the upper surface of the embedded member BM1 can be selected, for example, by appropriately controlling the etching conditions in the process of etching the insulating layer IL3 and leaving the embedded member BM1 in the manufacturing method described later. is there.

  The semiconductor device SD1 can include, for example, an insulating layer IL3 provided between the insulating layer IL1 and the insulating layer IL2 and positioned around the pad PD1. The insulating layer IL3 can function as a protective film that covers, for example, the uppermost wiring including the pad PD1. The insulating layer IL3 is made of, for example, the same material as the embedded member BM1. In this case, the embedded member BM1 can be embedded in the recess RC1 simultaneously with the protective film protecting the uppermost layer wiring. Therefore, an increase in the number of manufacturing steps can be suppressed.

  Insulating layer IL3 is provided, for example, on insulating layer IL1 and pad PD1, and has an opening OP2 that exposes a region of pad PD1 where recess RC1 is provided. In the present embodiment, for example, the insulating layer IL3 is provided so that all the recesses RC1 provided in the pad PD1 are exposed from the opening OP2. The insulating layer IL3 is provided so as to cover the outer periphery of the pad PD1.

The thickness of the insulating layer IL3 and _{T 3,} if the thickness of the portion where the recess RC1 is not provided within the pads PD1 was _{T P, T 3} is, for example, less 2/3 × _{T P.} Thereby, the thickness of the insulating layer IL3 can be reduced, which contributes to the reduction in thickness of the semiconductor device SD1. According to the present embodiment, even when the insulating layer IL3 is such a thin film, the expansion and contraction of the pad PD1 during the temperature cycle can be suppressed, so that the generation of cracks in the insulating layer IL3 is suppressed. It is possible. In the present embodiment, the thickness _{T 3} of the insulating layer IL3 is preferably for example at 1000nm or less, more preferably 800nm or less. On the other hand, the thickness _{T 3} of the insulating layer IL3 is preferably 200nm or more, and more preferably 400nm or more.

  An insulating layer IL2 is provided on the insulating layer IL1 and the pad PD1. FIG. 1 illustrates the case where the insulating layer IL2 is provided over the insulating layer IL3 and the pad PD1. The insulating layer IL2 has an opening OP1 that exposes a region including the recess RC1 in the pad PD1. In the present embodiment, for example, the insulating layer IL2 is provided so that all the recesses RC1 provided in the pad PD1 are exposed from the opening OP1. The opening OP1 is provided to have the same planar shape as the opening OP2 provided in the insulating layer IL3, for example. The insulating layer IL2 is provided so as to cover the outer periphery of the pad PD1.

  Insulating layer IL2 is formed of, for example, an organic insulating film. The organic insulating film includes, for example, polyimide. The thickness of the insulating layer IL2 is not particularly limited, but can be, for example, 3 μm or more and 30 μm or less.

  The semiconductor device SD1 includes a bonding wire BW1 that contacts the pad PD1 exposed from the opening OP1. In the present embodiment, one end of the bonding wire BW1 is in contact with a portion exposed from the opening OP1 in the pad PD1, and is electrically connected to the pad PD1. Although the material which comprises bonding wire BW1 is not specifically limited, For example, at least one of Au and Cu can be included.

  In the example shown in FIG. 1, at least a part of the recess RC1 is provided in a contact region in contact with the bonding wire BW1 in the pad PD1. In addition, the recess RC1 according to this example is only partially embedded in the thickness direction with the embedded member BM1, and the other part is not embedded with the embedded member BM1. In this case, a part of the bonding wire BW1 is embedded in the recess RC1. As a result, a sufficient contact area between the bonding wire BW1 and the pad PD1 can be secured, and the contact resistance of the pad PD1 can be effectively reduced.

  The semiconductor device SD1 includes a sealing resin ER1 that is provided on the insulating layer IL2 and seals the bonding wire BW1. In the present embodiment, the sealing resin ER1 seals, for example, the semiconductor chip SC1 and the bonding wire BW1 connected to the semiconductor chip SC1. Although the material which comprises sealing resin ER1 is not specifically limited, For example, it is comprised by the hardened | cured material etc. of an epoxy resin composition.

FIG. 5 is a cross-sectional view showing the semiconductor device SD1 according to the present embodiment.
In the example shown in FIG. 5, the semiconductor device SD1 includes a semiconductor substrate SB1, a transistor TR1 provided on the semiconductor substrate SB1, and a multilayer wiring structure provided on the semiconductor substrate SB1. The pad PD1 is formed, for example, in the uppermost layer of the multilayer wiring structure. Note that the structure of the semiconductor device SD1 is not limited to that shown in FIG.

The semiconductor substrate SB1 can be, for example, a silicon substrate or a compound semiconductor substrate. The transistor TR1 includes, for example, a gate insulating film GI1 provided on the semiconductor substrate SB1, a gate electrode GE1 provided on the gate insulating film GI1, a sidewall SW1 provided on the side surface of the gate electrode GE1, a source drain And an impurity diffusion region IR1 constituting the region. Further, under the sidewall SW1, for example, an impurity diffusion region IR2 that constitutes an extension region is provided. The semiconductor substrate SB1 is provided with an element isolation region EI1 for isolating one transistor TR1 from another transistor TR1.
On the semiconductor substrate SB1, an interlayer insulating film II1 that covers the transistor TR1 is provided. In the interlayer insulating film II1, a contact plug CP1 connected to the impurity diffusion region IR1 of the transistor TR1 is provided.

  The number of wiring layers constituting the multilayer wiring structure is not particularly limited. FIG. 5 illustrates a case where the number of wiring layers is five. In the example shown in FIG. 5, an etching stopper film ES1 and an interlayer insulating film II2 are sequentially stacked on the interlayer insulating film II1, and a wiring IC1 is formed therein. The wiring IC1 can be a Cu wiring formed by a damascene method, for example. On the interlayer insulating film II2, an interlayer insulating film II3 in which a via plug VP1 connected to the wiring IC1 is embedded and an etching stopper film ES2 are sequentially formed. On the etching stopper film ES2, a wiring IC2, an interlayer insulating film II4 covering the wiring IC2, and an etching stopper film ES3 located on the interlayer insulating film II4 are provided. A via plug VP2 connected to the wiring IC2 is provided on the wiring IC2. On the etching stopper film ES3, a wiring IC3, an interlayer insulating film II5 covering the wiring IC3, and an etching stopper film ES4 located on the interlayer insulating film II5 are provided. A via plug VP3 connected to the wiring IC3 is provided on the wiring IC3. On the etching stopper film ES4, a wiring IC4, an interlayer insulating film II6 that covers the wiring IC4, and an etching stopper film ES5 located on the interlayer insulating film II6 are provided. A via plug VP4 connected to the wiring IC4 is provided on the wiring IC4. Note that the wiring IC2, the wiring IC3, and the wiring IC4 are not particularly limited, but may be, for example, Al wiring. In the example shown in FIG. 5, the etching stopper film ES5 forms the insulating layer IL1.

On the insulating layer IL1, a wiring IC5 which is the uppermost layer wiring in the multilayer wiring structure is provided. Wiring IC5 is provided, for example, in the same layer as pad PD1, and is electrically connected to pad PD1. In the present embodiment, the pad PD1 is configured by a part of the wiring IC5, for example. On the other hand, the wiring IC 5 and the pad PD1 may be electrically connected to each other through, for example, a wiring layer provided in another layer.
In the example shown in FIG. 5, the insulating layer IL3 is provided so as to cover the wiring IC5, for example, and functions as a protective film for the wiring IC5. Further, as described above, in the present embodiment, the embedded member BM1 can be formed from the same material as the insulating layer IL3. In this case, the embedded member BM1 can be embedded in the recess RC1 simultaneously with the protective film that protects the wiring IC5 that is the uppermost layer wiring. For this reason, an increase in the number of manufacturing steps due to the formation of the embedded member BM1 can be suppressed.

FIG. 6 is a plan view showing the configuration of the pad PD1 shown in FIG.
In the example shown in FIG. 6, the pad PD1 is constituted by one end of the wiring IC5. In this case, the wiring IC5 can be formed, for example, such that the width at the one end constituting the pad PD1 is wider than the width at the other portion. The structure of the wiring IC 5 is not limited to this, and the width of the one end and the width of the other portion may be equal to each other.

Next, a method for manufacturing the semiconductor device SD1 will be described.
7 to 10 are cross-sectional views showing a method for manufacturing the semiconductor device SD1 shown in FIG. The manufacturing method of the semiconductor device SD1 according to the present embodiment can be performed, for example, as follows. First, a pad PD1 containing Al is formed on the insulating layer IL1, and a recess RC1 that does not penetrate the pad PD1 is formed in the pad PD1. Next, an insulating layer IL3 is formed on the insulating layer IL1 and the pad PD1 so as to fill the recess RC1. Next, the insulating layer IL2 is formed over the insulating layer IL3. Next, the insulating layer IL2 and the insulating layer IL3 are etched to form an opening that exposes the region including the recess RC1 in the pad PD1 so that the insulating layer IL3 embedded in the recess RC1 remains. Next, the bonding wire BW1 is brought into contact with the pad PD1 exposed from the opening.
Hereinafter, a method for manufacturing the semiconductor device SD1 will be described in detail.

  First, as shown in FIG. 7A, a conductor film CF1 containing Al is formed on the insulating layer IL1. The conductor film CF1 is formed using a material constituting the pad PD1. The method for forming the conductor film CF1 is not particularly limited, and examples thereof include sputtering, CVD (Chemical Vorposition), ALD (Atomic Layer Deposition), and plating. The insulating layer IL1 is, for example, an interlayer insulating film, an etching stopper film, or a protective film that forms part of a multilayer wiring structure provided on the semiconductor substrate SB1.

  Next, as shown in FIG. 7B, a pad PD1 containing Al is formed on the insulating layer IL1, and a recess RC1 that does not penetrate the pad PD1 is formed in the pad PD1. The pad PD1 is formed together with the uppermost wiring layer, for example, by patterning the conductor film CF1 using lithography and etching.

In the present embodiment, for example, the conductor film CF1 is patterned to form the pad PD1, and at the same time, the recess RC1 can be formed in the pad PD1. This can be realized, for example, by using the ARDE effect when performing lithography using a mask having a mask pattern corresponding to the pad PD1 and a mask pattern corresponding to the recess RC1. That is, by controlling the shape of the mask pattern corresponding to the recess RC1 to increase the aspect ratio of the recess RC1, the etching rate in the recess RC1 is made slower than that in the other etching regions. As a result, the conductor film CF1 is patterned to form the pad PD1, and at the same time, the recess RC1 that does not penetrate the pad PD1 is formed. Thus, according to the present embodiment, the formation of the pad PD1 and the formation of the recess RC1 can be performed by one lithography. For this reason, it is possible to improve the temperature cycle resistance while suppressing an increase in the number of manufacturing steps.
On the other hand, in this embodiment, after the conductor film CF1 is patterned to form the pad PD1, the recess RC1 may be formed in the pad PD1 by further performing lithography and etching. In this case, the design of the recess RC1 becomes easier.

Next, as shown in FIG. 8A, an insulating layer IL3 is formed on the insulating layer IL1 and the pad PD1 so as to fill the recess RC1. The insulating layer IL3 is formed so as to cover the uppermost layer wiring provided in the same layer as the pad PD1 together with the pad PD1, for example.
Next, as illustrated in FIG. 8B, the insulating layer IL2 is formed over the insulating layer IL3.

Next, the insulating layer IL2 and the insulating layer IL3 are etched to form an opening that exposes the region including the recess RC1 in the pad PD1 so that the insulating layer IL3 embedded in the recess RC1 remains. The opening is constituted by an opening OP1 formed in the insulating layer IL2 and an opening OP2 formed in the insulating layer IL3. Further, the insulating layer IL3 remaining in the recess RC1 constitutes the embedded member BM1.
In the present embodiment, the process is performed as follows, for example.

First, as shown in FIG. 9A, the insulating layer IL2 is patterned using lithography. As a result, an opening OP1 that overlaps the region including the recess RC1 in the pad PD1 is formed in the insulating layer IL2.
Next, as shown in FIG. 9B, the insulating layer IL3 is etched using the insulating layer IL2 as a mask to form an opening OP2 that overlaps the opening OP1 in the insulating layer IL3. At this time, the insulating layer IL3 is etched so that at least a part of the insulating layer IL3 embedded in the recess RC1 remains. In the present embodiment, for example, after etching the insulating layer IL3 located on the pad PD1, a part of the insulating layer IL3 embedded in the recess RC1 can be removed by overetching of 30% to 70%.
FIG. 9B illustrates a case where the upper surface of the formed embedded member BM1 is flat. On the other hand, the upper surface of the embedded member BM1 may be, for example, convex or concave. That the upper surface of the embedded member BM1 is convex refers to the case where the central portion of the upper surface is located above the outer peripheral portion in contact with the pad PD1. Further, that the upper surface of the embedded member BM1 is concave refers to the case where the central portion of the upper surface is located below the outer peripheral portion that contacts the pad PD1. Note that the shape of the upper surface of the embedded member BM1 can be selected, for example, by appropriately controlling the etching conditions in the above-described process for etching the insulating layer IL3 to leave the embedded member BM1.

  In the present embodiment, after the opening for exposing the pad PD1 is formed, a probe test can be performed on the pad PD1 as shown in FIG. The probe test is performed, for example, by bringing the probe needle PN1 into contact with the pad PD1.

  Next, as shown in FIG. 10B, the bonding wire BW1 is brought into contact with the pad PD1 exposed from the opening constituted by the opening OP1 and the opening OP2. As a result, the semiconductor chip including the pad PD1 and the substrate on which the semiconductor chip is mounted are electrically connected to each other.

Thereafter, the bonding wire BW1 is sealed with the sealing resin ER1. In the present embodiment, for example, the semiconductor chip and the bonding wire BW1 are both sealed with the sealing resin ER1.
In this way, the semiconductor device SD1 shown in FIG. 1 is obtained.

(Second Embodiment)
FIG. 11 is a cross-sectional view showing a semiconductor device SD2 according to the second embodiment, and corresponds to FIG. 1 according to the first embodiment. The semiconductor device SD2 according to the present embodiment has the same configuration as the semiconductor device SD1 according to the first embodiment except for the configuration of the pad PD1.
Hereinafter, the semiconductor device SD2 will be described in detail.

  As shown in FIG. 11, in the semiconductor device SD2, the recess RC1 is not provided in the contact region CR1 in contact with the bonding wire BW1 in the pad PD1. Therefore, for example, the recess RC1 is provided in a portion of the pad PD1 exposed from the opening OP1 and the opening OP2 in a portion that does not contact the bonding wire BW1. According to the present embodiment, wire bonding is performed on a region where the recess RC1 of the pad PD1 is not provided. For this reason, wire bonding can be performed under the same conditions as when the recess RC1 is not formed. Therefore, it is not necessary to change the bonding conditions accompanying the formation of the recess RC1, and application to mass production is facilitated.

FIG. 12 is a plan view showing an example of a planar structure of the pad PD1 according to the present embodiment.
FIG. 12A illustrates a case where the recess RC1 is provided in a lattice shape except for the contact region CR1 that contacts the bonding wire BW1. The contact region CR1 is not provided with the recess RC1. The length of the unit cell is not particularly limited, but can be, for example, 0.1 μm or more and 3.0 μm or less.
FIG. 12B illustrates a case where a frame-shaped recess RC1 surrounding the contact region CR1 is provided. Here, the plurality of recesses RC1 are provided apart from each other. The plurality of recesses RC1 are arranged from the center of the pad PD1 toward the outside. Although the space | interval of adjacent recessed part RC1 is not specifically limited, For example, it can be 0.05 micrometer or more and 3.0 micrometers or less.
Note that the planar shape of the recess RC1 and the number of the recesses RC1 are not limited to those shown in FIG.

  Also in this embodiment, the same effect as that of the first embodiment can be obtained.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

SD1, SD2 Semiconductor device SC1 Semiconductor chip SUB Substrate DP1 Die pad OL1 Outer lead SB1 Semiconductor substrate PD1 Pad CR1 Contact region CF1 Conductive film BW1 Bonding wire PN1 Probe needle RC1 Recess BM1 Embedding member IL1, IL2, IL3 Insulating layer ER1 Sealing resin OP1 , OP2 opening TR1 transistor GE1 gate electrode GI1 gate insulating film SW1 sidewall IR1, IR2 impurity diffusion region CP1 contact plug VP1, VP2, VP3, VP4 via plug IC1, IC2, IC3, IC4, IC5 wirings II1, II2, II3, II4 II5, II6 Interlayer insulating film ES1, ES2, ES3, ES4, ES5 Etching stopper film

Claims (18)

A pad provided on the first insulating layer, including Al and having a recess that does not penetrate;
An embedded member embedded in the recess;
A second insulating layer provided on the first insulating layer and the pad, and having an opening that exposes a region of the pad including the recess;
A semiconductor device comprising: The semiconductor device according to claim 1,
The embedded member is a semiconductor device configured by an inorganic insulating film. The semiconductor device according to claim 2,
The inorganic insulating _film, SiO _{2, SiN,} and a semiconductor device constituted by one or more selected from SiON. The semiconductor device according to claim 1,
The embedding member is a semiconductor device in which only a part of the recess is embedded in the thickness direction. The semiconductor device according to claim 1,
A semiconductor device comprising a third insulating layer provided between the first insulating layer and the second insulating layer, located around the pad, and made of the same material as the embedded member. The semiconductor device according to claim 5,
A wiring provided on the first insulating layer and electrically connected to the pad;
The third insulating layer is a semiconductor device provided to cover the wiring. The semiconductor device according to claim 5,
The thickness of the recess is not provided portion of the pad and T _P, wherein the thickness of the third insulating layer as a T _3, the semiconductor device T ₃ is equal to or less than 2/3 × T _P. The semiconductor device according to claim 5,
The thickness of the said 3rd insulating layer is a semiconductor device which is 1000 nm or less. The semiconductor device according to claim 1,
A bonding wire that contacts the pad is formed on the pad exposed from the opening,
A semiconductor device, wherein a sealing resin for sealing the bonding wire is provided on the second insulating layer. The semiconductor device according to claim 9.
The recess is a semiconductor device formed in a contact region in contact with the bonding wire in the pad. The semiconductor device according to claim 9.
The recess is not provided in a contact region in contact with the bonding wire in the pad. The semiconductor device according to claim 1,
A plurality of the pads,
One of the pads is provided with the recess extending in the first direction, and the other pad is provided with the recess extending in a second direction orthogonal to the first direction. . The semiconductor device according to claim 1,
The upper surface of the embedded member is a semiconductor device in which a central portion is located above an outer peripheral portion that contacts the pad. The semiconductor device according to claim 1,
The upper surface of the embedding member is a semiconductor device in which a central portion is positioned below an outer peripheral portion that contacts the pad. Forming a pad containing Al on the first insulating layer, and forming a recess in the pad that does not penetrate the pad;
Forming a third insulating layer on the first insulating layer and on the pad so as to be embedded in the recess;
Forming a second insulating layer on the third insulating layer;
Etching the second insulating layer and the third insulating layer to form an opening for exposing a region including the concave portion of the pad so that the third insulating layer embedded in the concave portion remains. Forming, and
A method for manufacturing a semiconductor device comprising: In the manufacturing method of the semiconductor device according to claim 15,
A method of manufacturing a semiconductor device, further comprising a step of bringing a bonding wire into contact with the pad exposed from the opening. In the manufacturing method of the semiconductor device according to claim 15,
After the step of forming the opening, the upper surface of the third insulating layer embedded in the recess is a method for manufacturing a semiconductor device in which a central portion is located above an outer peripheral portion that contacts the pad. In the manufacturing method of the semiconductor device according to claim 15,
After the step of forming the opening, the upper surface of the third insulating layer embedded in the recess is a method for manufacturing a semiconductor device in which a central portion is located below an outer peripheral portion that contacts the pad.

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