JP5564557B2 - Semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device and a manufacturing technique thereof, and more particularly to a technology for suppressing or preventing a crack from occurring in an insulating film under an external terminal due to an external force applied to the external terminal of the semiconductor device.

  In the manufacturing process of a semiconductor device, a probe inspection process for inspecting electrical characteristics of a semiconductor device by applying a probe to a bonding pad (hereinafter simply referred to as a pad) that is an external terminal of a semiconductor chip formed on a semiconductor wafer. However, the external force (impact) applied to the pad at that time causes a crack in the insulating film under the pad, which causes a problem that the reliability of the semiconductor device is lowered.

  Japanese Patent Laying-Open No. 2005-50963 (Patent Document 1) discloses a configuration in which a stress buffer layer is formed using an aluminum wiring layer immediately below a bonding pad.

  Further, as a technique for suppressing or preventing cracks under the pad as described above, for example, Japanese Patent Laying-Open No. 2005-109491 (Patent Document 2) includes a reinforcing layer formed of a refractory metal under a contact pad. Further, there is disclosed a configuration in which a first metal layer formed of copper or aluminum having the same size as the pad is provided below. As the reinforcing layer, a configuration using a plurality of refractory metals arranged in a line at regular intervals or a refractory metal having a lattice pattern is disclosed.

  Further, for example, in Japanese Patent Application Laid-Open No. 2003-324122 (Patent Document 3), a 1 μm thick reinforcing layer having the same size as a pad made of tungsten or a tungsten alloy is embedded in an interlayer insulating film under a bonding pad. A configuration is disclosed.

  Further, for example, Japanese Patent Laid-Open No. 2002-324797 (Patent Document 4) discloses a configuration in which a refractory metal layer is provided in contact with a first pad and a second pad is provided in contact with the refractory metal layer. Has been. The refractory metal layer is buried in a pad opening formed in the insulating film on the first pad, and is provided in contact with the first pad and the second pad. The first pad is about the same size as the second pad.

  For example, Japanese Patent Laid-Open No. 10-199925 (Patent Document 5) discloses a structure in which a tungsten structure is embedded in an insulating layer under a pad. In this patent document 5, a structure in which a plurality of tungsten structures arranged side by side at a predetermined interval are provided in contact with the lower surface of the pad, or a tungsten structure is provided in a state where the pad is not in contact with the wiring layer immediately below the pad. The structure to provide is disclosed.

  Further, for example, in Japanese Patent Application Laid-Open No. 2003-68740 (Patent Document 6), a laminated film having a concave cross section formed of tungsten between a pad and a wiring in a wiring layer immediately below the pad is in contact with the pad and the wiring. A configuration provided in such a state is disclosed. Tungsten and the wiring layer immediately below it are about the same size as the pad.

JP 2005-50963 A JP 2005-109491 A JP 2003-324122 A JP 2002-324797 A Japanese Patent Laid-Open No. 10-199925 JP 2003-68740 A

Recently, in order to reduce the area of the semiconductor chip, elements and wirings are arranged below the pads. For this reason, it is an important issue how to prevent the insulating film under the pad from cracking. Therefore, when an element or the like is disposed below the pad, a stress buffer layer is formed of the same material as that of the wiring layer immediately below the pad, as in Patent Documents 1 to 6, or the elastic modulus is higher than that of SiO _2. Therefore, it is necessary to reinforce with tungsten or refractory metal which is high in plasticity and difficult to plastically deform.

  However, according to the study of the present inventor, as in Patent Document 1, when a stress buffer layer is formed directly under the pad using the same metal (aluminum or copper) as the wiring layer, the impact caused when the probe is applied to the pad The present inventors have found that the stress buffer layer is plastically deformed, which causes a problem that the insulating film in the wiring layer cracks and propagates to the lower layer. Furthermore, as in Patent Documents 2 to 6, it has been found that there are the following problems even when used as a reinforcing layer of tungsten or a refractory metal. First, as in Patent Documents 2, 4, and 6, in a structure in which a wiring layer (aluminum or copper) is in contact directly under tungsten or a refractory metal, tungsten or refractory metal is caused by plastic deformation of the wiring layer. Cracks are generated and propagate to the lower layer. The plastic deformation increases as the width of the wiring layer directly below increases, and cracks are particularly prominent at the same size as the pad (30 to 100 μm). Secondly, as in Patent Documents 2 and 5, if there is a portion where tungsten is present and a portion where tungsten is not present, a crack is generated at the interface and propagates to the lower layer. Thirdly, as in Patent Document 3, when tungsten having high stress is formed thickly, tungsten is peeled off by the stress itself.

  On the other hand, in all areas in the chip including under the pads, it is possible to adjust the pattern occupancy to a certain degree by arranging dummy patterns made of wiring materials in the portions where the wiring pattern density of each wiring layer is low. It is common. This is because if there is a region with a low occupancy ratio, a difference in height occurs in the CMP process, and a lithographic focus shift occurs in the upper layer.

  When no element or wiring is arranged directly under the pad, it is conceivable to install a dummy pattern directly under the pad for the above purpose. However, according to the study of the present inventor, if there is a dummy pattern directly under the pad, the dummy pattern (wiring material) is plastically deformed and a crack is generated in the insulating film due to the impact when the probe is applied to the pad. We found that there is a problem of propagation to the lower layers.

  If cracks exist in the insulating film in the wiring layer as described above, moisture enters from there and there is a problem that the reliability of the device and the wiring is lowered. Furthermore, there is a problem in that wire bonds and bumps are subjected to a force due to thermal stress after packaging, and the pad portion is peeled off from the crack portion as a starting point to cause disconnection.

  Such a problem of cracking or peeling becomes prominent particularly when a low dielectric constant film (Low-k film) having low mechanical strength is used as the insulating film of the wiring layer.

  On the other hand, as a method of suppressing or preventing the crack, there is a method of reducing the probe needle pressure during the probe inspection process. However, when the needle pressure is reduced, the contact resistance between the probe and the pad increases, and the electrical resistance of the semiconductor device is increased. As a result, it becomes impossible to accurately measure the characteristics, resulting in a problem that the reliability of the semiconductor device is lowered.

  An object of the present invention is to provide a technique capable of suppressing or preventing the occurrence of cracks in an insulating film below an external terminal due to an external force applied to the external terminal of the semiconductor device.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in this application, the outline of one embodiment will be briefly described as follows.

  That is, in the present embodiment, the first external terminal formed in the uppermost wiring layer in the wiring layer immediately below the uppermost wiring layer among the plurality of wiring layers formed on the main surface of the semiconductor substrate. A conductor pattern is not formed directly under the region, and a conductor pattern is formed except under the first region of the external terminal.

  The outline of another embodiment of the invention disclosed in the present application will be briefly described as follows.

  That is, in the present embodiment, the lower surface of the external terminal is directly below the first region of the external terminal formed in the uppermost wiring layer of the plurality of wiring layers formed on the main surface of the semiconductor substrate. A conductor pattern having a concave cross section formed of a refractory metal, a refractory metal nitride, or a laminate thereof is in contact with the lower surface of the external terminal and has a boundary in the first region of the external terminal. In the wiring layer immediately below the uppermost wiring layer, there is no conductor pattern immediately below the first region of the external terminal and the conductor pattern having a concave cross section.

  Among the inventions disclosed in the present application, effects obtained by one embodiment will be briefly described as follows.

  That is, it is possible to suppress or prevent the generation of cracks in the insulating film below the external terminal due to the external force applied to the external terminal of the semiconductor device.

It is a principal part top view of the semiconductor chip of the semiconductor device which is one embodiment of this invention. The left side is a cross-sectional view taken along the line Y1-Y1 in the internal region of the semiconductor chip in FIG. 1, and the right side is a cross-sectional view taken along the line X1-X1 in the pad arrangement region of the semiconductor chip in FIG. It is an expanded sectional view of the wiring layer in the broken line A of FIG. It is an expanded sectional view of the wiring layer in the broken line B of FIG. FIG. 7 is a plan view of a principal portion showing a layout of a conductor pattern of a fifth wiring layer in the vicinity of a pad formation region of the semiconductor chip of FIG. 1. FIG. 4 is a plan view of relevant parts showing a layout of a conductor pattern of a fourth wiring layer in the vicinity of a pad formation region of the semiconductor chip of FIG. 1; It is principal part sectional drawing of the semiconductor chip which this inventor examined. FIG. 8 is a plan view of relevant parts showing a layout of a conductor pattern of a fifth wiring layer in the vicinity of a pad formation region of the semiconductor chip of FIG. 7; FIG. 8 is a plan view of a principal portion showing a layout of a conductor pattern of a fourth wiring layer in the vicinity of a pad formation region of the semiconductor chip of FIG. 7. FIG. 7 is a cross-sectional view of an internal region (left side) and a pad arrangement region (right side) of a semiconductor substrate during the manufacturing process of the semiconductor device described in FIGS. FIG. 11 is a cross-sectional view of an internal region (left side) and a pad arrangement region (right side) of a semiconductor substrate during the manufacturing process of the semiconductor device following FIG. 10; FIG. 12 is a cross-sectional view of the internal region (left side) and the pad arrangement region (right side) of the semiconductor substrate during the manufacturing process of the semiconductor device following FIG. 11; FIG. 13 is a cross-sectional view of the inner region (left side) and the pad arrangement region (right side) of the semiconductor substrate during the manufacturing process of the semiconductor device following FIG. 12; FIG. 14 is a cross-sectional view of the internal region (left side) and the pad arrangement region (right side) of the semiconductor substrate during the manufacturing process of the semiconductor device following FIG. 13; FIG. 15 is a cross-sectional view of the internal region (left side) and the pad arrangement region (right side) of the semiconductor substrate during the manufacturing process of the semiconductor device following FIG. 14; FIG. 9 is a plan view of relevant parts showing a layout of a conductor pattern of a fifth wiring layer in the vicinity of a pad formation region in a modification of the semiconductor chip of FIG. FIG. 9 is a plan view of relevant parts showing a layout of a conductor pattern of a fourth wiring layer in the vicinity of a pad formation region in a modification of the semiconductor chip of FIG. 1. The left side is a sectional view of a portion corresponding to the Y1-Y1 line of FIG. 1 in the internal region of the semiconductor chip of the semiconductor device according to another embodiment (Embodiment 2) of the present invention, and the right side is a pad arrangement of the same semiconductor chip. It is sectional drawing of the location corresponded to the X1-X1 line | wire of the area | region of FIG. FIG. 19 is a plan view of relevant parts showing the layout of the conductor pattern of the fifth wiring layer in the vicinity of the pad formation region of the semiconductor chip of FIG. 18; FIG. 19 is a plan view of relevant parts showing the layout of the conductor pattern of the fourth wiring layer in the vicinity of the pad formation region of the semiconductor chip of FIG. 18; It is principal part sectional drawing of the semiconductor chip which this inventor examined. It is principal part sectional drawing of the semiconductor chip which this inventor examined. FIG. 19 is a plan view of relevant parts showing a layout of a conductor pattern of a fifth wiring layer in the vicinity of a pad formation region in a modification of the semiconductor chip of FIG. 18; The left side is a cross-sectional view of a portion corresponding to the Y1-Y1 line of FIG. 1 in the internal region of the semiconductor chip of the semiconductor device of another embodiment (third embodiment) of the present invention, and the right side is a pad arrangement region of the same semiconductor chip. It is sectional drawing of the location corresponded to the X1-X1 line | wire of FIG. FIG. 25 is a substantial part plan view showing a layout of a conductor pattern of a fifth wiring layer in the vicinity of a pad formation region of the semiconductor chip of FIG. 24; FIG. 25 is a substantial part plan view showing a layout of a conductor pattern of a fourth wiring layer in the vicinity of a pad formation region of the semiconductor chip of FIG. 24; The left side is a cross-sectional view of a portion corresponding to the Y1-Y1 line of FIG. 1 in the internal region of the semiconductor chip of the semiconductor device of another embodiment (Embodiment 4) of the present invention, and the right side is a pad arrangement region of the same semiconductor chip. It is sectional drawing of the location corresponded to the X1-X1 line | wire of FIG. FIG. 28 is an enlarged cross-sectional view of the main part of the uppermost wiring layer in the pad arrangement region of the semiconductor chip of FIG. 27. It is sectional drawing of the pad arrangement | positioning part of the uppermost wiring layer of the semiconductor device which this inventor examined. FIG. 29 is a cross-sectional view of an internal region (left side) and a pad arrangement region (right side) of the substrate during the manufacturing process of the semiconductor device described in FIGS. 27 and 28; FIG. 29 is a cross-sectional view of an internal region (left side) and a pad arrangement region (right side) of a substrate during a manufacturing process subsequent to FIG. 30 of the semiconductor device described in FIG. 27 and FIG. 28; FIG. 31 is a cross-sectional view of an internal region (left side) and a pad arrangement region (right side) of a substrate during a manufacturing process subsequent to FIG. 31 of the semiconductor device described in FIGS. 27 and 28; FIG. 29 is a cross-sectional view of an internal region (left side) and a pad arrangement region (right side) of a substrate during a manufacturing process subsequent to FIG. 32 of the semiconductor device described in FIGS. 27 and 28; The left side is a cross-sectional view of a portion corresponding to the Y1-Y1 line of FIG. 1 in the internal region of the semiconductor chip of the semiconductor device of another embodiment (Embodiment 5) of the present invention, and the right side is a pad arrangement region of the same semiconductor chip. It is sectional drawing of the location corresponded to the X1-X1 line | wire of FIG. The left side is a sectional view of a portion corresponding to the Y1-Y1 line of FIG. 1 in the internal region of the semiconductor chip of the semiconductor device of another embodiment (sixth embodiment) of the present invention, and the right side is a pad arrangement region of the same semiconductor chip. It is sectional drawing of the location corresponded to the X1-X1 line | wire of FIG. The left side is a sectional view of a portion corresponding to the Y1-Y1 line of FIG. 1 in the internal region of the semiconductor chip of the semiconductor device of another embodiment (Embodiment 7) of the present invention, and the right side is a pad arrangement region of the same semiconductor chip. It is sectional drawing of the location corresponded to the X1-X1 line | wire of FIG. FIG. 37 is a substantial part plan view showing a layout of a conductor pattern of a fifth wiring layer in the vicinity of a pad formation region of the semiconductor chip of FIG. 36; FIG. 25 is a substantial part plan view showing a layout of a conductor pattern of a fourth wiring layer in the vicinity of a pad formation region of the semiconductor chip of FIG. 24; It is a principal part top view which shows the layout of the conductor pattern of the 5th wiring layer in the pad formation area vicinity of the semiconductor chip which this inventor examined. The left side is a sectional view of a portion corresponding to the Y1-Y1 line of FIG. 1 in the internal region of the semiconductor chip of the semiconductor device of another embodiment (Embodiment 8) of the present invention, and the right side is a pad arrangement region of the same semiconductor chip. It is sectional drawing of the location corresponded to the X1-X1 line | wire of FIG. FIG. 41 is a plan view of relevant parts showing the layout of the conductor pattern of the fourth wiring layer in the vicinity of the pad formation region of the semiconductor chip of FIG. 40; The left side is a cross-sectional view of a portion corresponding to the Y1-Y1 line of FIG. 1 in the internal region of the semiconductor chip of the semiconductor device according to another embodiment (Embodiment 9) of the present invention, and the right side is a pad arrangement region of the same semiconductor chip. It is sectional drawing of the location corresponded to the X1-X1 line | wire of FIG. 43 is a plan view of relevant parts showing the layout of the conductor pattern of the fifth wiring layer in the vicinity of the pad formation region of the semiconductor chip of FIG. 42; FIG. FIG. 43 is a plan view of relevant parts showing a layout of a conductor pattern of a fifth wiring layer in the vicinity of a pad formation region in a modification of the semiconductor chip of FIG. 42; The left side is a cross-sectional view of a portion corresponding to the Y1-Y1 line of FIG. 1 in the internal region of the semiconductor chip of the semiconductor device of another embodiment (Embodiment 10) of the present invention, and the right side is a pad arrangement region of the same semiconductor chip. It is sectional drawing of the location corresponded to the X1-X1 line | wire of FIG. FIG. 46 is a plan view of relevant parts showing the layout of the conductor pattern of the fourth wiring layer in the vicinity of the pad formation region of the semiconductor chip of FIG. 45; The left side is a cross-sectional view of a portion corresponding to the Y1-Y1 line of FIG. 1 in the internal region of the semiconductor chip of the semiconductor device of another embodiment (Embodiment 11) of the present invention, and the right side is a pad arrangement region of the same semiconductor chip. It is sectional drawing of the location corresponded to the X1-X1 line | wire of FIG. FIG. 48 is a substantial part plan view showing the layout of the conductor pattern of the fifth wiring layer in the vicinity of the pad formation region of the semiconductor chip of FIG. 47; The left side is a sectional view of a portion corresponding to the Y1-Y1 line of FIG. 1 in the internal region of the semiconductor chip of the semiconductor device of another embodiment (Embodiment 12) of the present invention, and the right side is a pad arrangement region of the same semiconductor chip. It is sectional drawing of the location corresponded to the X1-X1 line | wire of FIG. FIG. 50 is a substantial part plan view showing the layout of the conductor pattern of the fourth wiring layer in the vicinity of the pad formation region of the semiconductor chip of FIG. 49; The left side is a sectional view of a portion corresponding to the Y1-Y1 line of FIG. 1 in the internal region of the semiconductor chip of the semiconductor device of another embodiment of the present invention (Embodiment 13), and the right side is a pad arrangement region of the same semiconductor chip. It is sectional drawing of the location corresponded to the X1-X1 line | wire of FIG. The left side is a cross-sectional view of a portion corresponding to the Y1-Y1 line in FIG. 1 in the internal region of the semiconductor chip of the semiconductor device of another embodiment (Embodiment 14) of the present invention, and the right side is a pad arrangement region of the same semiconductor chip. It is sectional drawing of the location corresponded to the X1-X1 line | wire of FIG. The left side is a sectional view of a portion corresponding to the Y1-Y1 line of FIG. 1 in the internal region of the semiconductor chip of the semiconductor device of another embodiment (fifteenth embodiment) of the present invention, and the right side is a pad arrangement region of the same semiconductor chip. It is sectional drawing of the location corresponded to the X1-X1 line | wire of FIG. The left side is a cross-sectional view of a portion corresponding to the Y1-Y1 line of FIG. 1 in the internal region of the semiconductor chip of the semiconductor device of another embodiment (Embodiment 16) of the present invention, and the right side is a pad arrangement region of the same semiconductor chip. It is sectional drawing of the location corresponded to the X1-X1 line | wire of FIG. FIG. 55 is a substantial part plan view showing the layout of the conductor pattern of the fifth wiring layer in the vicinity of the pad formation region of the semiconductor chip of FIG. 54; FIG. 55 is a substantial part plan view showing the layout of the conductor pattern of the fourth wiring layer in the vicinity of the pad formation region of the semiconductor chip of FIG. 54;

  In the following embodiments, when referring to the number of elements, etc. (including the number, numerical value, quantity, range, etc.), unless otherwise specified and in principle limited to a specific number in principle, It is not limited to the specific number, and it may be more or less than the specific number. Further, in the following embodiments, the constituent elements (including element steps and the like) are not necessarily indispensable unless otherwise specified and apparently essential in principle. Needless to say. Similarly, in the following embodiments, when referring to the shapes, positional relationships, etc. of the components, etc., the shapes are substantially the same unless otherwise specified, or otherwise apparent in principle. And the like are included. The same applies to the above numerical values and ranges. Also, components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiments, and the repetitive description thereof is omitted as much as possible.

  In the present embodiment, a bonding pad illustrating an external terminal is simply referred to as a pad. In addition, the refractory metal referred to in this embodiment refers to a metal having a higher melting point than copper.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

(Embodiment 1)
1 is a plan view of a principal part of a semiconductor chip of the semiconductor device according to the first embodiment, the left side of FIG. 2 is a cross-sectional view taken along line Y1-Y1 of the internal region of the semiconductor chip of FIG. FIG. 3 is an enlarged cross-sectional view of the wiring layer in the broken line A of FIG. 2, and FIG. 4 is an enlarged cross-sectional view of the wiring layer in the broken line B of FIG. . 1 indicates the first direction, and Y indicates the second direction orthogonal to the first direction X.

A semiconductor substrate (hereinafter simply referred to as a substrate) 1 constituting a semiconductor chip is formed of, for example, p-type silicon (Si) single crystal. On the main surface (first main surface) of the substrate 1, for example, a groove-shaped separation portion 2 is formed. The groove-type separation portion 2 is formed by embedding an insulating film such as silicon oxide (SiO ₂ or the like) in a groove dug in the main surface of the substrate 1.

  In the active region surrounded by the isolation portion 2, for example, a field effect transistor (hereinafter referred to as MIS • FET (Metal Insulator Semiconductor • FET)) Q represented by a MOS • FET (Metal Oxide Semiconductor • Field Effect Transistor) Such an integrated circuit element is formed.

  The MIS • FETQ includes a pair of source and drain semiconductor regions formed on the main surface of the substrate 1, a gate insulating film formed on the main surface of the substrate 1 between the pair of semiconductor regions, A gate electrode formed on the gate insulating film. In the first embodiment, as shown in FIG. 2, a case where a plurality of MIS • FETs Q are arranged not only in the internal region of the semiconductor chip but also in the pad arrangement region (directly under the pad PD) is illustrated. ing.

  On the main surface of the substrate 1, for example, seven wiring layers are formed. This wiring layer has a lowermost wiring layer ML, first to fifth wiring layers M1 to M5 (intermediate wiring layer), and an uppermost wiring layer MH. The number of wiring layers is not limited to this, and can be variously changed.

  The lowermost wiring layer ML has insulating films 3A, 4A, 3B, a lowermost wiring (conductor pattern) 5A, and a plug (connection portion) 6A.

  The insulating films 3A, 4A, and 3B are sequentially deposited on the main surface of the substrate 1 from the lower layer. The insulating films 3A and 3B are made of, for example, silicon oxide and have a function of insulating between conductor patterns (wiring, plug, and dummy wiring). The insulating film 4A thinner than these insulating films 3A and 3B is formed of, for example, silicon carbonitride (SiCN), and has a function of insulating conductor patterns (wiring, plugs and dummy wiring) and a function as an etching stopper. doing.

  The lowermost wiring 5A is formed by embedding a conductor film in a wiring groove formed in the insulating films 3B and 4A (embedded wiring or damascene wiring). The conductor film forming the lowermost wiring 5A has a main wiring member and a barrier metal film. The main wiring member is formed of a metal such as copper (Cu). For example, aluminum, silver (Ag), or tin (Sn) may be added to the main wiring member as a countermeasure against migration. The barrier metal film is provided between the main wiring member and the insulating film on the outer periphery (side surface side and bottom surface side) in contact with each member. This barrier metal film has a function of suppressing or preventing copper diffusion of the main wiring member and a function of improving the adhesion between the wiring and the insulating film. The barrier metal film is formed thinner than the main wiring member, and is formed of, for example, a laminated film of a tantalum nitride (TaN) film and a tantalum (Ta) film thereon. The tantalum nitride film is in contact with the insulating film, and the tantalum film is in contact with the main wiring member.

  The plug 6A is formed by embedding a conductor film in a contact hole formed in the insulating film 3A. The conductor film forming the plug 6A has a main wiring member and a barrier metal film. This main wiring member is formed of a refractory metal such as tungsten (W). The barrier metal is provided between the main wiring member and the insulating film on the outer periphery (side surface side and bottom surface side) in contact with each member. This barrier metal film has a function of triggering the growth of tungsten and a function of improving the adhesion between the wiring and the insulating film. The barrier metal film is formed thinner than the main wiring member, and is formed of, for example, a titanium nitride (TiN) film.

  The lowermost wiring 5A is electrically connected to the semiconductor region for the source / drain of the MIS • FETQ through the plug 6A.

  The first wiring layer M1 has insulating films 4B, 3C, 3D and a first wiring (conductor pattern) 5B.

  The insulating films 4B, 3C, 3D of the first wiring layer M1 are sequentially deposited from the lower layer on the insulating film 3B. The insulating film 3C is formed of a single layer film, and the insulating film 3D is formed of a laminated film of an insulating film 3D1 and an insulating film 3D2 thereon as shown in FIG. The insulating films 3C and 3D have a function of insulating between conductor patterns (wiring, plug and dummy wiring).

The insulating films 3C and 3D1 are formed of a low dielectric constant film (Low-k film). In the present embodiment, the low dielectric constant film refers to an insulating film whose relative dielectric constant is lower than that of silicon oxide (SiO ₂ ) (= 3.8 to 4.3). Refers to an insulating film lower than 3.3. Specific examples of the insulating films 3C and 3D1 include carbon-containing silicon oxide (SiOC (relative permittivity = 2.0 to 3.2)) and SILK (registered trademark) (relative permittivity = 2.7). , FLARE (registered trademark) (relative dielectric constant = 2.8), methyl group-containing silicon oxide (MSQ: methylsilsesquioxane), and porous MSQ.

The insulating film 3D2 is formed of, for example, silicon oxide (SiO _x typified by SiO ₂ ) or SiOC (carbon-containing silicon oxide). In the case of SiOC, the dielectric constant is the same as that of the insulating film 3D1. A SiOC film having a dielectric constant equal to or higher than that is used. The insulating film 3D2 has a function of protecting the low dielectric constant film (insulating films 3D1, 3C) when the embedded wiring (damascene wiring) is formed and a low dielectric constant film (insulating films 3D1, 3C). Has a function of improving the mechanical strength of the wiring layer including

  The insulating film 4B thinner than these insulating films 3C and 3D has a function of insulating between conductor patterns (wiring, plug and dummy wiring) and a function as an etching stopper. The insulating film 4B is made of, for example, SiCN (silicon carbonitride).

  The first wiring 5B is formed by embedding a conductor film in a wiring groove formed in the insulating film 3D and in a through hole formed in the insulating films 3C and 4B at the bottom of the wiring groove (embedding). Wiring or dual damascene wiring). That is, in the first wiring 5B, a wiring portion (conductor pattern) formed in the wiring groove and a plug portion (connecting portion) formed in the through hole are integrally formed. As shown in FIG. 3, the conductor film forming the first wiring 5B has a main wiring member MM1 and a barrier metal film BM1.

  The main wiring member MM1 is made of a metal such as copper (Cu). For example, aluminum, silver (Ag), or tin (Sn) may be added to the main wiring member MM1 as a countermeasure against migration.

  The barrier metal film BM1 is provided between the main wiring member MM1 and the insulating film on the outer periphery (side surface and bottom surface side) in contact with the respective members. The barrier metal film BM1 has a function of suppressing or preventing copper diffusion of the main wiring member MM1, and a function of improving the adhesion between the wiring and the insulating film. The barrier metal film BM1 is formed thinner than the main wiring member MM1, and is formed of, for example, a laminated film of a tantalum nitride (TaN) film and a tantalum (Ta) film thereon. The tantalum nitride film is in contact with the insulating film, and the tantalum film is in contact with the main wiring member MM1.

  The first wiring 5B is electrically connected to the lowermost wiring 5A through the plug portion.

  Note that the width (short direction length), thickness, pitch and adjacent spacing of the first wiring 5B are larger than the width (short direction length), thickness, pitch and adjacent spacing of the lowermost wiring 5A.

  The second wiring layer M2 has insulating films 4D, 3C, 3D and a second wiring (conductor pattern) 5C.

  The insulating films 4D, 3C, 3D of the second wiring layer M2 are sequentially deposited from the lower layer on the insulating film 3D of the first wiring layer M1. The configuration and function of the insulating films 3C and 3D of the second wiring layer M2 are the same as the configuration and function of the insulating films 3C and 3D of the first wiring layer M1 (see FIG. 3).

  The insulating film 4D thinner than the insulating films 3C and 3D of the second wiring layer M2 has a function of insulating between conductor patterns (wiring, plugs and dummy wiring) and a function as an etching stopper. The insulating film 4D of the second wiring layer M2 is made of, for example, SiCN (silicon carbonitride).

  The second wiring 5C is formed by embedding a conductor film in a wiring groove formed in the insulating film 3D and in a through hole formed in the insulating films 3C and 4D at the bottom of the wiring groove (embedding). Wiring or dual damascene wiring). That is, in the second wiring 5C, a wiring portion (conductor pattern) formed in the wiring groove and a plug portion (connecting portion) formed in the through hole are integrally formed. The material configuration of the second wiring 5C is the same as that of the first wiring 5B (see FIG. 3). The second wiring 5C is electrically connected to the first wiring 5B through the plug portion.

  The configuration of the third wiring layer M3 is the same as the configuration of the second wiring layer M2. The configuration of the third wiring 5D of the third wiring layer M3 is the same as that of the second wiring 5C (see FIG. 3). The dimensions (width (short dimension), thickness, pitch, and adjacent interval) of the wirings from the first wiring layer M1 to the third wiring layer M3 (the first wiring 5B to the third wiring 5D) are equal to each other. The width and adjacent spacing of the first wiring 5B, the second wiring 5C, and the third wiring 5D are, for example, about 100 nm, and the thickness is, for example, about 200 nm.

  In the above example, the case where the insulating films 3C, 3D1, and 3D2 of the first wiring layer M1 to the third wiring layer M3 are formed of different films has been described. In this case, for example, the insulating film 3C is formed by the MSQ (for example, the relative dielectric constant = about 2.5), and the insulating film 3D1 is formed by the SILK (registered trademark) (the relative dielectric constant = about 2.7). The insulating film 3D2 can be formed of a SiOC film (for example, relative dielectric constant = about 3.0).

  As another form, in the insulating films 3C, 3D1, 3D2 of the first wiring layer M1 to the third wiring layer M3, the entire insulating films 3C, 3D1 are formed of the same low dielectric constant film (one low dielectric constant film). You can also. In this case, for example, the insulating film 3D2 is formed of an SiOC film (for example, a relative dielectric constant = about 3.0), and the entire insulating films 3C and 3D1 are made of another SiOC film having a lower dielectric constant than the insulating film 3D2 (for example, (Dielectric constant = approximately 2.5).

  As still another form, in the insulating films 3C, 3D1, 3D2 of the first wiring layer M1 to the third wiring layer M3, the entire insulating films 3C, 3D1, 3D2 are the same low dielectric constant film (one low dielectric constant film). It can also be formed. In this case, it is more preferable to use a film having relatively high CMP resistance as the low dielectric constant film. For example, the entire insulating films 3C, 3D1, and 3D2 can be formed of a SiOC film (for example, a relative dielectric constant of about 3.0).

  The fourth wiring layer M4 includes insulating films 4D, 3C, 3D and a fourth wiring (conductor pattern) 5E.

  The insulating films 4D, 3C, 3D of the fourth wiring layer M4 are sequentially deposited from the lower layer on the insulating film 3D of the third wiring layer M3. The insulating films 3C and 3D of the fourth wiring layer M4 are formed of, for example, a single film of silicon oxide, unlike the insulating films 3C and 3D of the first wiring layer M1 to the third wiring layer M3. That is, the insulating films 3C and 3D of the fourth wiring layer M4 do not have a low dielectric constant film (see FIG. 4). Further, in each of the fourth wiring layer M4 and the fifth wiring layer M5, the entire insulating films 3C and 3D can be formed of the same film (one film).

  The insulating film 4D thinner than the insulating films 3C and 3D of the fourth wiring layer M4 has a function of insulating between the conductor patterns (wiring, plugs and dummy wiring) and a function as an etching stopper. The insulating film 4D of the fourth wiring layer M4 is made of, for example, SiCN (silicon carbonitride).

  The configuration (excluding dimensions) of the fourth wiring 5E of the fourth wiring layer M4 is the same as the third wiring 5D of the third wiring layer M3 (embedded wiring or dual damascene wiring). The fourth wiring 5E is electrically connected to the third wiring 5D through the plug portion.

  The dimensions (width (short dimension), thickness, pitch, and adjacent interval) of the fourth wiring 5E are the first wiring 5B, the second wiring 5C, and the third wiring 5D of the first wiring layer M1 to the third wiring layer M3. Larger than the dimensions (width (dimension in the short direction), thickness, pitch, and adjacent spacing). The width and adjacent interval of the fourth wiring 5E are, for example, about 200 nm, and the thickness is, for example, about 400 nm.

  The configuration (excluding dimensions) of the fifth wiring layer M5 is the same as the configuration of the fourth wiring layer M4. The configuration of the fifth wiring 5F of the fifth wiring layer M5 is the same as that of the fourth wiring 5E (see FIG. 4). The dimensions (width (short dimension), thickness, pitch, and adjacent spacing) of the fifth wiring 5F of the fifth wiring layer M5 are the dimensions (width (short dimension)) of the fourth wiring 5E of the fourth wiring layer M4. Thickness, pitch and adjacent spacing). The width and the adjacent interval of the fifth wiring 5F are, for example, about 400 nm, and the thickness is, for example, about 800 nm.

  In the above example, the case where the insulating films 3C and 3D of the fifth wiring layer M5 are formed of a single film of silicon oxide has been described. However, one or both of the insulating films 3C and 3D of the fifth wiring layer M5 contain fluorine. It is also possible to use silicon oxide (FSG: Fluorinated Silicate Glass = SiOF). The relative dielectric constant of the fluorine-containing silicon oxide is larger than 3.3, for example, about 3.6 to 3.8. Further, in the fifth wiring layer M5, the entire insulating films 3C and 3D can be formed of the same film (one film), and in this case, a silicon oxide film or a fluorine-containing silicon oxide film can be used.

  In the above example, the case where the insulating films 3C and 3D of the fourth wiring layer M4 are formed of a single film of silicon oxide has been described. However, one or both of the insulating films 3C and 3D of the fourth wiring layer M4 are The fluorine-containing silicon oxide can also be used. In addition, in the fourth wiring layer M4, the entire insulating films 3C and 3D can be formed of the same film (one film). The film configuration of the insulating films 3C and 3D of the fourth wiring layer M4 is the same as the film configuration of the insulating films 3C and 3D of the first wiring layer M1 to the third wiring layer M3 (using a low dielectric constant film). Film structure).

  The uppermost wiring layer MH has insulating films 4D, 3E, and 3F, an uppermost wiring (conductor pattern) 5G, a pad PD, and a plug (connection portion) 6C.

  The insulating films 4D, 3E, and 3F are sequentially deposited from the lower layer on the insulating film 3D of the fifth wiring layer M5. The configuration and function of the insulating film 4D of the uppermost wiring layer MH are the same as the configuration and function of the insulating film 4D of the second wiring layer M2 to the fifth wiring layer M5. The insulating film 3E is made of, for example, silicon oxide, and has a function of insulating between conductor patterns (wiring, plug, and dummy wiring).

  The insulating film 3F is formed of, for example, a stacked body of a silicon oxide film, a silicon nitride film deposited thereon, and a polyimide resin film deposited thereon, and a conductor pattern (wiring, plug and dummy). It has a function of insulating the wiring) and a function as a surface protective film. The insulating film 3F covers the surface of the uppermost wiring 5G and a part of the surface of the pad PD. The vertical and horizontal dimensions W1 and L1 of the pad PD shown in FIG. 1 are, for example, about 30 to 100 μm (that is, approximately 30 μm ≦ W1 ≦ 100 μm, 30 μm ≦ L1 ≦ 100 μm).

  An opening S is formed in the insulating film 3F so that a part of the upper surface of the pad PD is exposed. The region exposed from the opening S on the upper surface of the pad PD is a region where an external member such as a bonding wire (hereinafter simply referred to as a wire), a bump, and a probe can contact the pad PD.

  In the present embodiment, as shown in FIG. 1, in the upper surface region of the pad PD exposed from the opening S, the region where the probe (probe) is in contact during the electrical characteristic test of the semiconductor chip is defined as the probe contact region (the first contact region). 1 area) PA. The planar dimension of the probe contact area PA is smaller than the area where the opening S is formed, but is preferably larger than the dimension of the probe mark left on the upper surface of the pad PD. In the first embodiment, the dimension of the contact surface (probe mark) at the tip of the probe is about 10 μm in diameter, so that the planar dimension of the probe contact area PA is preferably at least 10 μm × 10 μm or more. However, in consideration of misalignment between the probe and the pad PD, the size (planar dimension) of the probe contact area PA is more preferably 20 μm × 20 μm or more.

  In the upper surface region of the pad PD exposed from the opening S, a region including the probe contact region PA and the wire bonding region WA to which the wire is bonded is referred to as a wire inclusion region (first region) PWA. The planar dimension of the wire inclusion area PWA is smaller than the formation area of the opening S, but is preferably larger than the probe contact area PA and the wire bonding area WA (contact area of the wire (or bump)). In the first embodiment, since the dimension of the contact surface of the wire (or bump) is about 30 μm in diameter, the plane dimension of the wire inclusion region PWA is preferably at least 30 μm × 30 μm or more. However, in consideration of misalignment between the wire (or bump) and the pad PD, the size (planar dimension) of the wire inclusion region PWA is more preferably 40 μm × 40 μm or more.

  Further, the formation region of the opening S in the upper surface region of the pad PD (the entire region exposed from the opening S on the upper surface of the pad PD) is referred to as an opening formation region (first region) SA. In this case, it is not necessary to consider misalignment with the probe or wire (or bump).

  The uppermost wiring 5G and the pad PD are formed by patterning the same conductor film by a photolithography process and a dry etching process. As shown in FIG. 4, the conductor film forming the uppermost wiring 5G and the pad PD has a main wiring member MM2 and relatively thin barrier metal films BM2 and BM3 formed on the upper and lower surfaces thereof. . However, in the portion exposed from the opening S on the upper surface of the pad PD, the barrier metal film BM3 is removed, and the main wiring member MM2 is exposed.

  The main wiring member MM2 is made of aluminum, for example. For example, silicon or copper may be added to the main wiring member MM2 for migration countermeasures or the like.

  The barrier metal film BM2 on the lower surface side of the main wiring member MM2 has a function of suppressing the reaction between the material (aluminum) of the main wiring member and the lower wiring, and a function of improving the adhesion between the wiring and the insulating film. For example, it is formed of a laminated film of a titanium film, a titanium nitride film thereon, and a titanium film thereon.

  On the other hand, the barrier metal film BM3 on the upper surface side of the main wiring member MM2 has a function of improving the adhesion between the wiring and the insulating film, and a function as an antireflection film at the time of exposure in the photolithography process. It is formed of a titanium film.

  The plug 6C is formed by embedding a conductor film in a through hole formed in the insulating films 3E and 4D. The configuration (excluding dimensions) of the plug 6C is the same as that of the plug 6A. The plug 6C is electrically connected to the uppermost wiring 5G, the fifth wiring 5F, and the plug PD. That is, the uppermost wiring 5G and the pad PD are electrically connected to the lower fifth wiring 5F through the plug 6C.

  FIGS. 5 and 6 are plan views of main parts of the semiconductor chip of the semiconductor device according to the first embodiment. FIG. 5 shows a conductor pattern (fifth wiring 5F) of the fifth wiring layer M5 in the vicinity of the pad PD formation region. 6 shows an example of the layout of the dummy wiring DL), and FIG. 6 shows an example of the layout of the conductor pattern (the fourth wiring 5E and the dummy wiring DL) of the fourth wiring layer M4 in the vicinity of the pad PD formation region. ing. 5 and 6, the positions of the pad PD, the opening forming area SA, and the probe contact area PA are indicated by dotted lines.

  The dummy wirings DL shown in FIGS. 5 and 6 are provided to improve the flatness of each wiring layer and are generally formed at the same time as the wirings in the same layer. Is formed of an irrelevant conductor pattern. The dummy wiring DL is evenly arranged in the region where no wiring is arranged. Therefore, the dummy wiring DL of the fifth wiring layer M5 shown in FIG. 5 is formed in the same process as the fifth wiring 5F, and is arranged evenly in the region where the fifth wiring 5F is not arranged. Further, the dummy wiring DL of the fourth wiring layer M4 shown in FIG. 6 is formed in the same process as the fourth wiring 5E, and is arranged evenly in the region where the fourth wiring 5E is not arranged. In order to simplify the understanding, in the cross-sectional view of FIG. 2, the reference numeral DL of the dummy wiring is not attached, but a part of each wiring in the figure is a dummy wiring DL as necessary.

  In FIG. 5, among the fifth wirings 5F, a wiring having a width (wiring width) W2 larger than 2 μm (that is, W2> 2 μm) is denoted by 5Fa and is referred to as wiring 5Fa, and the width (wiring width) W2 is Reference numeral 5Fb is given to a wiring of 2 μm or less (that is, W2 ≦ 2 μm) and is referred to as wiring 5Fb. In FIG. 6, among the fourth wirings 5E, a wiring having a width (wiring width) W2 larger than 2 μm (that is, W2> 2 μm) is denoted by a reference numeral 5Ea and referred to as a wiring 5Ea. A wiring having W2 of 2 μm or less (that is, W2 ≦ 2 μm) is denoted by a reference numeral 5Eb and is referred to as a wiring 5Eb. The same applies to the following drawings.

  In the first embodiment, as can be seen from FIGS. 2, 5 and 6, the probe contact area PA (probe mark) of the pad PD in the fifth wiring layer M5 immediately below the uppermost wiring layer MH. A conductor pattern (the fifth wiring 5F, the dummy wiring DL, and the plug 6C) is not formed immediately below. In the fifth wiring layer M5, conductor patterns (fifth wirings 5F, dummy wirings DL, and plugs 6C) are formed in regions of the pad PD other than immediately below the probe contact region PA. That is, in the fifth wiring layer M5, the conductor pattern including the fifth wiring 5F and the dummy wiring DL is preferably arranged evenly in a region other than directly below the probe contact area PA. In the first embodiment, conductor patterns (wirings, dummy wirings, plugs) are formed in the lowermost wiring layer ML to the fourth wiring layer M4 even immediately below the probe contact area PA of the pad PD. The case is shown.

  The reason for such a configuration will be described with reference to FIGS. FIG. 7 shows a cross-sectional view of a main part of a semiconductor chip (semiconductor chip of a comparative example) examined by the present inventor, and shows a cross-sectional view corresponding to the cross-sectional view on the right side of FIG. Yes. 8 and 9 are main part plan views of the semiconductor chip of FIG. 7 (semiconductor chip of the comparative example) examined by the present inventors, and are plan views corresponding to FIGS. 5 and 6 of the present embodiment. It is shown. Therefore, FIG. 8 shows an example of the layout of the conductor pattern (fifth wiring 5F and dummy wiring DL) of the fifth wiring layer M5 in the vicinity of the pad PD formation region of the semiconductor chip of FIG. 7 (semiconductor chip of the comparative example). FIG. 9 shows an example of the layout of the conductor pattern (fourth wiring 5E and dummy wiring DL) of the fourth wiring layer M4 in the vicinity of the pad PD formation region.

  In the semiconductor chip of the comparative example shown in FIGS. 7 to 9, the fifth wiring 5F is formed immediately below the probe contact area PA of the pad PD in the fifth wiring layer M5 immediately below the uppermost wiring layer MH. . As described above, the fifth wiring 5F is formed of a buried wiring having copper as the main wiring member MM2.

  In this case, when the tip of the probe PRB of the test device is pressed against the probe contact area PA of the pad PD in the electrical characteristic test of the semiconductor chip, the fifth wiring just below the probe contact area PA of the pad PD is caused by the load applied from the probe PRB. 5F undergoes plastic deformation. As a result, there is a problem that stress is applied to the insulating film 3E immediately below the pad PD and further to the insulating film 3C immediately below the fifth wiring 5F, and cracks CLK are generated in the insulating films 3E and 3C. When copper or aluminum is used as the wiring material for the wiring layer directly under the pad PD, the elastic modulus (70 GPa and 130 GPa, respectively) of copper or aluminum is less than twice the elastic modulus (70 GPa) of the silicon oxide film, and is oxidized. Since the plastic film is more easily plastically deformed than the silicon film, the problem of the crack CLK becomes remarkable. Further, when the low dielectric constant film is used as the insulating material of the wiring layer as described above, the low dielectric constant film has a low mechanical strength, so that the problem of the crack CLK becomes remarkable.

  In the technique of Patent Document 1, a stress buffer layer is formed using an aluminum wiring layer immediately below a bonding pad. However, in this case as well, there is a problem that the stress buffer layer is plastically deformed by the impact when the probe is applied to the pad, and this causes a problem that the insulating film in the wiring layer cracks and propagates to the lower layer. The inventor found out.

  In the technique of Patent Document 2, a reinforcing layer formed of a refractory metal is provided below the contact pad layer, and further, a first layer formed of copper or aluminum having the same size as the pad is provided below the reinforcing layer. The metal layer is provided. In the technique of this Patent Document 2, since a refractory metal structure arranged in a fixed interval or a refractory metal structure having a lattice pattern is used as a reinforcing layer, the load applied when the probe is pressed against the contact pad layer is used. Stress concentrates on the boundary (edge) of the pattern of the tungsten structure, cracks are generated near the boundary (edge) of the pattern, and propagate to the lower layer. In addition, since the first metal layer immediately below the reinforcing layer is plastically deformed, the cracks become more prominent.

  In the technique disclosed in Patent Document 3, a 1 μm thick reinforcing layer having the same size as a pad made of tungsten or a tungsten alloy is embedded in an interlayer insulating film below the pad. However, in this case, the reinforcing layer itself is thick and may be peeled off due to the stress of the reinforcing layer itself.

  The technique of Patent Document 4 discloses a configuration in which a refractory metal layer is provided in contact with the second pad, and the first pad is further provided in contact with the refractory metal layer. However, in this case as well, the first pad is made of aluminum, and since the first pad and the second pad are of the same size, the melting point is increased by the load when the probe is pressed against the second pad. Plastic deformation occurs in the first pad under the metal layer, and a crack occurs in the insulating film.

  In the technique of the above-mentioned patent document 5, a structure is disclosed in which a tungsten structure arranged in a fixed interval is buried in an insulating layer under a pad so as to be in contact with the lower surface of the pad. However, in this case, stress concentrates on the boundary (edge) of the pattern of the tungsten structure, cracks are generated near the boundary (edge) of the pattern, and propagate to the lower layer.

  The technique of Patent Document 6 discloses a configuration in which a laminated body having a concave cross section formed of tungsten is provided in contact with the pad and the wiring between the pad and the wiring in the wiring layer immediately below the pad. Yes. However, in this case as well, since the wiring under the pad is made of an aluminum alloy and is about the same size as the pad, plastic deformation is caused in the wiring under the laminate by the load when the probe is pressed against the pad. The resulting insulating film is cracked.

  In addition, after bonding wires (or bumps) to the pad PD and further packaging, the wire bond and bumps are affected by the difference in thermal expansion coefficient between the semiconductor chip and the package material (resin or substrate), and the crack portion As a starting point, there is also a problem that the pad part is peeled off to cause disconnection.

  In contrast, in the first embodiment, as shown in FIGS. 2 and 5, in the fifth wiring layer M5 immediately below the uppermost wiring layer MH, the probe contact area PA (probe trace) of the pad PD is used. The conductor pattern (the fifth wiring 5F, the dummy wiring DL, and the plug 6C) is not provided immediately below the bracket.

  That is, in the fifth wiring layer M5, there is no conductor pattern (a wide pattern of the same size (30 to 100 μm) as the pad) immediately below the probe contact area PA of the pad PD, and insulation such as silicon oxide. Since only the film is formed, even if the probe PRB is pressed against the pad PD, it is difficult to be plastically deformed, and cracks are hardly generated in the insulating film. In the fifth wiring layer M5, since there is no conductor pattern boundary (edge) immediately below the probe contact area PA of the pad PD, the insulating film caused by stress concentration on the conductor pattern boundary (edge) is not present. No cracks occur.

  Therefore, it is possible to suppress or prevent a problem that the crack CLK is generated in the insulating film under the pad PD due to the external force applied to the pad PD during the probe inspection. For this reason, the yield and reliability of the semiconductor device can be improved.

  Further, the conductor pattern disposition prohibiting region in the fifth wiring layer M5 can be limited to the probe contact region PA. That is, the fifth wiring 5F and the dummy wiring DL can be disposed under the pad PD in the region other than the probe contact region PA. Further, since the fifth wiring layer M5 is not provided with a wide conductor pattern (a wide pattern as large as the pad, an impact buffering pattern, etc.) formed by the damascene method immediately below the probe contact area PA of the pad PD. In the fifth wiring layer M5, the fifth wiring 5F can be arranged close to the arrangement prohibition area of the conductor pattern immediately below the probe contact area PA of the pad PD. As a result, the degree of freedom of the arrangement of the fifth wiring 5F in the fifth wiring layer M5 can be improved. Therefore, the wiring design of the semiconductor chip can be facilitated. Further, since the detour arrangement of the wiring can be reduced, the chip size can be reduced.

  Further, since the crack CLK can be suppressed or prevented, the problem that the wire (or bump) is peeled off due to the crack CLK can also be suppressed or prevented. For this reason, the yield and reliability of the semiconductor device can be improved.

  Further, in the electrical characteristic test of the semiconductor device, it is not necessary to reduce the probe needle pressure to suppress or prevent the crack CLK, so that the contact resistance between the probe and the pad can be reduced, and the electrical characteristics of the semiconductor device can be reduced. Measurement accuracy can be improved. For this reason, the reliability of the semiconductor device can be improved.

  In the first embodiment, in the fourth wiring layer M4 just below the fifth wiring layer M5 just below the uppermost wiring layer MH, the probe contact area PA (probe trace) of the pad PD is just below the probe contact area PA. It is preferable that a conductor pattern (wiring 5Ea, dummy wiring DL and plug) having a width larger than 2 μm is not formed. In the fourth wiring layer M4, a conductor pattern (wiring 5Eb, dummy wiring DL and plug) having a width of 2 μm or less is arranged (formed) immediately below the probe contact area PA of the pad PD. . In FIG. 6, in the fourth wiring layer M4, the wiring 5Eb having a width (wiring width) of 2 μm or less is arranged immediately below the probe contact area PA of the pad PD, but the width (wiring width) larger than 2 μm. The wiring 5Ea having () is not disposed immediately below the probe contact area PA of the pad PD, but is disposed in an area other than directly below the probe contact area PA.

  Since the fourth wiring 5E is farther from the pad PD than the fifth wiring 5F, it is more difficult to plastically deform than the fifth wiring 5F. However, if the probe needle pressure is high, the fourth wiring 5E is plastically deformed and a crack is generated in the insulating film. there is a possibility. For this reason, as described above, in the fourth wiring layer M4, this plastic deformation is achieved by limiting the width of the conductor pattern (fourth wiring 5E) disposed immediately below the probe contact area PA of the pad PD to 2 μm or less. Is further suppressed, the probe can be brought into contact with the pad PD with a higher needle pressure, and the test (probe inspection) can be further stabilized. This also applies to the following fourth and fourth embodiments.

  Next, a method for manufacturing the semiconductor device according to the first embodiment will be described with reference to FIGS. 10 to 15 are cross-sectional views of the internal region (left side) and the pad arrangement region (right side) of the substrate 1 during the manufacturing process of the semiconductor device described with reference to FIGS.

  First, as shown in FIG. 10, a substrate 1 (a plane called a semiconductor wafer at this stage) having a main surface (first main surface) and a back surface (second main surface) positioned on opposite sides along the thickness direction. Prepare a circular semiconductor thin plate).

  Subsequently, after forming the groove-type isolation portion 2 on the main surface of the substrate 1, a plurality of elements (for example, MIS • FETQ) are formed in the active region surrounded by the isolation portion 2.

  Thereafter, a plurality of wiring layers are formed on the main surface of the substrate 1. A method of forming this wiring layer will be described with reference to FIGS. FIG. 11 shows a state where up to the fourth wiring layer M4 is formed. Here, since the formation method of the first wiring layer M1 to the fifth wiring layer M5 is the same, the formation method of the first wiring layer M1 to the fifth wiring layer M5 will be described by taking the formation method of the fifth wiring layer M5 as an example. .

  That is, as shown in FIG. 11, the insulating films 4D, 3C, 3D of the fifth wiring layer M5 are formed on the insulating film 3D of the fourth wiring layer M4 by the CVD (Chemical Vapor Deposition) method (in the case where there is a low dielectric constant film). In some cases, a coating method or the like may be used). Subsequently, as shown in FIG. 12, the wiring trench LV is formed in the wiring formation region of the insulating film 3D of the fifth wiring layer M5, and the insulating films 3C and 4D of the fifth wiring layer M5 are formed from the bottom of the wiring trench LV from the bottom. A through hole TH reaching the upper surface of the 4 wiring 5E is formed by a photolithography process and a dry etching process. The photolithography process refers to a series of processes such as application of a photoresist film, exposure and development.

  At this time, the etching selection ratio between the insulating films 3C and 3D and the insulating film 4D is increased. Thus, the insulating film 4D functions as an etching stopper when the insulating films 3D and 3C are etched, and the insulating films 3D and 3C are prevented from being etched when the insulating film 4D is etched.

  In the first embodiment, the wiring groove LV and the through hole TH are not formed under the probe contact area PA in the fifth wiring layer M5.

  Thereafter, as shown in FIG. 13, a conductor film 5 is deposited on the main surface of the substrate 1 so as to fill the wiring trench LV and the through hole TH. The conductor film 5 is obtained by sequentially depositing the barrier metal film BM1 and the main wiring member MM1 from the lower layer. The barrier metal film BM1 is deposited by a sputtering method or the like. The main wiring member MM1 is deposited by a sputtering method, a plating method, or the like. That is, a thin seed layer made of, for example, copper is first deposited by sputtering or the like, and then a conductor film made of, for example, copper is deposited on the seed layer by plating or the like.

  Next, portions of the conductor film 5 outside the wiring groove LV and the through hole TH are removed by a chemical mechanical polishing (CMP) method, thereby forming the wiring groove LV and the through hole as shown in FIG. A fifth wiring 5F formed of the conductor film 5 is formed in TH.

  In the first embodiment, in the fifth wiring layer M5 immediately below the uppermost wiring layer MH, the fifth wiring 5F and the plug 6C are not formed immediately below the probe contact area PA of the pad PD.

  The bottom wiring 5A is formed by a single damascene technique, but the basic formation process is the same as the method of forming the first wiring 5B to the fifth wiring 5F.

  Subsequently, as shown in FIG. 15, the insulating films 4D and 3E are sequentially formed from the lower layer on the main surface of the substrate 1 so as to cover the upper surface of the insulating film 3D and the fifth wiring 5F of the fifth wiring layer M5. After the deposition is performed, a through hole TH is formed in the insulating films 3E and 4D, and a plug 6C is formed in the same manner as the fifth wiring 5F.

  Thereafter, the barrier metal film BM2, the main wiring member MM2, and the barrier metal film BM3 are formed on the main surface of the substrate 1 by sputtering or the like so as to cover the upper surface of the insulating film 3E of the uppermost wiring layer MH and the plug 6C. After sequentially depositing from the lower layer, this laminated conductor film is patterned by photolithography and etching to form the uppermost wiring (first conductor pattern) 5G and pad (first conductor pattern, external terminal) PD in the same process. To do.

  Next, a silicon oxide film and a silicon nitride film are sequentially deposited from the lower layer on the main surface of the substrate 1 so as to cover the uppermost wiring 5G and the pad PD, and a polyimide resin film is further applied thereon. After forming the insulating film 3F by deposition, an opening S is formed in the insulating film 3F so that a part of the pad PD is exposed. At this time, the uppermost barrier metal film BM3 portion of the pad PD exposed from the opening S is also removed.

  Subsequently, the probe PRB is brought into contact with the plurality of pads PD of each of the plurality of semiconductor chips on the main surface of the substrate 1 to inspect the electrical characteristics of the plurality of semiconductor chips on the substrate 1. At this time, in the first embodiment, in the fifth wiring layer M5 immediately below the uppermost wiring layer MH, a conductor pattern (fifth wiring 5F, dummy wiring) is intentionally placed immediately below the probe contact area PA of the pad PD. By not providing the DL and the plug 6C), it is possible to suppress or prevent the occurrence of cracks in the insulating film directly under the pad PD due to the load from the probe PRB. As a result, the yield and reliability of the semiconductor device can be improved.

  Thereafter, the semiconductor chip is cut out from the substrate 1 by performing a dicing process on the substrate 1. Thereafter, a wire is bonded to the wire bonding area WA of the pad PD of the semiconductor chip (when a bump is bonded to the pad PD, it is performed before the semiconductor chip is cut out from the semiconductor wafer). Thereafter, a semiconductor device is manufactured through a sealing process.

  16 and 17 are main part plan views showing modifications of the semiconductor chip of the semiconductor device according to the first embodiment, and correspond to FIGS. 5 and 6, respectively. That is, FIG. 16 shows an example of the layout of the conductor pattern (fifth wiring 5F and dummy wiring DL) of the fifth wiring layer M5 in the vicinity of the pad PD formation region, and FIG. 17 shows the vicinity of the pad PD formation region. An example of the layout of the conductor pattern (fourth wiring 5E and dummy wiring DL) of the fourth wiring layer M4 in FIG. 16 and 17, the positions of the pad PD, the opening forming area SA, and the probe contact area PA are indicated by dotted lines.

  In the modification of the first embodiment shown in FIGS. 16 and 17, the planar dimension (area) of the probe contact area PA is made larger than in the case of FIGS. For example, about half of the opening formation area SA (the right half of the opening formation area SA in FIG. 16) is used as the probe contact area PA. Other configurations are the same as those in FIGS. Therefore, also in the modified examples shown in FIGS. 16 and 17, the probe contact of the pad PD is made in the fifth wiring layer M5 immediately below the uppermost wiring layer MH, as in the case of FIGS. The conductor pattern (the fifth wiring 5F, the dummy wiring DL, and the plug 6C) is not formed immediately below the area PA (probe mark).

  In the modification of the first embodiment shown in FIG. 16 and FIG. 17, it is possible to obtain a margin for misalignment of the probe by increasing the planar dimension (area) of the probe contact area PA.

(Embodiment 2)
The left side of FIG. 18 is a cross-sectional view of a portion corresponding to the Y1-Y1 line of FIG. 1 in the internal region of the semiconductor chip of the semiconductor device of the second embodiment, and the right side is a pad arrangement region of the same semiconductor chip, X1- It is sectional drawing of the location corresponded to a X1 line. FIGS. 19 and 20 are plan views showing main parts of the semiconductor chip of the semiconductor device according to the second embodiment, which correspond to FIGS. 5 and 6, respectively. That is, FIG. 19 shows an example of the layout of the conductor pattern (fifth wiring 5F and dummy wiring DL) of the fifth wiring layer M5 in the vicinity of the pad PD formation region, and FIG. 20 shows the vicinity of the pad PD formation region. An example of the layout of the conductor pattern (fourth wiring 5E and dummy wiring DL) of the fourth wiring layer M4 in FIG. 19 and 20, the positions of the pad PD, the opening forming area SA, the probe contact area PA, and the wire bonding area WA are indicated by dotted lines, and the position of the wire inclusion area PWA is indicated by a one-dot chain line. .

  As can be seen from FIGS. 18 to 20, in the second embodiment, in the fifth wiring layer M5 immediately below the uppermost wiring layer MH, the wire inclusion area PWA (the probe contact area PA and the wire) of the pad PD. A conductor pattern (the fifth wiring 5F, the dummy wiring DL, and the plug 6C) is not formed immediately below the bonding area WA.

  In the fifth wiring layer M5, conductor patterns (fifth wirings 5F, dummy wirings DL, and plugs 6C) are formed in regions other than immediately below the wire inclusion region PWA of the pad PD. That is, in the fifth wiring layer M5, the conductor pattern including the fifth wiring 5F and the dummy wiring DL is preferably arranged evenly in a region other than immediately below the wire inclusion region PWA. In the second embodiment, a conductor pattern (wiring, dummy wiring, plug) is formed in the lowermost wiring layer ML to the fourth wiring layer M4 even immediately below the wire inclusion area PWA of the pad PD. ing.

  According to the second embodiment, the same effects as those of the first embodiment can be obtained, and the following effects can be obtained.

  First, the problems found by the present inventors will be described with reference to FIGS. FIGS. 21 and 22 are cross-sectional views of the main part of the semiconductor chip investigated by the present inventors.

  21 and 22, in the fifth wiring layer M5 immediately below the uppermost wiring layer MH, a plurality of fifth wirings 5F are also formed immediately below the wire inclusion region PWA of the pad PD. As described above, the fifth wiring 5F is formed of a buried wiring having copper as the main wiring member MM2.

  In this case, as shown in FIG. 21, when the wire WR (or bump) is bonded to the pad PD or when the bonding state of the wire WR (or bump) is inspected, the force shown by arrows D and E is applied. The fifth wiring 5F immediately below the wire bonding area WA of the pad PD is plastically deformed. As a result, stress concentrates on the boundary (edge) C of the fifth wiring 5F. Furthermore, as shown in FIG. 22, there is a problem that a crack CLK is generated to release stress and the wire WR (or bump) is peeled off.

  On the other hand, in the second embodiment, as shown in FIGS. 18 and 19, in the fifth wiring layer M5 immediately below the uppermost wiring layer MH, immediately below the wire inclusion area PWA of the pad PD. However, the conductor pattern (the fifth wiring 5F, the dummy wiring DL, and the plug 6C) is not provided.

  That is, in the fifth wiring layer M5, there is no conductor pattern (a wide pattern as large as the pad) directly below the wire inclusion area PWA of the pad PD, and only an insulating film such as silicon oxide is formed. Therefore, it is difficult to plastically deform and cracks are hardly generated in the insulating film. Further, in the fifth wiring layer M5, since there is no conductor pattern boundary (edge) immediately below the wire inclusion area PWA of the pad PD, the insulating film caused by stress concentration on the conductor pattern boundary (edge) is not present. No cracks occur.

  Therefore, it is possible to suppress or prevent the occurrence of the crack CLK in the insulating film under the pad PD due to the external force applied to the pad PD during bonding of the wire WR (or bump) or bonding inspection. The problem of the wire WR (or bump) peeling off can also be suppressed or prevented. For this reason, the yield and reliability of the semiconductor device can be improved.

  Further, although the disposition prohibition region of the conductor pattern under the pad PD in the fifth wiring layer M5 is wider than that in the first embodiment, the damascene method is provided immediately below the wire inclusion region PWA of the pad PD in the fifth wiring layer M5. In the fifth wiring layer M5, the conductor pattern located immediately below the wire inclusion area PWA is near the prohibited area of the conductor pattern, because the wide conductor pattern formed in (5) is not provided. The 5th wiring 5F can be arranged. For this reason, the fifth wiring 5F in the fifth wiring layer M5 is compared with the case where the wide fifth wiring 5F (wide pattern having the same size as the pad) formed by the damascene method is disposed under the pad PD. The degree of freedom of arrangement can be improved. Therefore, the wiring design of the semiconductor chip can be facilitated as compared with the case where the fifth wide wiring 5F (wide pattern having the same size as the pad) formed by the damascene method is disposed under the pad PD. . In addition, compared to the case where the fifth wide wiring 5F (wide pattern having the same size as the pad) formed by the damascene method is disposed under the pad PD, the detour arrangement of the wiring can be reduced, so that the chip size can be reduced. Can be reduced.

  In the second embodiment, in the fourth wiring layer M4 directly below the fifth wiring layer M5 immediately below the uppermost wiring layer MH, the wire inclusion area PWA (the probe contact area PA and the wire bonding) of the pad PD is provided. It is preferable that a conductor pattern (wiring 5Ea, dummy wiring DL, and plug) having a width larger than 2 μm is not formed immediately below the area including the area WA. In the fourth wiring layer M4, a conductor pattern (wiring 5Eb, dummy wiring DL and plug) having a width of 2 μm or less is arranged (formed) immediately below the wire inclusion area PWA of the pad PD. . In FIG. 20, in the fourth wiring layer M4, the wiring 5Eb having a width (wiring width) of 2 μm or less is arranged immediately below the wire inclusion area PWA of the pad PD, but the width (wiring width) larger than 2 μm. The wiring 5Ea having () is not arranged immediately below the wire inclusion area PWA of the pad PD, but is arranged in an area other than immediately below the wire inclusion area PWA.

  Since the fourth wiring 5E is farther from the pad PD than the fifth wiring 5F, it is more difficult to plastically deform than the fifth wiring 5F. However, if the probe needle pressure is high, the fourth wiring 5E is plastically deformed and a crack is generated in the insulating film. there is a possibility. For this reason, as described above, in the fourth wiring layer M4, the width of the conductor pattern (fourth wiring 5E) disposed immediately below the wire inclusion area PWA of the pad PD is limited to 2 μm or less, thereby making this plastic deformation. Is further suppressed, the probe can be brought into contact with the pad PD with a higher needle pressure, and the test (probe inspection) can be further stabilized. The same applies to the following fifth embodiment.

  FIG. 23 is a plan view showing a principal part of a modification of the semiconductor chip of the semiconductor device according to the second embodiment, and corresponds to FIG. That is, FIG. 23 shows an example of the layout of the conductor pattern (the fifth wiring 5F and the dummy wiring DL) of the fifth wiring layer M5 in the vicinity of the pad PD formation region.

  In the modification of the second embodiment shown in FIG. 23, the wire bonding area WA and the probe contact area PA are arranged so that at least a part thereof overlaps (planarly overlaps). Other configurations are the same as those in FIGS. Therefore, also in the modification of the second embodiment shown in FIG. 23, in the fifth wiring layer M5 immediately below the uppermost wiring layer MH, the pad PD is formed in the same manner as in the case of FIGS. The conductor pattern (the fifth wiring 5F, the dummy wiring DL, and the plug 6C) is not formed immediately below the wire inclusion area PWA (area including the probe contact area PA and the wire bonding area WA).

  As in the second embodiment, the conductor pattern (the fifth wiring 5F, the dummy wiring DL, and the plug is provided immediately below the wire inclusion area PWA (the area including the probe contact area PA and the wire bonding area WA) of the pad PD. 6C), the wire bonding area WA and the probe contact area PA are arranged so as to at least partially overlap (planarly overlap) as in the modification shown in FIG. You can also. As a result, the plane dimension (area) of the wire inclusion area PWA can be reduced by an amount corresponding to the overlap area between the two, thereby reducing the plane dimension (area) of the opening forming area SA and the pad PD. be able to. For this reason, the planar dimension (area) of the semiconductor chip can be reduced. In addition, since the probe contact area PA is not cracked by the probe, the wire bond and the bump are subjected to a force due to the thermal stress after the package, and the pad portion is peeled off from the crack portion of the probe contact area PA to cause a disconnection. There is no problem.

(Embodiment 3)
24 is a cross-sectional view of a portion corresponding to the Y1-Y1 line of FIG. 1 in the internal region of the semiconductor chip of the semiconductor device of the third embodiment, and the right side is a pad arrangement region of the same semiconductor chip, X1- It is sectional drawing of the location corresponded to a X1 line. FIGS. 25 and 26 are plan views showing the principal parts of the semiconductor chip of the semiconductor device according to the third embodiment, which correspond to FIGS. 5 and 6, respectively. That is, FIG. 25 shows an example of the layout of the conductor pattern (fifth wiring 5F and dummy wiring DL) of the fifth wiring layer M5 in the vicinity of the pad PD formation region, and FIG. 26 shows the vicinity of the pad PD formation region. An example of the layout of the conductor pattern (fourth wiring 5E and dummy wiring DL) of the fourth wiring layer M4 in FIG. 25 and 26, the positions of the pad PD, the opening forming area SA, and the probe contact area PA are indicated by dotted lines.

  As can be seen from FIGS. 24 to 26, in the third embodiment, in the fifth wiring layer M5 immediately below the uppermost wiring layer MH, the opening forming area SA (the wire inclusion area PWA of the pad PD is defined). The conductor pattern (the fifth wiring 5F, the dummy wiring DL, and the plug 6C) is not formed immediately below the included region.

  In the fifth wiring layer M5, conductor patterns (fifth wiring 5F, dummy wiring DL, and plug 6C) are formed in regions other than the region immediately below the opening formation region SA of the pad PD. That is, in the fifth wiring layer M5, the conductor pattern including the fifth wiring 5F and the dummy wiring DL is preferably arranged evenly in a region other than immediately below the opening forming region SA. In the third embodiment, conductor patterns (wirings, dummy wirings, plugs) are formed in the lowermost wiring layer ML to the fourth wiring layer M4 even immediately below the opening formation region SA of the pad PD. Has been.

  According to the third embodiment, the same effects as those of the first and second embodiments can be obtained.

  In the third embodiment, in the fourth wiring layer M4 directly below the fifth wiring layer M5 immediately below the uppermost wiring layer MH, the opening forming area SA (including the wire inclusion area PWA) of the pad PD is provided. It is preferable that a conductor pattern (wiring 5Ea, dummy wiring DL, and plug) having a width larger than 2 μm is not formed immediately below the region. In the fourth wiring layer M4, a conductor pattern (wiring 5Eb, dummy wiring DL and plug) having a width of 2 μm or less is arranged (formed) immediately below the opening forming area SA of the pad PD. To do. In FIG. 26, in the fourth wiring layer M4, the wiring 5Eb having a width (wiring width) of 2 μm or less is disposed immediately below the opening formation area SA of the pad PD, but a width (wiring) larger than 2 μm The wiring 5Ea having a width) is not disposed directly under the opening formation area SA of the pad PD, but is disposed in an area other than directly under the opening formation area SA.

  Since the fourth wiring 5E is farther from the pad PD than the fifth wiring 5F, it is more difficult to plastically deform than the fifth wiring 5F. However, if the probe needle pressure is high, the fourth wiring 5E is plastically deformed and a crack is generated in the insulating film. there is a possibility. Therefore, as described above, in the fourth wiring layer M4, by limiting the width of the conductor pattern (fourth wiring 5E) disposed immediately below the opening formation area SA of the pad PD to 2 μm or less, this plasticity is achieved. Deformation is further suppressed, the probe can be brought into contact with the pad PD with a higher needle pressure, and the test (probe inspection) can be further stabilized. The same applies to the sixth embodiment described below.

  Further, as a modification of the third embodiment, as in the modification of the second embodiment (FIG. 23), at least a part of the wire bonding area WA and the probe contact area PA overlap (planarly overlap). ) Can also be arranged. Thereby, the planar dimension (area) of the pad PD can be reduced, and the planar dimension (area) of the semiconductor chip can be reduced.

(Embodiment 4)
The left side of FIG. 27 is a cross-sectional view of a portion corresponding to the Y1-Y1 line of FIG. 1 in the internal region of the semiconductor chip of the semiconductor device of the fourth embodiment, and the right side is X1- of FIG. FIG. 28 is an enlarged cross-sectional view of the main part of the uppermost wiring layer in the pad arrangement region of the semiconductor chip of FIG. 27.

  Note that the conductor pattern (fifth wiring 5F and dummy wiring DL) of the fifth wiring layer M5 and the conductor pattern (fourth wiring 5E and dummy wiring) of the fourth wiring layer M4 in the vicinity of the pad PD formation region in the fourth embodiment. The layout of (DL) is substantially the same as that of the first embodiment (FIGS. 5 and 6), and is not shown here.

  In the fourth embodiment, as in the first embodiment, in the fifth wiring layer M5 immediately below the uppermost wiring layer MH, immediately below the probe contact area PA (probe mark) of the pad PD, Conductor patterns (fifth wiring 5F, dummy wiring DL and plug 6C) are not formed. Thereby, the same effect as the first embodiment can be obtained.

  In the fourth embodiment, the conductor pattern (second conductor pattern) 6M having a concave cross section is formed immediately below the probe contact area PA (probe mark) of the pad PD in contact with the lower surface of the pad PD. Yes. That is, in the fourth embodiment, a large hole THA is formed in the probe contact region PA in the insulating films 3E and 4D of the uppermost wiring layer MH, and the above-described concave cross section is formed in the hole THA. The conductor pattern 6M and a part of the conductor film of the pad PD are deposited (embedded) in order from the lower layer.

  The configuration of the conductor pattern 6M is the same as that of the plugs 6A and 6C. That is, as shown in FIG. 28, the conductor pattern 6M has a main wiring member MM0 and a barrier metal film BM0. The main wiring member MM0 of the conductor pattern 6M is formed of a refractory metal such as tungsten (W). The thickness of the main wiring member MM0 here is, for example, about 400 nm. The upper surface of the main wiring member MM0 of the conductor pattern 6M is in contact with the barrier metal film BM2 of the pad PD.

  The barrier metal film BM0 is provided between the main wiring member MM0 and the insulating film on the outer periphery (side surface side and bottom surface side) in contact with the respective members. The barrier metal film BM0 has a function of triggering the growth of tungsten and a function of improving the adhesion between the wiring and the insulating film.

  The barrier metal film BM0 is formed thinner than the main wiring member MM0, and is formed of, for example, a laminated film of a titanium (Ti) film and a titanium nitride (TiN) film thereon. The titanium film is in contact with the insulating film, and the titanium nitride film is in contact with the main wiring member MM0. The thickness of the barrier metal film BM0 here is, for example, about 60 nm.

  Examples of the material of the conductor pattern 6M include a refractory metal such as tungsten, titanium and tantalum, a refractory metal nitride such as tungsten nitride, titanium nitride and tantalum nitride, or two or more materials selected from these materials. You may form by the laminated body of.

  Tungsten and titanium have an elastic modulus of 400 GPa and 600 GPa, respectively, and more than twice the elastic modulus of silicon oxide of 70 GPa. Moreover, refractory metals such as tungsten and titanium are less susceptible to plastic deformation than aluminum and copper.

  As described above, in the fourth embodiment, the conductor pattern 6M having a concave cross section is provided immediately below the probe contact area PA of the pad PD, so that the probe PRB is pressed against the pad PD when the probe PRB is pressed against the pad PD. Since the stress applied to the insulating film immediately below can be dispersed, the crack suppressing or preventing effect of the insulating film can be further improved.

  The formation range (plane position and plane dimension) of the hole THA is the same as the plane range (plane position and plane dimension) of the probe contact area PA. For this reason, the formation range (plane position and plane dimension) of the conductor pattern 6M is also the same as the plane range (plane position and plane dimension) of the probe contact area PA. That is, the conductor pattern 6M is patterned so as not to have a boundary (edge) in the probe contact area PA. Therefore, even if the conductor pattern 6M is provided immediately below the probe contact area PA of the pad PD, the insulating film is not cracked due to stress concentration on the boundary (edge) of the conductor pattern.

  As a result, it is possible to further suppress or prevent the occurrence of cracks CLK in the insulating film under the pad PD due to the external force applied to the pad PD during probe inspection, thereby further improving the yield and reliability of the semiconductor device. it can.

  Further, the plane dimension of the hole THA is larger than the plane dimension of the through hole TH of the same wiring layer (the uppermost wiring layer MH), and the conductor pattern 6M does not completely fill the hole THA. It is larger than twice the thickness of the pattern 6M. Thereby, the conductor pattern 6M is formed in a concave shape so as to cover the insulating films 3E and 4D on the inner side surface and the bottom surface of the hole THA without filling the hole THA. That is, the conductor pattern 6M has a portion that is attached along the inner side surface of the hole THA and a portion that is attached along the bottom surface of the hole THA. In addition, corners are formed on the side where the constituent material of the pad PD contacts. The reason for this configuration will be described with reference to FIG.

  FIG. 29 shows a cross-sectional view of the pad arrangement portion of the uppermost wiring layer of the semiconductor device examined by the present inventors. As shown in FIG. 29, it is conceivable to fill the hole THA with the conductor film 6. The material of the conductor film 6 is the same as that of the conductor pattern 6M. However, the total thickness of the insulating films 3E and 4D between the pad PD and the uppermost wiring 5G and the fifth wiring 5F immediately below the pad PD is to prevent an increase in capacitance between the pad PD and the uppermost wiring 5G and the fifth wiring 5F. For example, the thickness is 600 nm or more. That is, the depth of the hole THA is 600 nm or more. For this reason, if the hole THA is completely filled with the conductor film 6, the conductor film 6 becomes too thick and the conductor film 6 may be peeled off by its own stress (arrow F).

  On the other hand, in the fourth embodiment, the conductor pattern 6M is formed in a concave shape so as to cover the insulating films 3E and 4D on the inner side surface and the bottom surface of the hole THA without filling the hole THA. Therefore, a large stress is not applied to the conductor pattern 6M. The conductor pattern 6M is formed in a cross-sectional shape having no continuity along the direction of the stress (arrow F) in FIG. That is, it is formed in a cross-sectional shape that divides the stress (arrow F) in FIG. By these, peeling of the conductor pattern 6M can be prevented.

  According to the study by the present inventor, it is known that the thickness of the conductor pattern may be set to, for example, 500 nm or less so that the conductor pattern 6M is not peeled off by its own stress. However, if the conductor pattern 6M is too thin, an effect sufficient to suppress or prevent cracks in the insulating film under the probe contact area PA cannot be obtained. According to the study of the present inventor, in order to obtain a sufficient effect for suppressing or preventing cracks in the insulating film under the probe contact area PA of the pad PD as described above, the thickness of the conductor pattern 6M is set to It has been found that the thickness is preferably larger than the thickness of the barrier metal films BM2 and BM3 of the pad PD, for example, 200 nm or more. Therefore, in the fourth embodiment, the thickness h1 of the conductor pattern 6M is preferably, for example, 200 nm to 500 nm. Since the depth of the hole THA is 600 nm or more, the thickness h2 of the outer peripheral portion of the conductor pattern 6M is, for example, 600 nm or more.

  In the fourth embodiment, the conductor pattern 6M is formed in a concave shape in cross section, and a part of the conductor film of the pad PD is embedded in the recess in a state in contact with the conductor pattern 6M. For this reason, the contact area between the conductor pattern 6M and the pad PD can be improved, and thus the adhesion between the conductor pattern 6M and the pad PD can be improved.

  As a modification of the fourth embodiment, in the fifth wiring layer M5 immediately below the uppermost wiring layer MH, a conductor pattern (fifth wiring) is provided immediately below the wire inclusion area PWA or the opening forming area SA of the pad PD. 5F, dummy wiring DL and plug 6C) may not be provided.

  Next, a method for manufacturing the semiconductor device of the fourth embodiment will be described with reference to FIGS. 30 to 33 are cross-sectional views of the internal region (left side) and the pad arrangement region (right side) of the substrate 1 during the manufacturing process of the semiconductor device described with reference to FIGS.

  First, through the same steps as described in FIGS. 10 to 14 of the first embodiment, as shown in FIG. 30, the main surface of the substrate 1 (planar circular semiconductor thin plate called a semiconductor wafer at this stage) A plurality of wiring layers are formed thereon. FIG. 30 shows a stage where up to the fifth wiring layer M5 is formed.

  Subsequently, as shown in FIG. 31, after the insulating films 4D and 3E are sequentially deposited on the upper surfaces of the insulating film 3D and the fifth wiring 5F of the fifth wiring layer M5 from the lower layer by the CVD method or the like, the insulating film 4D , 3E, through holes TH and holes THA are formed in the same process by photolithography and dry etching.

  The plane dimension of the hole THA is larger than the plane dimension of the through hole TH. From the bottom surface of the hole THA, the upper surface of the insulating film 3D of the fifth wiring layer M5 is exposed. A part of the upper surface of the fifth wiring 5F is exposed from the bottom of the through hole TH.

  When forming the through hole TH and the hole THA, first, the insulating film 3E is etched using the resist pattern as an etching mask, but this etching prevents the insulating film 4D from being etched. Next, after removing the resist pattern, the insulating film 4D is etched (at this time, the insulating film 3E functions as an etching mask). Thereby, it is possible to prevent the fifth-layer wiring 5F from being oxidized by the oxygen plasma treatment for removing the resist.

  Thereafter, as shown in FIG. 32, a conductor film 6 is deposited on the main surface of the substrate 1 on the insulating film 3E of the fifth wiring layer M5. The conductor film 6 is obtained by sequentially depositing the barrier metal film BM0 and the main wiring member MM0 from the lower layer. The barrier metal film BM0 is deposited by a sputtering method or the like. The main wiring member MM0 is deposited by a CVD method or the like.

  The planar dimension of the through hole TH is twice or less than the thickness of the conductor film 6, but the planar dimension of the hole THA is larger than twice the thickness of the conductor film 6. For this reason, the through hole TH is filled with the conductor film 6, but the hole THA is not completely filled with the conductor film 6.

  Next, by removing the through hole TH and the outside of the hole THA by the CMP method in the conductor film 6, as shown in FIG. 33, the plug 6C formed by the conductor film 6 is formed in the through hole TH. A conductor pattern (second conductor pattern) 6M formed of the conductor film 6 is formed in the hole THA.

  The subsequent steps are the same as in the first embodiment. That is, the uppermost wiring 5G and the pad PD shown in FIG. 27 are formed in the uppermost wiring layer MH in the same process. Subsequently, after forming the insulating film 3F so as to cover the uppermost wiring 5G and the pad PD, an opening S is formed in the insulating film 3F so that a part of the pad PD is exposed.

  Thereafter, the probe PRB is brought into contact with the plurality of pads PD of each of the plurality of semiconductor chips on the main surface of the substrate 1 to inspect the electrical characteristics of the plurality of semiconductor chips on the substrate 1. At this time, also in the fourth embodiment, as described above, it is possible to suppress or prevent the occurrence of cracks in the insulating film directly under the pad PD, so that the yield and reliability of the semiconductor device can be improved. it can.

  Thereafter, the substrate 1 is subjected to a dicing process, and individual semiconductor chips are cut out from the substrate 1. Then, wires are bonded to the pads PD of the semiconductor chips, and a semiconductor device is manufactured through a sealing process. When bonding bumps to the pad PD, the bumps are bonded to the pads in the chip formation region in the semiconductor wafer after the probe inspection, and then a dicing process is performed.

(Embodiment 5)
The left side of FIG. 34 is a cross-sectional view of a portion corresponding to the Y1-Y1 line of FIG. 1 in the internal region of the semiconductor chip of the semiconductor device of the fifth embodiment, and the right side is X1- of FIG. It is sectional drawing of the location corresponded to a X1 line.

  Note that the conductor pattern (fifth wiring 5F and dummy wiring DL) of the fifth wiring layer M5 and the conductive pattern (fourth wiring 5E and dummy wiring) of the fourth wiring layer M4 in the vicinity of the pad PD formation region in the fifth embodiment. The layout of (DL) is substantially the same as that of the second embodiment (FIGS. 19 and 20), and is not shown here.

  In the fifth embodiment, similarly to the second embodiment, in the fifth wiring layer M5 immediately below the uppermost wiring layer MH, a conductor pattern (first pattern) is directly below the wire inclusion area PWA of the pad PD. 5 wiring 5F, dummy wiring DL and plug 6C) are not formed. Thereby, the same effect as the second embodiment can be obtained.

  In the fifth embodiment, the conductor pattern 6M having a concave cross section is formed immediately below the wire inclusion area PWA of the pad PD in contact with the lower surface of the pad PD. That is, in the fifth embodiment, a large hole THA is formed in the wire inclusion region PWA in a wider range than the probe contact region PA in the insulating films 3E and 4D of the uppermost wiring layer MH. In the THA, the above-described conductor pattern 6M having a concave cross section and a part of the conductor film of the pad PD are sequentially deposited (embedded) from the lower layer.

  The configuration and the formation method of the hole THA and the conductor pattern 6M of the fifth embodiment are the same as those described in the fourth embodiment except for the planar dimensions. In the case of the fifth embodiment, the formation range (plane position and plane dimension) of the hole THA and the conductor pattern 6M is the same as the plane range (plane position and plane dimension) of the wire inclusion area PWA. That is, the conductor pattern 6M is patterned so as not to have a boundary (edge) in the wire inclusion region PWA. Therefore, even if the conductor pattern 6M is provided immediately below the wire inclusion area PWA of the pad PD, the insulating film does not crack due to stress concentration on the boundary (edge) of the conductor pattern.

  According to the fifth embodiment as described above, the generation of cracks CLK in the insulating film under the pad PD can be further suppressed or prevented as compared with the fourth embodiment. Reliability can be further improved. Other than this, the same effects as those of the fourth embodiment can be obtained.

  As a modification of the fifth embodiment, in the fifth wiring layer M5 immediately below the uppermost wiring layer MH, a conductor pattern (fifth wiring 5F, dummy wiring DL is formed immediately below the opening formation area SA of the pad PD. The plug 6C) may not be provided.

  Further, as a modification of the fifth embodiment, as in the modification of the second embodiment (FIG. 23), at least a part of the wire bonding area WA and the probe contact area PA overlap (planarly overlap). ) Can also be arranged. Thereby, the planar dimension (area) of the pad PD can be reduced, and the planar dimension (area) of the semiconductor chip can be reduced.

(Embodiment 6)
The left side of FIG. 35 is a cross-sectional view of a portion corresponding to the Y1-Y1 line of FIG. 1 in the internal region of the semiconductor chip of the semiconductor device of the sixth embodiment, and the right side is X1- of FIG. It is sectional drawing of the location corresponded to a X1 line.

  In the sixth embodiment, the conductive pattern (fifth wiring 5F and dummy wiring DL) of the fifth wiring layer M5 and the conductive pattern (fourth wiring 5E and dummy wiring) of the fourth wiring layer M4 in the vicinity of the pad PD formation region in the sixth embodiment. The layout of (DL) is substantially the same as that of the third embodiment (FIGS. 25 and 26), and is not shown here.

  In the sixth embodiment, similarly to the third embodiment, in the fifth wiring layer M5 immediately below the uppermost wiring layer MH, a conductor pattern ( The fifth wiring 5F, the dummy wiring DL, and the plug 6C) are not formed. As a result, the same effect as in the third embodiment can be obtained.

  In the sixth embodiment, the conductor pattern 6M having a concave cross section is formed immediately below the opening formation area SA of the pad PD in contact with the lower surface of the pad PD. That is, in the sixth embodiment, a large hole THA is formed in the opening forming area SA in a wider range than the probe contact area PA and the wire inclusion area PWA in the insulating films 3E and 4D of the uppermost wiring layer MH. In the hole THA, the above-described concave conductor pattern 6M and a part of the conductor film of the pad PD are deposited (embedded) in order from the lower layer.

  The configuration and the formation method of the hole THA and the conductor pattern 6M of the sixth embodiment are the same as those described in the fourth and fifth embodiments except for the planar dimensions. In the case of the sixth embodiment, the formation range (planar position and planar dimension) of the hole THA and the conductor pattern 6M is the same as the planar range (planar position and planar dimension) of the opening forming area SA. That is, the conductor pattern 6M is patterned so as not to have a boundary (edge) in the opening formation area SA. Therefore, even if the conductor pattern 6M is provided immediately below the opening formation area SA of the pad PD, the insulating film is not cracked due to stress concentration on the boundary (edge) of the conductor pattern.

  According to the sixth embodiment, since it is possible to further suppress or prevent the occurrence of cracks CLK in the insulating film under the pad PD, compared to the case of the fifth embodiment, the yield of the semiconductor device and Reliability can be further improved. Except for this, the same effects as in the fourth and fifth embodiments can be obtained.

  As a modification of the sixth embodiment, as in the modification of the second embodiment (FIG. 23), at least a part of the wire bonding area WA and the probe contact area PA overlap (planarly overlap). ) Can also be arranged. Thereby, the planar dimension (area) of the pad PD can be reduced, and the planar dimension (area) of the semiconductor chip can be reduced.

(Embodiment 7)
36 is a cross-sectional view of a portion corresponding to the Y1-Y1 line in FIG. 1 in the internal region of the semiconductor chip of the semiconductor device of the seventh embodiment, and the right side is a pad arrangement region of the same semiconductor chip in FIG. It is sectional drawing of the location corresponded to a X1 line. FIG. 37 and FIG. 38 are main part plan views showing the semiconductor chip of the semiconductor device according to the seventh embodiment, and correspond to FIG. 5 and FIG. 6, respectively. That is, FIG. 37 shows an example of the layout of the conductor pattern (fifth wiring 5F and dummy wiring DL) of the fifth wiring layer M5 in the vicinity of the pad PD formation region, and FIG. 38 shows the vicinity of the pad PD formation region. An example of the layout of the conductor pattern (fourth wiring 5E and dummy wiring DL) of the fourth wiring layer M4 in FIG. 37 and 38, the positions of the pad PD, the opening forming area SA, and the probe contact area PA are indicated by dotted lines.

  In the seventh embodiment, no element is formed below the pad PD, and a groove-type separation portion 2 is formed. In this case, in order to prevent a step from being generated between the region where the element is present and the region where the element is not present (that is, to ensure flatness of each wiring layer), in particular, dummy wiring is provided in each wiring layer below the pad PD. It is necessary to provide DL. The dummy wiring DL is generally formed in the same process as the wiring in the same layer, but is formed with a conductor pattern unrelated to the configuration of the integrated circuit itself. The dummy wiring DL is arranged evenly in the area where no wiring is arranged.

  However, also in the seventh embodiment, as in the first embodiment, in the fifth wiring layer M5 immediately below the uppermost wiring layer MH, the probe PD is directly below the probe contact area PA (probe mark). The conductor pattern (the fifth wiring 5F, the dummy wiring DL, and the plug 6C) is not formed. Here, since the minimum processing dimension of the uppermost wiring layer MH is larger than the minimum processing dimension of the wiring layer below the fifth wiring layer M5 and the focal depth of lithography is large, the dummy wiring DL in the fifth wiring layer M5 is large. Even if some of them are eliminated, deterioration of flatness can be tolerated.

  In the fifth wiring layer M5, conductor patterns (the fifth wiring 5F, the dummy wiring DL, and the plug 6C) are formed in a region other than directly below the probe contact region PA. That is, in the fifth wiring layer M5, the conductor pattern including the fifth wiring 5F and the dummy wiring DL is preferably arranged evenly in a region other than directly below the probe contact area PA.

  Even immediately below the probe contact area PA of the pad PD, the dummy wiring DL is disposed in the fourth wiring layer M4 and the lower wiring layer, and the flatness of each wiring layer is ensured. ing. Other configurations are the same as those in the first embodiment.

  FIG. 39 is a plan view of an essential part of a semiconductor chip of another comparative example examined by the present inventors, and a conductor pattern (fifth wiring 5F and dummy wiring DL) of the fifth wiring layer M5 in the vicinity of the pad PD formation region. This corresponds to FIG. 8 of the semiconductor chip of the comparative example described in the first embodiment. In the comparative example of FIGS. 7 to 9 described in the first embodiment and the comparative example of FIG. 39, the type of conductor pattern formed under the pad PD (in the case of FIGS. The mixing of dummy wirings, which is almost dummy wiring in the case of FIG. 39, is different, but the comparative example of FIG. 39 also has the same problem as the comparative example of FIGS. 7 to 9 described in the first embodiment. As described in the first embodiment, the seventh embodiment can solve this problem.

  According to the seventh embodiment, the same effects as those of the first embodiment can be obtained, and the following effects can be obtained. That is, since the flatness of the wiring layer can be secured, the transfer accuracy and formation accuracy of the wiring pattern can be improved. For this reason, layout restrictions due to deterioration of the flatness of the wiring layer can be minimized. Therefore, the reliability and yield of the semiconductor device can be improved. In addition, the size reduction of the semiconductor chip can be promoted.

(Embodiment 8)
The left side of FIG. 40 is a cross-sectional view of a portion corresponding to the Y1-Y1 line of FIG. 1 in the internal region of the semiconductor chip of the semiconductor device of the eighth embodiment, and the right side is X1- of FIG. It is sectional drawing of the location corresponded to a X1 line. FIG. 41 is a plan view of the principal part showing the semiconductor chip of the semiconductor device of the eighth embodiment, and corresponds to FIG. That is, FIG. 41 shows an example of the layout of the conductor pattern (fourth wiring 5E and dummy wiring DL) of the fourth wiring layer M4 in the vicinity of the pad PD formation region. In FIG. 41, the positions of the pad PD, the opening formation area SA, and the probe contact area PA are indicated by dotted lines.

  The layout of the conductor pattern (fifth wiring 5F and dummy wiring DL) of the fifth wiring layer M5 in the vicinity of the pad PD formation region in the eighth embodiment is substantially the same as that in the seventh embodiment (FIG. 37). Therefore, the illustration is omitted here.

  The eighth embodiment is a modification of the seventh embodiment. That is, in the eighth embodiment, as in the seventh embodiment, since no element is formed below the pad PD, the dummy wiring DL is provided in each of the plurality of wiring layers below the pad. Yes.

  The configuration of the semiconductor device of the eighth embodiment is different from that of the seventh embodiment as follows. In the eighth embodiment, in the two layers of the fifth wiring layer M5 and the fourth wiring layer M4 immediately below the uppermost wiring layer MH, immediately below the probe contact area PA (probe trace) of the pad PD, Conductor patterns (fifth wiring 5F, fourth wiring 5E, dummy wiring DL, and plug 6C) are not formed. That is, all the wiring layers (fourth wiring layers) not having the low dielectric constant film above the wiring layers having the low dielectric constant film having low mechanical strength (the first wiring layer M1 to the third wiring layer M3). The conductor pattern in the corresponding part of M4 and the fifth wiring layer M5) (directly under the probe contact area PA (probe mark) of the pad PD) was selectively removed. Thereby, cracks in the insulating film below the pad PD can be suppressed or prevented more effectively than in the first embodiment.

  In the fourth wiring layer M4 and the fifth wiring layer M5, conductor patterns (the fourth wiring 5E, the fifth wiring 5F, the dummy wiring DL, and the plug 6C) are formed in a region other than immediately below the probe contact region PA. ing. That is, in the fourth wiring layer M4 and the fifth wiring layer M5, a conductor pattern made up of the fourth wiring 5E and the dummy wiring DL or a conductor made up of the fifth wiring 5F and the dummy wiring DL is provided in a region other than directly below the probe contact area PA. The pattern is preferably arranged evenly.

  Here, since the minimum processing dimension of the uppermost wiring layer MH and the fifth wiring layer M5 is larger than the minimum processing dimension of the wiring layers below the fourth wiring layer M4 and the depth of focus of lithography is large, the fifth wiring layer Even if the dummy wiring DL in the M5 and the fourth wiring layer M4 is partially eliminated, deterioration of flatness can be allowed. In the eighth embodiment, the dummy wiring DL is arranged in the third wiring layer M3 and the lower wiring layer even in the pad PD immediately below the probe contact area PA. The flatness of the layer is ensured. Therefore, since the flatness of the wiring layer can be ensured, the transfer accuracy and formation accuracy of the wiring pattern can be improved. For this reason, layout restrictions due to deterioration of the flatness of the wiring layer can be minimized. Therefore, the reliability and yield of the semiconductor device can be improved. In addition, the size reduction of the semiconductor chip can be promoted. Other than this, the same effects as those of the first and seventh embodiments can be obtained.

(Embodiment 9)
42 is a cross-sectional view of a portion corresponding to the Y1-Y1 line of FIG. 1 in the internal region of the semiconductor chip of the semiconductor device of the ninth embodiment, and the right side is a pad arrangement region X1- It is sectional drawing of the location corresponded to a X1 line. FIG. 43 is a plan view showing a principal part of the semiconductor chip of the semiconductor device according to the ninth embodiment, which corresponds to FIG. That is, FIG. 43 shows an example of the layout of the conductor pattern (fifth wiring 5F and dummy wiring DL) of the fifth wiring layer M5 in the vicinity of the pad PD formation region. In FIG. 43, the positions of the pad PD, the opening forming area SA, the probe contact area PA, and the wire bonding area WA are indicated by dotted lines, and the position of the wire inclusion area PWA is indicated by a dashed line.

  The layout of the conductor pattern (fourth wiring 5E and dummy wiring DL) of the fourth wiring layer M4 in the vicinity of the pad PD formation region in the ninth embodiment is substantially the same as that in the seventh embodiment (FIG. 38). Therefore, the illustration is omitted here.

  In the ninth embodiment, as in the seventh and eighth embodiments, no element is formed below the pad PD. Therefore, as described in the seventh and eighth embodiments, the pad PD A dummy wiring DL is provided in each of the plurality of wiring layers below.

  However, also in the ninth embodiment, as in the second embodiment, in the fifth wiring layer M5 immediately below the uppermost wiring layer MH, the conductor pattern is located immediately below the wire inclusion area PWA of the pad PD. (Fifth wiring 5F, dummy wiring DL, and plug 6C) are not formed. Therefore, as in the second embodiment, cracks in the insulating film below the pad PD can be suppressed or prevented.

  In the fifth wiring layer M5, conductor patterns (fifth wiring 5F, dummy wiring DL, and plug 6C) are formed in regions other than directly below the wire inclusion region PWA. That is, in the fifth wiring layer M5, the conductor pattern including the fifth wiring 5F and the dummy wiring DL is preferably arranged evenly in a region other than immediately below the wire inclusion region PWA.

  Here, since the minimum processing dimension of the uppermost wiring layer MH is larger than the minimum processing dimension of the wiring layer below the fifth wiring layer M5 and the focal depth of lithography is large, the dummy wiring DL in the fifth wiring layer M5 is large. Even if some of them are eliminated, deterioration of flatness can be tolerated. Further, even immediately below the wire inclusion area PWA of the pad PD, the dummy wiring DL is arranged in the fourth wiring layer M4 and the lower wiring layer, so that the flatness of each wiring layer is ensured. ing. Therefore, since the flatness of the wiring layer can be ensured, the transfer accuracy and formation accuracy of the wiring pattern can be improved. For this reason, layout restrictions due to deterioration of the flatness of the wiring layer can be minimized. Therefore, the reliability and yield of the semiconductor device can be improved. In addition, the size reduction of the semiconductor chip can be promoted. Other configurations and effects are the same as those of the second embodiment.

  FIG. 44 is a plan view of relevant parts showing a modification of the semiconductor chip of the semiconductor device of the ninth embodiment, which corresponds to FIG. That is, FIG. 44 shows an example of the layout of the conductor pattern (the fifth wiring 5F and the dummy wiring DL) of the fifth wiring layer M5 in the vicinity of the pad PD formation region.

  Similarly to the modification shown in FIG. 23, in the modification of the ninth embodiment shown in FIG. 44, the wire bonding area WA and the probe contact area PA are at least partially overlapped (planarly overlapped). Is arranged. Also in this case, in the fifth wiring layer M5 immediately below the uppermost wiring layer MH, the conductor pattern (the fifth wiring 5F, the dummy wiring DL, and the plug 6C) is directly below the wire inclusion area PWA of the pad PD. Not formed. As a result, the plane dimension (area) of the wire inclusion area PWA can be reduced by an amount corresponding to the overlap area between the two, thereby reducing the plane dimension (area) of the opening forming area SA and the pad PD. be able to. For this reason, the planar dimension (area) of the semiconductor chip can be reduced.

(Embodiment 10)
The left side of FIG. 45 is a cross-sectional view of a portion corresponding to the Y1-Y1 line of FIG. 1 in the internal region of the semiconductor chip of the semiconductor device of the tenth embodiment, and the right side is the same as FIG. It is sectional drawing of the location corresponded to a X1 line. FIG. 46 is a plan view showing a principal part of the semiconductor chip of the semiconductor device according to the tenth embodiment, and corresponds to FIG. That is, FIG. 46 shows an example of the layout of the conductor pattern (fourth wiring 5E and dummy wiring DL) of the fourth wiring layer M4 in the vicinity of the pad PD formation region. In FIG. 46, the positions of the pad PD, the opening forming area SA, the probe contact area PA, and the wire bonding area WA are indicated by dotted lines, and the position of the wire inclusion area PWA is indicated by a one-dot chain line.

  The layout of the conductor pattern (fifth wiring 5F and dummy wiring DL) of the fifth wiring layer M5 in the vicinity of the pad PD formation region in the tenth embodiment is substantially the same as in the ninth embodiment (FIG. 43). Therefore, the illustration is omitted here.

  The tenth embodiment is a modification of the ninth embodiment. That is, also in the tenth embodiment, as in the ninth embodiment, since no element is formed below the pad PD, the dummy wiring DL is provided in each of the plurality of wiring layers below the pad. Yes.

  The configuration of the semiconductor device of the tenth embodiment is different from that of the ninth embodiment as follows. In the tenth embodiment, in the two layers of the fifth wiring layer M5 and the fourth wiring layer M4 immediately below the uppermost wiring layer MH, the conductor pattern (first wiring) is directly below the wire inclusion area PWA of the pad PD. 5 wiring 5F, 4th wiring 5E, dummy wiring DL, and plug 6C) are not formed. That is, all the wiring layers (fourth wiring layers) not having the low dielectric constant film above the wiring layers having the low dielectric constant film having low mechanical strength (the first wiring layer M1 to the third wiring layer M3). M4 and the fifth wiring layer M5) were selectively removed from the conductor pattern at the relevant location (just below the wire inclusion area PWA of the pad PD). Thereby, cracks in the insulating film below the pad PD can be suppressed or prevented more effectively than in the case of the second embodiment.

  In the fourth wiring layer M4 and the fifth wiring layer M5, conductor patterns (the fourth wiring 5E, the fifth wiring 5F, the dummy wiring DL, and the plug 6C) are formed in regions other than directly below the wire inclusion region PWA. ing. That is, in the fourth wiring layer M4 and the fifth wiring layer M5, a conductor pattern composed of the fourth wiring 5E and the dummy wiring DL or a conductor composed of the fifth wiring 5F and the dummy wiring DL is provided in a region other than immediately below the wire inclusion region PWA. The pattern is preferably arranged evenly.

  Here, since the minimum processing dimension of the uppermost wiring layer MH and the fifth wiring layer M5 is larger than the minimum processing dimension of the wiring layers below the fourth wiring layer M4 and the depth of focus of lithography is large, the fifth wiring layer Even if the dummy wiring DL in the M5 and the fourth wiring layer M4 is partially eliminated, deterioration of flatness can be allowed. Further, in the tenth embodiment, the dummy wiring DL is arranged in the third wiring layer M3 and the lower wiring layer, even immediately below the wire inclusion area PWA of the pad PD. The flatness of the wiring layer is ensured. Therefore, since the flatness of the wiring layer can be ensured, the transfer accuracy and formation accuracy of the wiring pattern can be improved. For this reason, layout restrictions due to deterioration of the flatness of the wiring layer can be minimized. Therefore, the reliability and yield of the semiconductor device can be improved. In addition, the size reduction of the semiconductor chip can be promoted. Other than this, the same effects as those of the second and ninth embodiments can be obtained.

  Further, as a modification of the tenth embodiment, as in the modification of the ninth embodiment (FIG. 44), at least a part of the wire bonding area WA and the probe contact area PA overlap (planarly overlap). ) Can also be arranged. Thereby, the planar dimension (area) of the pad PD can be reduced, and the planar dimension (area) of the semiconductor chip can be reduced.

(Embodiment 11)
47 is a cross-sectional view of a portion corresponding to the Y1-Y1 line of FIG. 1 in the internal region of the semiconductor chip of the semiconductor device of the eleventh embodiment, and the right side is a pad arrangement region of the same semiconductor chip, X1- It is sectional drawing of the location corresponded to a X1 line. FIG. 48 is a plan view of a principal part showing the semiconductor chip of the semiconductor device of the eleventh embodiment, and corresponds to FIG. That is, FIG. 48 shows an example of the layout of the conductor pattern (fifth wiring 5F and dummy wiring DL) of the fifth wiring layer M5 in the vicinity of the pad PD formation region. In FIG. 48, the positions of the pad PD, the opening forming area SA, and the probe contact area PA are indicated by dotted lines.

  Note that the layout of the conductive pattern (fourth wiring 5E and dummy wiring DL) of the fourth wiring layer M4 in the vicinity of the pad PD formation region in the eleventh embodiment is substantially the same as in the seventh embodiment (FIG. 38). Therefore, the illustration is omitted here.

  In the eleventh embodiment, since no element is formed below the pad PD as in the seventh to tenth embodiments, the lower portion of the pad is the same as described in the seventh to tenth embodiments. A dummy wiring DL is provided in each of the plurality of wiring layers.

  However, also in the eleventh embodiment, as in the third embodiment, in the fifth wiring layer M5 immediately below the uppermost wiring layer MH, a conductor is disposed immediately below the opening formation region SA of the pad PD. A pattern (fifth wiring 5F, dummy wiring DL, and plug 6C) is not formed. Therefore, as in the third embodiment, cracks in the insulating film below the pad PD can be suppressed or prevented.

  In the fifth wiring layer M5, conductor patterns (the fifth wiring 5F, the dummy wiring DL, and the plug 6C) are formed in a region other than immediately below the opening formation region SA. That is, in the fifth wiring layer M5, the conductor pattern including the fifth wiring 5F and the dummy wiring DL is preferably arranged evenly in a region other than immediately below the opening forming region SA.

  Here, since the minimum processing dimension of the uppermost wiring layer MH is larger than the minimum processing dimension of the wiring layer below the fifth wiring layer M5 and the focal depth of lithography is large, the dummy wiring DL in the fifth wiring layer M5 is large. Even if some of them are eliminated, deterioration of flatness can be tolerated. Further, even immediately below the wire inclusion area PWA of the pad PD, the dummy wiring DL is arranged in the fourth wiring layer M4 and the lower wiring layer, so that the flatness of each wiring layer is ensured. ing. Therefore, since the flatness of the wiring layer can be ensured, the transfer accuracy and formation accuracy of the wiring pattern can be improved. For this reason, layout restrictions due to deterioration of the flatness of the wiring layer can be minimized. Therefore, the reliability and yield of the semiconductor device can be improved. In addition, the size reduction of the semiconductor chip can be promoted. Other configurations and effects are the same as those of the third embodiment.

  As a modification of the eleventh embodiment, as in the modification of the ninth embodiment (FIG. 44), at least a part of the wire bonding area WA and the probe contact area PA overlap (planarly overlap). ) Can also be arranged. Thereby, the planar dimension (area) of the pad PD can be reduced, and the planar dimension (area) of the semiconductor chip can be reduced.

(Embodiment 12)
49 is a cross-sectional view of a portion corresponding to the Y1-Y1 line of FIG. 1 in the internal region of the semiconductor chip of the semiconductor device of the twelfth embodiment, and the right side is a pad arrangement region of the same semiconductor chip, X1- It is sectional drawing of the location corresponded to a X1 line. FIG. 50 is a plan view of a principal part showing the semiconductor chip of the semiconductor device of the twelfth embodiment, and corresponds to FIG. That is, FIG. 50 shows an example of the layout of the conductor pattern (fourth wiring 5E and dummy wiring DL) of the fourth wiring layer M4 in the vicinity of the pad PD formation region. In FIG. 50, the positions of the pad PD, the opening formation area SA, and the probe contact area PA are indicated by dotted lines.

  Note that the layout of the conductor pattern (fifth wiring 5F and dummy wiring DL) of the fifth wiring layer M5 in the vicinity of the pad PD formation region in the twelfth embodiment is substantially the same as that in the eleventh embodiment (FIG. 48). Therefore, the illustration is omitted here.

  The twelfth embodiment is a modification of the eleventh embodiment. That is, in the twelfth embodiment, as in the eleventh embodiment, since no element is formed below the pad PD, the dummy wiring DL is provided in each of the plurality of wiring layers below the pad. Yes.

  The configuration of the semiconductor device of the twelfth embodiment is different from that of the eleventh embodiment as follows. In the twelfth embodiment, in the two layers of the fifth wiring layer M5 and the fourth wiring layer M4 immediately below the uppermost wiring layer MH, the conductor pattern ( The fifth wiring 5F, the fourth wiring 5E, the dummy wiring DL, and the plug 6C) are not formed.

  That is, all the wiring layers (fourth wiring layers) not having the low dielectric constant film above the wiring layers having the low dielectric constant film having low mechanical strength (the first wiring layer M1 to the third wiring layer M3). M4 and the fifth wiring layer M5) were selectively removed from the conductor pattern at the corresponding location (immediately below the opening formation area SA of the pad PD). Thereby, cracks in the insulating film below the pad PD can be suppressed or prevented more effectively than in the case of the second embodiment.

  In the fourth wiring layer M4 and the fifth wiring layer M5, conductor patterns (fourth wiring 5E, fifth wiring 5F, dummy wiring DL, and plug 6C) are formed in regions other than directly below the opening formation region SA. Has been. That is, in the fourth wiring layer M4 and the fifth wiring layer M5, a region other than immediately below the opening formation region SA is formed of a conductor pattern including the fourth wiring 5E and the dummy wiring DL or the fifth wiring 5F and the dummy wiring DL. The conductor patterns are preferably arranged evenly.

  Here, since the minimum processing dimension of the uppermost wiring layer MH and the fifth wiring layer M5 is larger than the minimum processing dimension of the wiring layers below the fourth wiring layer M4 and the depth of focus of lithography is large, the fifth wiring layer Even if the dummy wiring DL in the M5 and the fourth wiring layer M4 is partially eliminated, deterioration of flatness can be allowed. Further, in the twelfth embodiment, the dummy wiring DL is arranged in the third wiring layer M3 and the lower wiring layer, even immediately below the opening formation region SA of the pad PD. Flatness of each wiring layer is ensured. Therefore, since the flatness of the wiring layer can be ensured, the transfer accuracy and formation accuracy of the wiring pattern can be improved. For this reason, layout restrictions due to deterioration of the flatness of the wiring layer can be minimized. Therefore, the reliability and yield of the semiconductor device can be improved. In addition, the size reduction of the semiconductor chip can be promoted. Other than this, the same effects as those of the third and eleventh embodiments can be obtained.

  Further, as a modification of the twelfth embodiment, as in the modification of the ninth embodiment (FIG. 44), at least a part of the wire bonding area WA and the probe contact area PA overlap (planarly overlap). ) Can also be arranged. Thereby, the planar dimension (area) of the pad PD can be reduced, and the planar dimension (area) of the semiconductor chip can be reduced.

(Embodiment 13)
51 is a cross-sectional view of a portion corresponding to line Y1-Y1 of FIG. 1 in the internal region of the semiconductor chip of the semiconductor device of the thirteenth embodiment, and the right side is X1- It is sectional drawing of the location corresponded to a X1 line.

  In the thirteenth embodiment, the conductive pattern (fifth wiring 5F and dummy wiring DL) of the fifth wiring layer M5 and the conductive pattern (fourth wiring 5E and dummy wiring) of the fourth wiring layer M4 in the vicinity of the pad PD formation region. The layout of (DL) is substantially the same as that of the seventh embodiment (FIGS. 37 and 38), and the illustration thereof is omitted here.

  In the thirteenth embodiment, dummy wirings DL are provided in each of the plurality of wiring layers in the internal region of the semiconductor chip, and an element is formed below the pad PD as in the seventh to twelfth embodiments. Therefore, the dummy wiring DL is also provided in each of the plurality of wiring layers below the pad PD.

  However, in the thirteenth embodiment, as in the third embodiment, in the fifth wiring layer M5 immediately below the uppermost wiring layer MH, a conductor is disposed immediately below the opening formation region SA of the pad PD. A pattern (fifth wiring 5F, dummy wiring DL, and plug 6C) is not formed. As a result, the same effect as in the third embodiment can be obtained.

  In the thirteenth embodiment, similarly to the fourth embodiment, a conductor pattern (second conductor pattern) 6M having a concave cross section is formed immediately below the probe contact area PA (probe mark) of the pad PD. It is formed in contact with the lower surface. That is, in the thirteenth embodiment, a large hole THA is formed in the probe contact area PA in the insulating films 3E and 4D of the uppermost wiring layer MH, and the above-described concave cross section is formed in the hole THA. The conductor pattern 6M and a part of the conductor film of the pad PD are sequentially deposited from the lower layer. The configuration and formation method of the conductor pattern 6M are the same as those described in the fourth embodiment. As a result, the same effect as in the fourth embodiment can be obtained.

  Further, as described above, the minimum processing dimension of the uppermost wiring layer MH is larger than the minimum processing dimension of the wiring layer below the fifth wiring layer M5, and the depth of focus of lithography is large. Even if the dummy wiring DL is partially removed, the deterioration of flatness can be allowed. Further, even immediately below the opening formation area SA of the pad PD, the dummy wiring DL is arranged in the fourth wiring layer M4 and the wiring layer below it, so that the flatness of each wiring layer is improved. It can be secured. Further, since the dummy wiring DL is provided in each of the plurality of wiring layers in the inner region of the semiconductor chip, the flatness of the wiring layer in the inner region can be ensured. Thus, since the flatness of the wiring layer can be ensured, the transfer accuracy and formation accuracy of the wiring pattern can be improved. For this reason, layout restrictions due to deterioration of the flatness of the wiring layer can be minimized. Therefore, the reliability and yield of the semiconductor device can be improved. In addition, the size reduction of the semiconductor chip can be promoted. Other configurations and effects are the same as those of the third and fourth embodiments.

  As a modification of the thirteenth embodiment, in the fifth wiring layer M5 immediately below the uppermost wiring layer MH, a conductor pattern (fifth wiring 5F, dummy wiring DL, and dummy wiring DL) is provided immediately below the probe contact area PA of the pad PD. The plug 6C) may not be provided.

  Further, in the fifth wiring layer M5 immediately below the uppermost wiring layer MH, the conductor pattern (the fifth wiring 5F, the dummy wiring DL, and the plug 6C) is not provided immediately below the wire inclusion region PWA of the pad PD. May be.

(Embodiment 14)
52 is a cross-sectional view of a portion corresponding to the Y1-Y1 line in FIG. 1 in the internal region of the semiconductor chip of the semiconductor device of the fourteenth embodiment, and the right side is a pad arrangement region of the same semiconductor chip in FIG. It is sectional drawing of the location corresponded to a X1 line.

  Note that the conductor pattern (fifth wiring 5F and dummy wiring DL) of the fifth wiring layer M5 and the conductor pattern (fourth wiring 5E and dummy wiring) of the fourth wiring layer M4 in the vicinity of the pad PD formation region in the fourteenth embodiment. The layout of (DL) is substantially the same as that of the ninth embodiment (FIGS. 43 and 38), and is not shown here.

  In the fourteenth embodiment, dummy wirings DL are provided in each of the plurality of wiring layers in the internal region of the semiconductor chip, and an element is formed below the pad PD as in the seventh to thirteenth embodiments. Therefore, the dummy wiring DL is provided in each of the plurality of wiring layers below the pad.

  However, in the fourteenth embodiment, as in the third embodiment, in the fifth wiring layer M5 immediately below the uppermost wiring layer MH, a conductor is disposed immediately below the opening formation region SA of the pad PD. A pattern (fifth wiring 5F, dummy wiring DL, and plug 6C) is not formed. As a result, the same effect as in the third embodiment can be obtained.

  In the fourteenth embodiment, similarly to the fifth embodiment, a conductor pattern (second conductor pattern) 6M having a concave cross section is in contact with the lower surface of the pad PD immediately below the wire inclusion area PWA of the pad PD. It is formed in a state. That is, in the fourteenth embodiment, a large hole THA is formed in the wire inclusion region PWA in the insulating films 3E and 4D of the uppermost wiring layer MH, and the above-described concave section is formed in the hole THA. The conductor pattern 6M and a part of the conductor film of the pad PD are sequentially deposited from the lower layer. The configuration and formation method of the conductor pattern 6M are the same as those described in the fourth embodiment. Thereby, the same effects as those of the fourth and fifth embodiments can be obtained.

  Further, as described above, the minimum processing dimension of the uppermost wiring layer MH is larger than the minimum processing dimension of the wiring layer below the fifth wiring layer M5, and the depth of focus of lithography is large. Even if the dummy wiring DL is partially removed, the deterioration of flatness can be allowed. Further, even immediately below the opening formation area SA of the pad PD, the dummy wiring DL is arranged in the fourth wiring layer M4 and the wiring layer below it, so that the flatness of each wiring layer is improved. It can be secured. Further, since the dummy wiring DL is provided in each of the plurality of wiring layers in the inner region of the semiconductor chip, the flatness of the wiring layer in the inner region can be ensured. Thus, since the flatness of the wiring layer can be ensured, the transfer accuracy and formation accuracy of the wiring pattern can be improved. For this reason, layout restrictions due to deterioration of the flatness of the wiring layer can be minimized. Therefore, the reliability and yield of the semiconductor device can be improved. In addition, the size reduction of the semiconductor chip can be promoted. Other configurations and effects are the same as those of the third and fifth embodiments.

  As a modification of the fourteenth embodiment, in the fifth wiring layer M5 immediately below the uppermost wiring layer MH, the conductor pattern (the fifth wiring 5F, the dummy wiring DL, and the wiring pattern PWA is directly below the wire inclusion area PWA of the pad PD. The plug 6C) may not be provided.

  As a modification of the fourteenth embodiment, as in the modification of the ninth embodiment (FIG. 44), at least a part of the wire bonding area WA and the probe contact area PA overlap (planarly overlap). ) Can also be arranged. Thereby, the planar dimension (area) of the pad PD can be reduced, and the planar dimension (area) of the semiconductor chip can be reduced.

(Embodiment 15)
53 is a cross-sectional view of a portion corresponding to the Y1-Y1 line of FIG. 1 in the internal region of the semiconductor chip of the semiconductor device of the fifteenth embodiment, and the right side is a pad arrangement region of the same semiconductor chip, X1- It is sectional drawing of the location corresponded to a X1 line.

  Note that the conductor pattern (fifth wiring 5F and dummy wiring DL) of the fifth wiring layer M5 and the conductor pattern (fourth wiring 5E and dummy wiring) of the fourth wiring layer M4 in the vicinity of the pad PD formation region in the fifteenth embodiment. The layout of (DL) is substantially the same as that of Embodiment 11 (FIGS. 48 and 38), and is not shown here.

  In the fifteenth embodiment, dummy wirings DL are provided in each of the plurality of wiring layers in the internal region of the semiconductor chip, and elements are formed below the pad PD, as in the seventh to fourteenth embodiments. Therefore, the dummy wiring DL is provided in each of the plurality of wiring layers below the pad.

  However, in the fifteenth embodiment, as in the third embodiment, in the fifth wiring layer M5 immediately below the uppermost wiring layer MH, a conductor is disposed immediately below the opening formation region SA of the pad PD. A pattern (fifth wiring 5F, dummy wiring DL, and plug 6C) is not formed. As a result, the same effect as in the third embodiment can be obtained.

  In the fifteenth embodiment, similarly to the sixth embodiment, a conductor pattern (second conductor pattern) 6M having a concave cross section contacts the lower surface of the pad PD immediately below the opening formation area SA of the pad PD. It is formed in the state. That is, in the fifteenth embodiment, a large hole THA is formed in the opening formation region SA in the insulating films 3E and 4D of the uppermost wiring layer MH, and the above-described sectional concave shape is formed in the hole THA. The conductor pattern 6M and a part of the conductor film of the pad PD are sequentially deposited from the lower layer. The configuration and formation method of the conductor pattern 6M are the same as those described in the fourth embodiment. Thereby, the same effects as those of the fourth and sixth embodiments can be obtained.

  Further, as described above, the minimum processing dimension of the uppermost wiring layer MH is larger than the minimum processing dimension of the wiring layer below the fifth wiring layer M5, and the depth of focus of lithography is large. Even if the dummy wiring DL is partially removed, the deterioration of flatness can be allowed. Further, even immediately below the opening formation area SA of the pad PD, the dummy wiring DL is arranged in the fourth wiring layer M4 and the wiring layer below it, so that the flatness of each wiring layer is improved. It can be secured. Further, since the dummy wiring DL is provided in each of the plurality of wiring layers in the inner region of the semiconductor chip, the flatness of the wiring layer in the inner region can be ensured. Thus, since the flatness of the wiring layer can be ensured, the transfer accuracy and formation accuracy of the wiring pattern can be improved. For this reason, layout restrictions due to deterioration of the flatness of the wiring layer can be minimized. Therefore, the reliability and yield of the semiconductor device can be improved. In addition, the size reduction of the semiconductor chip can be promoted. Other configurations and effects are the same as those of the third and sixth embodiments.

  Further, as a modification of the fifteenth embodiment, as in the modification of the ninth embodiment (FIG. 44), at least a part of the wire bonding area WA and the probe contact area PA overlap (planarly overlap). ) Can also be arranged. Thereby, the planar dimension (area) of the pad PD can be reduced, and the planar dimension (area) of the semiconductor chip can be reduced.

(Embodiment 16)
The left side of FIG. 54 is a cross-sectional view of a portion corresponding to the Y1-Y1 line of FIG. 1 in the internal region of the semiconductor chip of the semiconductor device of the sixteenth embodiment, and the right side is the same as X1- It is sectional drawing of the location corresponded to a X1 line. FIGS. 55 and 56 are plan views showing main parts of the semiconductor chip of the semiconductor device according to the sixteenth embodiment, and correspond to FIGS. 5 and 6, respectively. That is, FIG. 55 shows an example of the layout of the conductor pattern (fifth wiring 5F and dummy wiring DL) of the fifth wiring layer M5 in the vicinity of the pad PD formation region, and FIG. 56 shows the vicinity of the pad PD formation region. An example of the layout of the conductor pattern (fourth wiring 5E and dummy wiring DL) of the fourth wiring layer M4 in FIG. 55 and 56, the positions of the pad PD, the opening forming area SA, the probe contact area PA, and the wire bonding area WA are indicated by dotted lines.

  The sixteenth embodiment corresponds to a further modification in which the formation of the plug 6C is omitted in the modification of the semiconductor chip of the semiconductor device of the first embodiment shown in FIGS.

  In the sixteenth embodiment, the plug 6C is not formed. Instead, as shown in FIG. 54, openings (holes, through holes) 7A and 7B are provided in the insulating films 3E and 4D, and the uppermost wiring 5G and the pad PD are formed so as to fill the openings 7A and 7B. doing. A part of the uppermost wiring 5G is formed (arranged) in the opening 7A, and a part of the pad PD is formed (arranged) in the opening 7B.

  That is, in the sixteenth embodiment, after the structure of FIG. 14 is obtained in the same manner as in the first embodiment, the insulating films 4D and 3E are deposited, and then the openings 7A and the fifth wiring 5F are exposed. 7B is formed on the insulating films 3E and 4D, the uppermost wiring 5G and the conductor film for forming the pad PD are formed on the insulating film 3E including the inside of the openings 7A and 7B, and this conductive film is patterned to form the uppermost wiring. 5G and pad PD are formed. The steps after the formation of the uppermost wiring 5G and the pad PD are the same as those in the first embodiment.

  For this reason, in the sixteenth embodiment, the uppermost wiring 5G and a part of the pad PD (portions in the openings 7A and 7B) also serve as the plug 6C, and the uppermost wiring 5G is the fifth wiring at the bottom of the opening 7A. The pad PD is electrically connected to the fifth wiring 5F (that is, the wiring 5Fc of the fifth wiring 5F) at the bottom of the opening 7B.

  Since the uppermost wiring 5G and the conductor film for forming the pad PD (the barrier metal films BM2 and BM3 and the main wiring member MM2) are formed by the sputtering method, the coverage is lower than that of the tungsten film formed by the CVD method. For this reason, if the hole diameters (hole diameters) of the openings 7A and 7B are too small, the conductor film for forming the uppermost wiring 5G and the pad PD cannot be formed well in the openings 7A and 7B, and the uppermost wiring 5G and the pad PD are not formed. There is a possibility that electrical connection between the first wiring 5F and the fifth wiring 5F cannot be secured. Therefore, it is preferable that the hole diameter (hole diameter) of the openings 7A and 7B is 1 μm or more, thereby ensuring the electrical connection between the uppermost wiring 5G and the pad PD and the fifth wiring 5F accurately. be able to. Compared with the through hole in which the plug 6C is embedded, the required area of the internal region (left side in FIG. 54) of the semiconductor chip is slightly increased because the hole diameter of the opening 7A needs to be increased (1 μm or more). Since the plug 6C formation step can be omitted, the number of manufacturing steps of the semiconductor device can be reduced, thereby reducing the manufacturing cost of the semiconductor device.

  On the other hand, the opening 7B has the same size as the wire bonding area WA (that is, the opening 7B is provided in the entire wire bonding area WA), and the portion in the opening 7B of the pad PD is the wire bonding area WA. . The probe contact area PA is provided in a portion of the pad PD outside the opening 7B. Thereby, the area increase of a pad formation area can be avoided.

  Of the fifth wiring 5F, the wiring 5Fc connected to the pad PD at the bottom of the opening 7B has a pattern (for example, about half the area of the pad PD) that includes the opening 7B in a plane. The wiring 5Fc does not extend below the probe contact area PA.

  As can be seen from FIGS. 54 to 56, in the sixteenth embodiment, in the fifth wiring layer M5 immediately below the uppermost wiring layer MH, the conductor pattern (first pattern) is directly below the probe contact area PA of the pad PD. 5 wiring 5F and dummy wiring DL) are not formed. In the fifth wiring layer M5, conductor patterns (fifth wiring 5F and dummy wiring DL) are formed in regions other than the region directly below the probe contact region PA of the pad PD. That is, in the fifth wiring layer M5, the conductor pattern including the fifth wiring 5F and the dummy wiring DL is preferably arranged evenly in a region other than directly below the probe contact area PA. In the sixteenth embodiment, conductor patterns (wirings, dummy wirings, plugs) are formed in the lowermost wiring layer ML to the fourth wiring layer M4 even immediately below the probe contact area PA of the pad PD. Yes. Also in the sixteenth embodiment, the same effect as in the first embodiment can be obtained.

  Furthermore, in the sixteenth embodiment, since the plug 6C forming step can be omitted, the number of manufacturing steps of the semiconductor device can be reduced, and the manufacturing cost of the semiconductor device can be reduced.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the above embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  In the above description, the case where the invention made mainly by the present inventor is applied to a semiconductor device which is a field of use as the background has been described. However, the present invention is not limited to this and can be applied in various ways, for example, a liquid crystal display device. And MEMS (Micro Electro Mechanical Systems).

  The present invention can be applied to the semiconductor device manufacturing industry.

DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 2 Separation part 3A, 3B, 3C, 3D, 3D1, 3D2, 3E, 3F Insulating film 4A, 4B, 4D Insulating film 5 Conductor film 5A Bottom wiring 5B First wiring 5C Second wiring 5D Third wiring 5E 4th wiring 5F 5th wiring 5G Topmost wiring 6 Conductor film 6A, 6C Plug (connection part)
7A, 7B Opening 6M Conductor pattern (second conductor pattern)
Q MIS • FET
ML Lowermost wiring layer M1 First wiring layer M2 Second wiring layer M3 Third wiring layer M4 Fourth wiring layer M5 Fifth wiring layer MH Uppermost wiring layers MM0, MM1, MM2 Main wiring members BM0, BM1, BM2, BM3 barrier metal film PD bonding pad (external terminal)
S opening PA probe contact area (first area)
WA Wire bonding area PWA Wire inclusion area (first area)
SA opening formation region (first region)
PRB Probe CLK Crack LV Wiring groove TH Through hole THA Hole DL Dummy wiring W1, L1 Dimension W2 Width

Claims (4)

A semiconductor substrate;
A semiconductor element formed on the semiconductor substrate;
A first insulating film formed on the semiconductor element;
A first wiring formed in the first insulating film;
A second wiring formed in the same layer as the first wiring in the first insulating film;
A second insulating film formed on the first insulating film, the first wiring, and the second wiring;
A third wiring formed in the second insulating film;
A third insulating film formed on the second insulating film and the third wiring;
A pad formed on the third insulating film;
A fourth insulating film formed on the third insulating film so as to cover the pad and having an opening formed on the pad;
Have
The pad is included in the uppermost wiring layer,
The pad in the opening includes a first region and a second region;
The first region is a probe contact region;
The second region is a bonding region of bonding wires,
The third wiring is included in a wiring layer that is one level lower than the uppermost wiring layer, and is disposed immediately below the second region,
A conductor pattern of the same layer as the third wiring is not formed immediately below the first region,
The first wiring is disposed immediately below the second region,
The second wiring is disposed immediately below the first region,
The semiconductor device according to claim 1, wherein the second wiring has a smaller width than the first wiring. The semiconductor device according to claim 1 ,
The semiconductor device, wherein the first wiring, the second wiring, and the third wiring are formed using copper as a main material. The semiconductor device according to claim 1 or 2 ,
The semiconductor device, wherein the first insulating film, the second insulating film, or the third insulating film is formed of a material having a dielectric constant lower than that of silicon oxide. The semiconductor device according to any one of claims 1 to 3,
The semiconductor device according to claim 1, wherein the first wiring and the second wiring are included in a wiring layer that is two layers below the uppermost wiring layer.

Images