JP2015053371A - Semiconductor device and method of manufacturing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve the performance of a semiconductor device by preventing a passivation film covering a pad from being cracked or peeled without increasing the area of the pad on an upper surface of a semiconductor chip.SOLUTION: A pad PD is formed on a wiring L7 which is an uppermost wiring constituting a multilayer wiring and has a greatest film thickness among the multilayer wiring. The pad PD is electrically connected to the wiring L7 and has a smaller film thickness than the wiring L7. A bonding wire is connected to an upper surface of the pad PD which mainly contains Al (Aluminum) and is exposed from the passivation film PS.

Description

  The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly to a semiconductor device having a pad on an upper surface of a semiconductor chip and a technique effective when applied to the method for manufacturing the same.

  In recent years, in order to improve the performance of a semiconductor chip, it is required to reduce the wiring resistance of the semiconductor chip. As a structure for realizing this, it is known that the wiring is multilayered. In the lowermost layer of this multilayer wiring, in order to form the wiring connected to the miniaturized element with a high density, the distance between the lowermost layer wirings is set narrow, and the film thickness and width of the wiring are reduced. Make it smaller. On the other hand, in the multilayer wiring, the wiring above the lowermost wiring has a larger pitch, wiring width, and film thickness between the wirings closer to the uppermost layer. With such a configuration, the resistance of the multilayer wiring can be reduced.

  Patent Document 1 (Japanese Patent Application Laid-Open No. 2010-205974) describes that the strength of the pad is increased by providing a reinforcing layer between the pad and the metal layer therebelow.

  In Patent Document 2 (Japanese Patent Laid-Open No. 2011-18832), a Cu (copper) wiring layer is connected to an upper surface of a wiring layer mainly composed of Al (aluminum), and a pad is provided on the upper surface of the Cu wiring layer. It is described that the semiconductor wafer is prevented from warping by connecting a Cu wire. The film thickness of the Cu wiring layer described here is larger than the film thickness of the wiring layer mainly composed of Al.

JP 2010-205974 A JP 2011-18832 A

  Of the multilayer wiring, the uppermost wiring can be used to strengthen the power supply. Therefore, since the resistance of the uppermost layer wiring needs to be particularly low, it is conceivable to increase the film thickness among the multilayer wirings. When this uppermost layer wiring is used as a bonding pad, the following problems occur.

  That is, when a bonding wire made of a material that easily reacts with the material of the pad is connected to a pad formed with a large film thickness for the purpose of reducing resistance or the like, an alloy reaction occurs due to the large film thickness of the pad. As the reaction layer grows excessively and presses the passivation film exposing the pad, a crack is generated in the passivation film.

  In addition, if a bonding wire made of a material harder than the pad material is pressed onto the upper surface of the pad, the bonding wire is submerged in a relatively soft pad due to the large film thickness of the pad. .

  If a passivation film is formed on the pad, the passivation film is opened to expose a part of the upper surface of the pad, wire bonding is performed, and then the semiconductor chip is covered with a resin film, the pad having a large film thickness is formed. The difference in level between the passivation film on the side and the passivation film on the pad becomes large, and the passivation film on the pad is broken by receiving pressure from the resin film.

  In order to avoid these problems, it is conceivable to increase the area of the opening of the passivation film for exposing the pad. However, in this case, the area occupied by the pad becomes large, and it becomes difficult to miniaturize the semiconductor device. .

  Other objects and novel features will become apparent from the description of the specification and the accompanying drawings.

  Of the embodiments disclosed in the present application, the outline of typical ones will be briefly described as follows.

  A semiconductor device according to an embodiment forms a pad electrically connected to the uppermost layer wiring and having a smaller film thickness than the uppermost layer wiring on the uppermost layer wiring constituting the multilayer wiring. is there.

  In one embodiment, a method of manufacturing a semiconductor device includes forming a multilayer wiring on a semiconductor substrate, electrically connected to the uppermost layer wiring on the uppermost layer wiring constituting the multilayer wiring, and A pad having a smaller film thickness than the uppermost layer wiring is formed.

  According to one embodiment disclosed in the present application, the performance of a semiconductor device can be improved. In particular, the semiconductor device can be miniaturized.

2 is a plan layout showing the semiconductor device according to the first embodiment of the present invention; It is sectional drawing which shows the semiconductor device which is Embodiment 1 of this invention. It is sectional drawing which shows the semiconductor device which is Embodiment 1 of this invention. It is sectional drawing which shows the manufacturing method of the semiconductor device which is Embodiment 1 of this invention. FIG. 5 is a cross-sectional view showing a method for manufacturing the semiconductor device following FIG. 4. FIG. 6 is a cross-sectional view showing a method for manufacturing the semiconductor device following FIG. 5; FIG. 7 is a cross-sectional view showing a method for manufacturing the semiconductor device following FIG. 6; FIG. 8 is a cross-sectional view showing a method for manufacturing the semiconductor device following FIG. 7; FIG. 9 is a cross-sectional view showing a method for manufacturing the semiconductor device following FIG. 8. FIG. 10 is a cross-sectional view showing a method for manufacturing the semiconductor device following FIG. 9; FIG. 11 is a cross-sectional view showing a method for manufacturing the semiconductor device following FIG. 10; FIG. 12 is a cross-sectional view showing a method for manufacturing the semiconductor device following FIG. 11; FIG. 13 is a cross-sectional view showing a method for manufacturing the semiconductor device following FIG. 12; FIG. 14 is a cross-sectional view showing a method for manufacturing the semiconductor device following FIG. 13; FIG. 15 is a cross-sectional view showing a method for manufacturing the semiconductor device following FIG. 14; 4 is a plan layout showing a semiconductor device according to a second embodiment of the present invention. It is sectional drawing which shows the semiconductor device which is Embodiment 2 of this invention. It is a plane layout which shows the semiconductor device which is Embodiment 3 of this invention. It is sectional drawing which shows the semiconductor device which is Embodiment 3 of this invention. It is sectional drawing which shows the semiconductor device which is Embodiment 4 of this invention. It is sectional drawing which shows the semiconductor device which is a comparative example. It is sectional drawing which shows the semiconductor device which is a comparative example. It is sectional drawing which shows the semiconductor device which is a comparative example.

  Hereinafter, embodiments will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiments, and the repetitive description thereof will be omitted. In the following embodiments, the description of the same or similar parts will not be repeated in principle unless particularly necessary.

  Note that the width of the wiring referred to in this application refers to the length of the wiring in a direction orthogonal to the extending direction of the wiring. In addition, the same layer as used in the present application is each film formed by separating what was originally one film in the manufacturing process, and the mutual relationship of a plurality of films provided at the same height Say.

  Further, the height in the present application refers to a distance in a direction perpendicular to the main surface of the semiconductor substrate, and refers to a distance from the main surface of the semiconductor substrate unless otherwise specified. However, the height of the side wall referred to in the present application refers to the distance from the lower end to the upper end of the side wall of the specific film.

(Embodiment 1)
The semiconductor device and the manufacturing method thereof according to the present embodiment are particularly characterized by the structure of the uppermost layer wiring on the upper side of the multilayer wiring and the pad thereon and the manufacturing method thereof. This is to increase or prevent the insulating film near the pad from cracking.

  The semiconductor device of this embodiment will be described below with reference to FIGS. FIG. 1 is a plan layout of the semiconductor device of the present embodiment, and FIGS. 2 and 3 are cross-sectional views of the semiconductor device of the present embodiment. FIG. 3 shows a cross section of a wider area than FIG.

  FIG. 1 shows one pad PD among a plurality of pads formed on the upper surface of a semiconductor chip which is the semiconductor device of the present embodiment. A part of the upper surface of the pad PD is covered with the passivation film PS (see FIGS. 2 and 3), and the other part is exposed from the opening OP of the passivation film PS. In FIG. 1, the passivation film PS itself is not shown, but the outline of the opening of the passivation film PS is indicated by a solid line. In FIG. 1, the outline of the wiring under the pad PD is indicated by a broken line, but each via under the pad PD is indicated by a solid line.

  The opening OP has, for example, a rectangular shape in plan view, and the opening area is smaller than the area of the upper surface of the pad PD in plan view. Only the upper surface of the pad PD is exposed at the bottom of the rectangular opening OP. That is, in the plan view, the opening OP overlaps the pad PD in any region.

  The pad PD is a first conductor film disposed under the passivation film PS and mainly contains Al (aluminum). A wiring L7 mainly containing Al (aluminum) is formed under the pad PD. Both the pad PD and the wiring L7 have a rectangular shape in plan view. The pad PD and the wiring L7 are electrically connected through a plurality of vias V2 formed between them. In FIG. 1, the pad PD extends in a specific direction. The width of the pad PD in the direction orthogonal to the extending direction is, for example, 40 μm.

  The via V2 is made of the same conductive film as the pad PD. In the plan view, the via V2 is not disposed inside the opening OP. A plurality of vias V2 are arranged side by side in a specific direction in plan view. In the present embodiment, a part of the wiring L7 is arranged immediately below the region inside the opening OP.

  The wiring L7 is connected to a wiring (not shown) below the via V1 through a plurality of vias V1 formed below the wiring L7. The via V1 is made of the same conductor film as the wiring L7. A plurality of vias V1 are arranged in a specific direction in plan view. In FIG. 1, the via V <b> 1 and the via V <b> 2 are arranged at positions where they do not overlap each other in plan view, but the via V <b> 1 and the via V <b> 2 may be arranged at positions where they overlap each other when seen in plan view.

  FIG. 2 shows a cross-sectional view taken along line AA in FIG. FIG. 2 shows a wiring L7 that is the uppermost layer wiring among the multilayer wirings including a plurality of stacked wirings, and a wiring L6 that constitutes a wiring layer immediately below the wiring L7, and is below the wiring L6. The multilayer wiring is not shown. The multilayer wiring is a structure in which a plurality of wiring layers including wiring are stacked, and includes a top layer wiring formed in the top layer and a lower layer wiring formed below the top layer wiring.

  As shown in FIG. 2, the wiring L6 is a wiring mainly made of Cu (copper), and is embedded in a wiring trench opened in the interlayer insulating film IL6b. The interlayer insulating film IL6b is made of, for example, a silicon oxide film. The wiring L6 is formed by a so-called dual damascene method, and a via V1 made of the same film as the wiring L7 is connected to the upper surface of the wiring L6. In FIG. 2, a plurality of films constituting the wiring L6 are not distinguished, but the wiring L6 is formed on the barrier conductor film including, for example, a barrier conductor film containing Ta (tantalum) or TaN (tantalum nitride). In addition, the main conductor film includes Cu (copper).

  The via V1 is buried in the via hole VH1 opened in the laminated film including the barrier insulating film SF and the interlayer insulating film IL7a on the barrier insulating film SF. That is, the interlayer insulating film IL7a is formed over the wiring L6 and the interlayer insulating film IL6b via the barrier insulating film SF, and the wiring L7 is formed over the interlayer insulating film IL7a. The wiring L6 and the wiring L7 are electrically connected via the via V1. The barrier insulating film SF is made of, for example, a SiCN film, and the interlayer insulating film IL7a is made of, for example, a silicon oxide film.

  The wiring L7 includes a barrier conductor film BL1, a main conductor film M1, and a barrier conductor film BU1 that are sequentially stacked on the interlayer insulating film IL7a. The via V1 includes a barrier conductor film BL1 and a main conductor film M1 that are sequentially stacked in the via hole VH1. The side wall and the upper surface of the wiring L7 are covered with an interlayer insulating film IL7b. The interlayer insulating film IL7b is a second insulating film made of, for example, a silicon oxide film. Here, the bottom surface of the interlayer insulating film IL7b is in contact with the top surface of the interlayer insulating film IL7a.

  A plurality of via holes VH2 are opened in the interlayer insulating film IL7b immediately above the wiring L7, and the upper surface of the wiring L7 is exposed at the bottom of the via hole VH2. A via V2 made of the same conductor film as the pad PD formed on the interlayer insulating film IL7b is buried in the via hole VH2. Therefore, the wiring L7 and the pad PD are electrically connected via the via V2. The pad PD includes a barrier conductor film BL2, a main conductor film M2, and a barrier conductor film BU2 that are sequentially stacked on the interlayer insulating film IL7b. The via V2 includes a barrier conductor film BL2 and a main conductor film M2 that are sequentially stacked in the via hole VH2. As shown in FIG. 2, the via V2 may include a barrier conductor film BU2 on the main conductor film M2.

  The barrier conductor films BL1, BL2, BU1, and BU2 are, for example, a Ti (titanium) film or a TiN (titanium nitride) film, or a laminated film of a Ti (titanium) film and a TiN (titanium nitride) film. Each film thickness of the barrier conductor films BL1, BL2, BU1, and BU2 is, for example, about 100 nm. The main conductor films M1 and M2 are Al (aluminum) films. The main conductor film M1 has a film thickness of, for example, 1500 nm, and the main conductor film M2 has a film thickness of, for example, 800 nm or less. That is, the film thickness of the pad PD formed on the wiring L7 which is the uppermost layer wiring among the multilayer wirings is smaller than the film thickness of the wiring L7.

  Since the upper surface of the interlayer insulating film IL7b is flattened, the pad PD is formed flat along the upper surface of the interlayer insulating film IL7b. As shown in FIGS. 1 and 2, here, the configuration in which the width of the pad PD is larger than the width of the wiring L7 is illustrated, but the width of the pad PD may be smaller than the width of the wiring L7. In the layout shown in FIG. 1, the entire wiring L7 overlaps the pad PD. However, when the width of the pad PD is smaller than the width of the wiring L7, the entire pad PD overlaps the wiring L7. Also good. Further, both the pad PD and the wiring L7 may be arranged at a position where parts do not overlap each other.

  As shown in FIG. 2, a part of the upper surface and the side wall of the pad PD are covered with a passivation film PS that is a first insulating film. The passivation film PS is made of, for example, a silicon oxide film, and the film thickness is, for example, 1000 nm or less. The passivation film PS has an opening OP that exposes the upper surface of the pad PD.

  The area exposed from the opening OP, that is, the pad area, on the upper surface of the pad PD is a bonding wire for electrically connecting the lead around the die pad and the semiconductor chip after the semiconductor chip is mounted on the die pad. Is an area to connect. The pad region is a region for conducting the inspection device and the semiconductor chip by bringing the inspection needle into contact with each other in probe inspection performed for the purpose of functional inspection of the semiconductor chip.

  Here, FIG. 3 shows a cross section of the semiconductor chip in which the bonding wire is connected to the pad region, including a multilayer wiring below the wiring L6 shown in FIG. As shown in FIG. 3, the semiconductor chip which is the semiconductor device of the present embodiment has a semiconductor substrate SB at the bottom. An element isolation region STI made of an insulating film is formed on the main surface of the semiconductor substrate SB. A plurality of MISFETs (Metal Insulator Semiconductor Field Effect Transistors) Q1 are formed on the semiconductor substrate SB exposed from the element isolation region STI. The semiconductor element formed on or in the main surface of the semiconductor substrate SB may be an element other than the MISFET.

  An interlayer insulating film CL made of a silicon oxide film is formed on the semiconductor substrate SB so as to cover the MISFET Q1. A plurality of plugs PL1 penetrating the interlayer insulating film CL are formed, and the plug PL1 is connected to the source / drain regions or gate electrodes constituting the MISFET Q1. An interlayer insulating film IL1 is formed on the plug PL1 and the interlayer insulating film CL, and a wiring L1 connected to the plug PL1 is formed in each of a plurality of wiring trenches penetrating the interlayer insulating film IL1. ing. The interlayer insulating film IL1 is made of, for example, a silicon oxide film. The wiring L1 is formed by a so-called single damascene method. The wiring L1 is the lowest layer wiring formed at the bottom of the multilayer wiring. Here, the layer including the wiring L1 and the interlayer insulating film IL1 is referred to as a first wiring layer.

  Over the wiring L1 and the interlayer insulating film IL1, there are formed an interlayer insulating film IL2 and a wiring L2 formed in each of a plurality of wiring grooves formed on the upper surface of the interlayer insulating film IL2. The interlayer insulating film IL2 is made of, for example, a silicon oxide film. The wiring L2 and the wiring L1 are connected to each other via a plug PL2 made of the same conductor film as the wiring L2. The plug PL2 is opened at the bottom of the wiring trench in which the wiring L2 is embedded, and is embedded in a via hole that penetrates the interlayer insulating film IL2. The wiring L2 and the plug PL2 are formed by a so-called dual damascene method. Here, the layer including the wiring L2, the plug PL2, and the interlayer insulating film IL2 is referred to as a second wiring layer.

  On the second wiring layer, a third wiring layer, a fourth wiring layer, and a fifth wiring layer having the same structure as the second wiring layer are sequentially formed. The third wiring layer includes a wiring L3, a plug PL3, and an interlayer insulating film IL3. The fourth wiring layer includes a wiring L4, a plug PL4, and an interlayer insulating film IL4. The fifth wiring layer includes a wiring L5, a plug PL5, and an interlayer insulating film IL5.

  The widths and thicknesses of the wirings L1, L2, and L3 are the same. The widths and thicknesses of the wirings L5 and L4 are the same. The widths and thicknesses of the wirings L5 and L4 are larger than the widths and thicknesses of the wirings L1, L2, and L3, respectively. The diameters of plugs PL5 and PL4 are larger than the diameters of plugs PL1, PL2 and PL3.

  On the fifth wiring layer, an interlayer insulating film IL6a and an interlayer insulating film IL6b are sequentially stacked. The interlayer insulating film IL6a and the interlayer insulating film IL6b are made of, for example, a silicon oxide film. A plug PL6 is formed in the via hole penetrating the interlayer insulating film IL6a, and a wiring L6 made of the same conductor film as the plug PL6 is formed on the plug PL6. Here, the wiring L6, the plug PL6, and the interlayer insulating films IL6a and IL6b are referred to as a sixth wiring layer. The width and thickness of the wiring L6 are larger than the width and thickness of each of the wirings L1 to L5. The diameter of plug PL6 is larger than the diameter of each of plugs PL1 to PL5.

  The structure on the sixth wiring layer, that is, the wiring L6 is the same as the structure described with reference to FIG. That is, the wiring L7 is connected to the upper surface on the wiring L6 through the via V1. Of the multilayer wiring, the wiring L7, which is the uppermost wiring, has a wiring width, a film thickness, and a spacing between the wirings larger than that of the wiring L6. However, the wiring width, the film thickness, and the spacing between the wirings of the wiring L7 may be equal to those of the wiring L6. Here, a layer including the wiring L7, the via V1, and the interlayer insulating films IL7a and IL7b is referred to as a seventh wiring layer.

  As described above, the multilayer wiring formed in the semiconductor chip according to the present embodiment includes the wirings L1 to L6 and the wiring L7 that are electrically connected to each other. The pad PD on the wiring L7 is electrically connected to the MISFET Q1 via the vias V1 and V2, the plugs PL1 to PL6, and the wirings L1 to L7.

  Here, as a wiring layer constituting the multilayer wiring, a high-density wiring layer, a medium-density wiring layer on the high-density wiring layer, and a low-density wiring layer on the medium-density wiring layer are provided. The high-density wiring layer is a layer in which the width and thickness are small and the miniaturized wiring is arranged at the narrowest intervals in the multilayer wiring. Specifically, the first wiring layer and the second wiring layer described above are used. And the third wiring layer. The medium-density wiring layer is a layer in which wirings having a width and thickness larger than those of the high-density wiring layer are arranged at intervals wider than the inter-wiring pitch in the high-density wiring layer. Specifically, the above-described fourth wiring It refers to the layer and the fifth wiring layer. The low-density wiring layer is a layer in which wirings having a width and thickness larger than those of the medium-density wiring layer are arranged at intervals wider than the inter-wiring pitch in the medium-density wiring layer. Specifically, the above-described sixth wiring This refers to the layer and the seventh wiring layer.

  As described above, the wiring width and thickness and the spacing between the wirings may be the same in a specific wiring layer and the layer above or below the wiring layer. Regarding the width and thickness, and the interval between the wirings, the lowermost layer wiring is the smallest and the uppermost layer wiring is the largest. That is, the width and thickness of the wiring and the spacing between the wirings increase from the bottom layer to the top layer. Thus, by increasing the size of the upper layer wiring, the resistance of the wiring layer of the semiconductor chip can be reduced. The wirings L1 to L6 and the plugs PL2 to PL6 are mainly made of Cu (copper).

  As shown in FIG. 3, a bonding wire BW is connected to the upper surface of the pad PD in the opening OP. The bonding wire is a conductor film mainly containing, for example, Au (gold), Ag (silver), or Cu (copper). When an Au wire is used, a high bonding strength can be obtained for the pad PD by reacting with Al (aluminum) constituting the pad PD and alloying. Further, since the Au wire is a softer material than Al (aluminum), Ag (silver), or Cu (copper), there is an advantage that the possibility of disconnection is small and bonding is easy.

  Further, since the Cu wire is a harder material than Al (aluminum), a high bonding strength can be obtained by applying a mechanical pressure to the pad PD and pressing it. Further, the Cu wire has an advantage that it is less expensive than the Au wire. The Ag wire is a wire having intermediate characteristics between the Au wire and the Cu wire, and high bonding strength can be obtained by pressure bonding to the pad PD.

  Here, the main feature of the semiconductor device of the present embodiment is that a pad PD made of an Al film having a thickness smaller than that of the uppermost layer wiring is formed on the uppermost layer wiring having the largest thickness among the multilayer wirings. It is in the point. In a semiconductor device having a multilayer wiring, it is conceivable to use the thickest uppermost wiring among the multilayered wirings as a pad. Here, a conductor film for bonding pads is used separately from the uppermost wiring, that is, the wiring L7. As shown, a pad PD, which is a conductor film having a smaller film thickness than the uppermost layer wiring, is provided.

  Further, the upper surface of the wiring L7 and the bottom surface of the pad PD are not in direct contact, and an interlayer insulating film IL7b is formed between the height of the upper surface of the wiring L7 and the height of the bottom surface of the pad PD. That is, the wiring L7 and the pad PD are separated from each other. Therefore, when the opening OP, the pad PD, and the wiring L7 all overlap in plan view, the interlayer insulating film IL7b is always interposed between the pad PD and the wiring L7.

  Although not shown in FIG. 2, a plurality of wirings L7 are arranged on the interlayer insulating film IL7b. Here, the structure in which the interlayer insulating film IL7b is completely buried between the plurality of wirings L7 and the upper surface of the interlayer insulating film IL7b is flattened has been described. It may be so small that the space between the wirings L7 is not completely buried. In this case, the interlayer insulating film IL7b is formed along the upper surface, the side wall, and the upper surface of the interlayer insulating film IL7a.

  That is, when the thickness of the interlayer insulating film IL7b is small and the width of the pad PD is wider than the wiring L7, the pad PD is placed on the upper surface, the side wall, and the upper surface of the interlayer insulating film IL7a via the interlayer insulating film IL7b. Formed along. At this time, the end portion of the pad PD is terminated immediately above the interlayer insulating film IL7b in contact with the upper surface of the interlayer insulating film IL7a, beside the wiring L7. That is, the pad PD may be terminated at a position lower than the upper surface of the interlayer insulating film IL7b immediately above the wiring L7. The height of the end portion of the pad PD needs to be aligned on the semiconductor substrate. This is because when forming a resist pattern used as a mask in the step of forming the pad PD by patterning, it is necessary to align the position of the end portion of the resist pattern with the focal length of the exposure apparatus.

  The effects of the semiconductor device of this embodiment will be described below with reference to FIGS. 21 to 23 are cross-sectional views of a semiconductor device of a comparative example, showing a structure in which bonding wires are connected to pads. All of the semiconductor devices of the comparative examples are the same as the present embodiment in that Al (aluminum) is used as the pad material, but differs from the present embodiment in that the uppermost wiring is used as the pad. .

  FIG. 21 shows a structure in which an Au wire is connected to the wiring PDa which is the uppermost layer wiring of the multilayer wiring. In the semiconductor device of the comparative example shown in FIG. 21, the structure of the sixth wiring layer including the wiring L6 and the multilayer wiring under the sixth wiring layer is the same as the structure shown in FIG. Here, the wiring PDa, which is the uppermost wiring of the multilayer wiring and has a larger film thickness than the wiring L6, is formed on the wiring L6. An interlayer insulating film IL7a is formed between the wiring PDa and the wiring L6, and a via V1 made of the same conductor film as the wiring PDa is buried in the via hole opened in the interlayer insulating film IL7a.

  The wiring PDa includes a barrier conductor film BL1, a main conductor film M1, and a barrier conductor film BU1 that are sequentially stacked on the interlayer insulating film IL7a. The via V1 is composed of the barrier conductor film BL1 and the main conductor film M1. The barrier conductor films BL1 and BU1 are made of, for example, a TiN (titanium nitride) film, and the main conductor film M1 is made of an Al (aluminum) film. Each of the barrier conductor films BL1 and BU1 has a thickness of about 100 nm, and the main conductor film M1 has a thickness of about 1500 nm. That is, the wiring PDa is mainly made of Al (aluminum). The wiring PDa has the largest film thickness among the wirings constituting the multilayer wiring.

  The wiring PDa is a wiring used as a pad. Therefore, a part of the upper surface and the side wall of the wiring PDa are covered with the passivation film PSa, and the other part of the upper surface of the wiring PDa is exposed from the opening OP of the passivation film PSa. A bonding wire BW made of Au (gold) is connected to the upper surface of the wiring PDa exposed at the bottom of the opening OP, that is, the pad region. The passivation film PSa needs to have a relatively large film thickness in order to cover the sidewall of the wiring PDa having a large film thickness. The thickness of the passivation film PSa needs to be 1500 to 2000 nm, for example.

  Au (gold) is a metal that causes an alloy reaction with Al (aluminum) in a high temperature environment. When the Au wire is connected to the upper surface of the wiring PDa which is an Al film having a large film thickness as in the comparative example shown in FIG. 21, the reaction is saturated because there are abundant sources of Al (aluminum) to the Au wire. The time to do becomes longer. FIG. 21 shows a reaction layer ALL made of an Au—Al alloy around the ball at the tip of the bonding wire BW.

  In this case, the reaction layer ALL becomes excessively large due to the large film thickness of the wiring PDa, which is a supply source of Al (aluminum), and the sidewalls of the passivation film PSa at both ends of the opening OP become the reaction layer ALL. When pressed, there is a possibility that cracks may occur in the passivation film PSa. For the same reason, the passivation film PSa may be peeled off from the upper surface of the wiring PDa.

  Next, a structure shown in FIG. 22 will be described as another comparative example. The semiconductor device of the comparative example shown in FIG. 22 has the same structure as that of the semiconductor device shown in FIG. 21 except that Cu (copper) is used as the material of the bonding wire BW. Since Cu (copper) is a harder material than Al (aluminum), when the Cu wire is connected to the wiring PDa that is the uppermost layer wiring, the film thickness of the wiring PDa is large, so The ball enters the wiring PDa. That is, since Al (aluminum) is softer than Cu (copper) and the film thickness of the wiring PDa is large, it is difficult to press the tip of the Cu wire against the pad. Here, the Al film pushed out to the bonding wire BW, that is, a part of the wiring PDa is pushed out so as to rise to the side of the Cu wire in the opening OP.

  In this case, since the pressure applied to the ball in the bonding process is absorbed by the wiring PDa, there arises a problem that the pressure bonding strength of the bonding wire BW is lowered. Even if the pressure in the bonding process is increased, the amount of the Al film pushed out in the opening OP only increases, and it is difficult to prevent a decrease in adhesive strength. When the bonding strength of the bonding wire BW is lowered, the bonding wire BW and the pad are not electrically connected to each other, so that the reliability of the semiconductor device is lowered. Further, when the pressure is increased, cracks may occur in the interlayer insulating film IL7a below the wiring PDa.

  Further, when the Al film is pushed upward in the opening OP, the side walls of the passivation film PSa at both ends of the opening OP receive pressure from the Al film. This may cause cracks in the passivation film PSa. For the same reason, the passivation film PSa may be peeled off from the upper surface of the wiring PDa. When Ag (silver) is used as the material of the bonding wire BW, the same problem as that of the Cu wire occurs.

  Next, a structure shown in FIG. 23 will be described as another comparative example. The semiconductor device of the comparative example shown in FIG. 23 has the same structure as the semiconductor device shown in FIG. However, although the bonding wire BW is made of Au (gold), the reaction layer of the Au wire and the Al film is not shown. Further, the semiconductor chip and the bonding wire BW connected to the pad are covered with a sealing resin film RS. The resin film RS is, for example, a mold resin film, and is made of, for example, an epoxy resin.

  Further, a crack CR is generated in a part of the passivation film PSa. The crack CR is not filled with the resin film RS or the like, and a space is formed in which no insulating film is formed. Although not shown, the semiconductor substrate under the wiring L6 is mounted on the die pad, and the lower surface of the die pad is also covered with the resin film RS. Although not shown, a resin film made of polyimide or the like may be formed between the resin film RS and the passivation film PSa.

  As shown in FIG. 23, a crack CR is generated in the passivation film PSa in the vicinity of the end of the upper surface of the wiring PDa. The crack CR is caused by the stress that the passivation film PSa receives from the resin film RS due to the shrinkage of the resin film RS.

  Here, since the film thickness of the wiring PDa covered by the passivation film PSa is large, it is necessary to increase the film thickness of the passivation film PSa. For this reason, the step between the passivation film PSa beside the wiring PDa and the passivation film PSa on the wiring PDa and the side wall inside the opening OP become large. Due to the large step, the pressure received by the passivation film PSa on the wiring PDa from the resin film increases, and the passivation film PSa is cracked to generate a crack CR. When the resin film made of polyimide or the like is formed, the passivation film PSa can receive stress from the resin film.

  On the other hand, if the thickness of the passivation film PSa is small, the step can be reduced and the height of the side wall inside the opening OP can be reduced, so that the passivation film PSa is separated from the resin film RS. The stress received can be reduced. However, the thickness of the passivation film PSa must be reduced because the thickness of the wiring PDa is large and the passivation film PSa needs to be formed with a thickness that can sufficiently cover the sidewall of the pad wiring PDa. It is difficult.

  In the comparative example described with reference to FIGS. 21 to 23, when a crack or peeling occurs in the passivation film PSa, moisture or the like invades into the space generated by the occurrence of the crack, so that deterioration of the wiring or the insulating film is remarkable. Thus, there arises a problem that the reliability of the semiconductor device is lowered.

  Here, in order to prevent the occurrence of cracks or peeling in the passivation film PSa described with reference to FIGS. 21 and 22, it is conceivable to increase the area of the opening OP. Thereby, in the comparative example shown in FIG. 21, the reaction layer ALL can be prevented from contacting the passivation film PSa. In the comparative example shown in FIG. 22, the extruded Al film is added to the passivation film PSa. This is because the stress can be reduced.

  In the comparative example described with reference to FIG. 23, it can be considered that the distance from the upper end portion of the wiring PDa to the end portion of the opening OP is increased in order to prevent the occurrence of the crack CR. This is because if the area where the upper surface of the wiring PDa is in contact with the passivation film PSa is increased, the stress received by the passivation film PSa from the resin film RS can be dispersed, and the generation of cracks CR can be prevented.

  However, in the semiconductor device of the comparative example described with reference to FIGS. 21 to 23, when the area of the pad opening OP or the area where the upper surface of the wiring PDa and the passivation film PSa are in contact with each other is increased as described above. Since the area occupied by the pad increases, miniaturization of the semiconductor device becomes difficult.

  The above problem described with reference to FIGS. 21 to 23 is caused by using a thick conductor film as a pad like the uppermost layer wiring. Therefore, in the semiconductor device of the present embodiment, the uppermost layer wiring having the largest film thickness among the multilayer wirings is not used as a pad, and as shown in FIG. Also, a pad PD having a small film thickness is provided.

  When the Au wire is connected to the pad PD of the present embodiment, the pad PD has a smaller film thickness than the pad shown in FIG. 21, that is, the wiring PDa, so that the supply amount of Al (aluminum) to the Au wire can be suppressed. Therefore, since the reaction time between the Au wire and the Al film can be shortened, the growth of the reaction layer made of the Au—Al alloy can be prevented. Therefore, since the generation of cracks or peeling in the passivation film PS can be prevented without increasing the opening area of the opening OP shown in FIG. 2, the semiconductor chip can be miniaturized. Thereby, the performance of the semiconductor device can be improved.

  Further, when the Cu wire is connected to the pad PD of the present embodiment, since the pad PD has a smaller film thickness than the wiring PDa which is the pad shown in FIG. 22, a Cu wire harder than the Al film is shown in FIG. The amount of sinking into the pad PD can be reduced. Further, since the amount of the Al film constituting the pad PD rising upward in the opening OP can be reduced, the Al film can prevent the passivation film PS from receiving pressure. Therefore, since the occurrence of cracks or peeling in the passivation film PS can be prevented without increasing the opening area of the opening OP, the semiconductor chip can be miniaturized. Thereby, the performance of the semiconductor device can be improved.

  In the present embodiment, the Cu wire can be prevented from being buried in the pad PD, and the Cu wire can be crimped onto the interlayer insulating film IL7b via the pad PD having a small film thickness. It is possible to prevent the pressure from being absorbed. Therefore, the Cu wire can be firmly connected to the pad PD by pressure bonding. For this reason, since the conduction | electrical_connection between Cu wire and pad PD can be ensured, the reliability of a semiconductor device can be improved. Even when the material of the bonding wire is Ag (silver), the same effect can be obtained.

  Further, since the pad PD has a smaller film thickness than the wiring PDa which is the pad shown in FIG. 23, the side wall of the pad PD shown in FIG. 2 has a passivation film PS (see FIG. 23) having a smaller film thickness than the passivation film PSa shown in FIG. 2). Therefore, since the thickness of the passivation film PS can be kept small, when the passivation film PS is covered with a resin film, the stress applied to the passivation film PS from the resin film can be reduced.

  Therefore, when the bonding wire is connected to the pad PD of the present embodiment and the semiconductor chip and the bonding wire are covered with the resin film, the passivation film is not increased without increasing the contact area between the upper surface of the pad PD and the passivation film PS. Since the occurrence of cracks or peeling in PS can be prevented, the semiconductor chip can be miniaturized. Thereby, the performance of the semiconductor device can be improved.

  Next, a method for manufacturing the semiconductor device of the present embodiment will be described with reference to FIGS. 4 to 15 are cross-sectional views showing a method for manufacturing a semiconductor device in the present embodiment. Since the manufacturing method of the semiconductor device of the present embodiment is in the manufacturing method of the uppermost layer wiring of the multilayer wiring and the pad thereon, the manufacturing process of the multilayer wiring and the semiconductor element below the uppermost layer wiring is as follows. Detailed description is omitted. The semiconductor element formed on the semiconductor substrate and the high-density wiring layer, medium-density wiring layer, and low-density wiring layer of the multilayer wiring can be formed by a known method. Here, the process after the formation of the wiring L6, the plug PL6, the interlayer insulating films IL6a and IL6b, and the semiconductor elements and wiring layers thereunder shown in FIG. 3 will be specifically described.

  First, a plurality of wiring layers are stacked on a semiconductor substrate. That is, after preparing the semiconductor substrate SB shown in FIG. 3, a semiconductor element such as MISFET Q1 is formed on the semiconductor substrate SB, and then the interlayer insulating film CL covering the semiconductor element and the interlayer insulating film CL are penetrated. Then, a plug PL1 connected to the semiconductor element is formed. Thereafter, a plurality of wiring layers including wirings electrically connected to the semiconductor element are stacked. FIG. 4 shows the interlayer insulating film IL6b constituting the sixth wiring layer and the wiring L6 embedded in the wiring trench penetrating the interlayer insulating film IL6b.

  Next, as shown in FIG. 4, after the interlayer insulating film IL6b and the wiring L6 are formed, the barrier insulating film SF and the interlayer insulating film IL7a are sequentially formed thereon by using, for example, a CVD (Chemical Vapor Deposition) method. Form. The barrier insulating film SF is an insulating film used as an etching stopper film in a later etching process, and is made of, for example, a SiCN film. The interlayer insulating film IL7a is made of, for example, a silicon oxide film. The barrier insulating film SF has a role to prevent Cu (copper) atoms in the wiring L6 mainly made of Cu (copper) from diffusing into the interlayer insulating film IL7a. Although not shown, a barrier insulating film may be formed in contact with the bottom surface of the interlayer insulating film IL6.

  Next, as shown in FIG. 5, a resist pattern RP1 made of a photoresist film is formed on the interlayer insulating film IL7a by using a photolithography technique. The resist pattern RP1 has an opening immediately above the wiring L6, and the upper surface of the interlayer insulating film IL7a is exposed at the bottom of the opening. Thereafter, etching is performed using the resist pattern RP1 as a mask to remove part of the interlayer insulating film IL7a and part of the barrier insulating film SF. As a result, the via hole VH1 that opens the laminated film including the barrier insulating film SF and the interlayer insulating film IL7a is formed, thereby exposing the upper surface of the wiring L6.

  Next, as shown in FIG. 6, after removing the resist pattern RP1, the barrier conductor film BL1, the main conductor film M1, and the barrier conductor film BU1 are formed on the wiring L6 and the interlayer insulating film IL7a by using, for example, a sputtering method. A third conductor film, which is a laminated film formed in order, is formed. The barrier conductor films BL1 and BU1 are, for example, a Ti (titanium) film or a TiN (titanium nitride) film, or a laminated film of a Ti (titanium) film and a TiN (titanium nitride) film. Each film thickness of the barrier conductor films BL1 and BU1 is, for example, about 100 nm. The main conductor film M1 is an Al (aluminum) film, and the film thickness of the main conductor film M1 is, for example, 1500 nm. Thereby, the via V1 including the barrier conductor film BL1 and the main conductor film M1 is formed in the via hole VH1.

  Next, as shown in FIG. 7, the barrier conductor film BU1, the main conductor film M1, and the barrier conductor film BL1 are patterned using a photolithography technique and a dry etching method. As a result, a wiring L7 composed of a laminated pattern of the barrier conductor film BL1, the main conductor film M1, and the barrier conductor film BU1 is formed.

  Next, as shown in FIG. 8, an interlayer insulating film IL7b is formed on the interlayer insulating film IL7a so as to cover the side wall and the upper surface of the wiring L7. The interlayer insulating film IL7b is formed by, for example, a CVD method. The interlayer insulating film IL7b is made of, for example, a silicon oxide film. The film thickness of the interlayer insulating film IL7b is 2000 nm or less. Here, the film thickness of the interlayer insulating film IL7b is made larger than the film thickness of the wiring L7. However, the film thickness of the interlayer insulating film IL7b may be smaller than the film thickness of the wiring L7.

  Next, as shown in FIG. 9, the upper surface of the interlayer insulating film IL7b is planarized using, for example, a CMP (Chemical Mechanical Polishing) method. At this time, the upper surface of the wiring L7 is not exposed from the interlayer insulating film IL7b. Note that in the case where the film thickness of the interlayer insulating film IL7b is smaller than the film thickness of the wiring L7, the planarization process may not be performed by the CMP method. Further, when the film thickness of the interlayer insulating film IL7b is larger than the film thickness of the wiring L7, the manufacturing process can be advanced without performing the planarization process.

  Next, as shown in FIG. 10, a resist pattern RP2 is formed on the interlayer insulating film IL7b by using a photolithography technique. The resist pattern RP2 is a photoresist film having an opening immediately above the wiring L7. Subsequently, by etching using the resist pattern RP2 as a mask, a part of the interlayer insulating film IL7b is opened to form a via hole VH2. The upper surface of the wiring L7 is exposed at the bottom of the via hole VH2.

  Next, as shown in FIG. 11, after removing the resist pattern RP2, the barrier conductor film BL2, the main conductor film M2, and the barrier conductor film BU2 are formed on the wiring L7 and the interlayer insulating film IL7b by using, for example, a sputtering method. A fourth conductor film which is a laminated film formed in order is formed. The barrier conductor films BL2 and BU2 are, for example, a Ti (titanium) film or a TiN (titanium nitride) film, or a laminated film of a Ti (titanium) film and a TiN (titanium nitride) film. Each film thickness of the barrier conductor films BL2 and BU2 is, for example, about 100 nm. The main conductor film M2 is an Al (aluminum) film, and the film thickness of the main conductor film M2 is, for example, 800 nm or less. Thereby, the via V2 including the barrier conductor film BL2 and the main conductor film M2 is formed in the via hole VH2. As shown in FIG. 11, the via V2 may include a barrier conductor film BU2 on the main conductor film M2.

  Next, as shown in FIG. 12, the upper surface of the interlayer insulating film IL7b is exposed by patterning the barrier conductor film BU2, the main conductor film M2, and the barrier conductor film BL2 using a photolithography technique and a dry etching method. . Thereby, a pad PD having a pattern in which the barrier conductor film BL2, the main conductor film M2, and the barrier conductor film BU2 are laminated is formed.

  Next, as shown in FIG. 13, a passivation film PS is formed on the interlayer insulating film IL7b so as to cover the side wall and the upper surface of the pad PD. The passivation film PS is formed by, for example, a CVD method. The passivation film PS is made of, for example, a silicon oxide film. The thickness of the passivation film PS is, for example, 1000 nm or less.

  Next, as shown in FIG. 14, the opening OP is formed by partially removing the passivation film PS using a photolithography technique and an etching method. The opening OP exposes only the upper surface of the pad PD. The via V2 and the opening OP are formed at positions that do not overlap in plan view. Thereafter, a semiconductor substrate (not shown) is diced to form a plurality of semiconductor chips with pads PD exposed on the upper surface. Thereby, the semiconductor device of the present embodiment is substantially completed. The planar layout in the vicinity of the pad PD has the shape shown in FIG.

  Although not shown here, an insulating film that exposes the pad PD at the bottom of the opening OP, for example, an insulating film made of polyimide or the like may be formed on the passivation film PS before the dicing step. Good.

  Next, as shown in FIG. 15, after the semiconductor chip is mounted on the die pad, the bonding wire BW is connected to the upper surface of the pad PD in order to electrically connect the lead around the die pad and the pad PD. Perform the process. The bonding wire BW is a conductor film mainly containing, for example, Au (gold), Ag (silver), or Cu (copper).

  When an Au wire is used, a reaction layer is formed by the reaction of the bonding wire BW and Al (aluminum) constituting the pad PD to form an alloy, so that the bonding wire BW has a high strength against the pad PD. Can be joined. On the other hand, when a bonding wire BW made of Ag (silver) or Cu (copper) is used, a reaction layer such as an Au wire is difficult to form, so the ball at the tip of the bonding wire BW is pressed against the upper surface of the pad PD. The bonding wire BW and the pad PD are firmly connected by pressure bonding.

  Below, the effect of the manufacturing method of the semiconductor device of this Embodiment is demonstrated using the semiconductor device of the comparative example shown in FIGS.

  As described above, in the semiconductor device of the comparative example shown in FIG. 21, the wiring PDa, which is the uppermost layer wiring among the multilayer wirings, is used as a pad, and an Au wire is connected to the pad. have. The wiring PDa is an Al film mainly containing Al (aluminum). For this reason, when an alloy reaction occurs between the Au wire and the Al film, a large amount of Al (aluminum) is supplied from the wiring PDa having a large film thickness, so that the reaction layer ALL grows greatly. In this case, the reaction layer ALL may cause cracks in the passivation film PSa by pressing the side walls of the passivation film PSa at both ends of the opening OP. Further, for the same reason, there is a possibility that the passivation film PSa is peeled off from the upper surface of the wiring PDa when the passivation film PSa is pushed by the reaction layer ALL.

  In addition, in the semiconductor device of the comparative example shown in FIG. 22, when a Cu wire harder than the Al film is connected to the wiring PDa, the bonding strength between the Cu wire and the pad is increased because the tip of the Cu wire enters the wiring PDa. The problem of deteriorating occurs. Further, when the Al film is pushed upward in the opening OP, the side walls of the passivation film PSa at both ends of the opening OP receive pressure from the Al film. This may cause cracks in the passivation film PSa. For the same reason, the passivation film PSa may be peeled off from the upper surface of the wiring PDa. When Ag (silver) is used as the material of the bonding wire BW, the same problem as that of the Cu wire occurs.

  In order to prevent the bonding wire BW from entering the wiring PDa, it is conceivable to use a bonding wire BW made of a relatively soft material such as Au (gold) instead of a hard material such as Cu (copper). However, since the Au wire is more expensive than the Cu wire or the like, the use of the Au wire causes a problem that the manufacturing cost of the semiconductor device increases.

  In the semiconductor device of the comparative example shown in FIG. 23, there is a problem that a crack CR is generated in a part of the passivation film PSa when the semiconductor chip is covered with the sealing resin film RS. The crack CR is caused by the stress that the passivation film PSa receives from the resin film RS due to the shrinkage of the resin film RS. Here, since the film thickness of the wiring PDa covered by the passivation film PSa is large, it is necessary to increase the film thickness of the passivation film PSa. For this reason, the step between the passivation film PSa beside the wiring PDa and the passivation film PSa on the wiring PDa and the side wall inside the opening OP become large. Due to the large step, the pressure received by the passivation film PSa on the wiring PDa from the resin film increases, and the passivation film PSa is cracked to generate a crack CR.

  As a method for preventing the occurrence of the crack CR, after forming the passivation film PSa covering the wiring PDa and before forming the opening OP, the upper surface of the passivation film PSa on the wiring PDa is polished by, for example, CMP. Thus, a method of reducing the thickness of the passivation film PSa on the wiring PDa can be considered. Thereby, the step between the passivation film PSa beside the wiring PDa and the passivation film PSa on the wiring PDa can be reduced, and the height of the side wall inside the opening OP can be reduced. For this reason, when the passivation film PSa is covered with the resin film RS, the stress that the passivation film PSa receives from the resin film RS can be reduced.

  However, if the upper surface of the passivation film PSa is polished by a CMP method or the like as described above, the number of semiconductor device manufacturing steps such as the polishing step and the subsequent cleaning step increases, which causes a problem of increasing the manufacturing cost of the semiconductor device.

  As a method for solving the problem that occurs in the semiconductor device of the comparative example described with reference to FIGS. 21 to 23, the area of the opening OP is increased, or from the upper surface end of the wiring PDa to the end of the opening OP. It is conceivable to increase the distance. However, in the semiconductor device of the comparative example described with reference to FIGS. 21 to 23, when the area of the pad opening OP or the area where the upper surface of the wiring PDa and the passivation film PSa are in contact with each other is increased as described above. Since the area occupied by the pad increases, miniaturization of the semiconductor device becomes difficult. Further, when the area of the semiconductor device increases, the manufacturing cost of the semiconductor device also increases.

  Therefore, in the semiconductor device of the present embodiment, the uppermost layer wiring having the largest film thickness in the multilayer wiring is not used as a pad, and the wiring L7 is formed on the wiring L7 which is the uppermost layer wiring as shown in FIG. Also, a pad PD having a small film thickness is provided.

  When the Au wire is connected to the pad PD of the present embodiment, the pad PD has a smaller film thickness than the pad shown in FIG. 21, that is, the wiring PDa, so that the supply amount of Al (aluminum) to the Au wire can be suppressed. Therefore, since the reaction time between the Au wire and the Al film can be shortened, the growth of the reaction layer made of the Au—Al alloy can be prevented. That is, even when the reaction layer grows, the end portion of the reaction layer does not reach the side wall inside the opening OP, and thus the passivation film PS can be prevented from receiving pressure from the reaction layer.

  Therefore, since the generation of cracks or peeling in the passivation film PS can be prevented without increasing the opening area of the opening OP shown in FIG. 15, the semiconductor chip can be miniaturized. Thereby, the performance of the semiconductor device can be improved.

  Further, when the Cu wire is connected to the pad PD of the present embodiment, since the pad PD has a smaller film thickness than the wiring PDa which is the pad shown in FIG. 22, a Cu wire harder than the Al film is shown in FIG. The amount of sinking into the pad PD can be reduced. Further, since the amount of the Al film constituting the pad PD rising upward in the opening OP can be reduced, the Al film can prevent the passivation film PS from receiving pressure. Therefore, since the occurrence of cracks or peeling in the passivation film PS can be prevented without increasing the opening area of the opening OP, the semiconductor chip can be miniaturized. Thereby, the performance of the semiconductor device can be improved. In addition, since a Cu wire that is less expensive than an Au wire or the like can be used, the manufacturing cost of the semiconductor device can be reduced.

  Further, the Cu wire can be firmly connected to the pad PD by pressure bonding. For this reason, the reliability of the semiconductor device can be improved. Even when the material of the bonding wire is Ag (silver), the same effect can be obtained.

  Further, since the pad PD has a smaller film thickness than the wiring PDa which is the pad shown in FIG. 23, the side wall of the pad PD shown in FIG. 2 has a passivation film PS (see FIG. 23) having a smaller film thickness than the passivation film PSa shown in FIG. 14). Therefore, since the thickness of the passivation film PS can be kept small, when the passivation film PS is covered with a resin film, the stress applied to the passivation film PS from the resin film can be reduced.

  Therefore, when the bonding wire is connected to the pad PD of the present embodiment and the semiconductor chip and the bonding wire are covered with the resin film, the passivation film is not increased without increasing the contact area between the upper surface of the pad PD and the passivation film PS. Since the occurrence of cracks or peeling in PS can be prevented, the semiconductor chip can be miniaturized. Thereby, the performance of the semiconductor device can be improved.

  In addition, it is not necessary to add a step of polishing the upper surface of the passivation film PS by a CMP method or the like to reduce the thickness of the passivation film PS, and thus it is possible to prevent an increase in the number of manufacturing steps of the semiconductor device. For this reason, the manufacturing cost of the semiconductor device can be reduced.

(Embodiment 2)
In this embodiment, arrangement of a plurality of wirings immediately below a pad will be described with reference to FIGS. FIG. 16 is a plan layout of the semiconductor device of this embodiment, and FIG. 17 is a cross-sectional view of the semiconductor device of this embodiment. 17 is a cross-sectional view taken along line BB in FIG.

  As shown in FIG. 16, the layout of the pad PD, the opening OP, and the via V2 is the same as that in the first embodiment. However, the wiring L7 is formed in a region that does not overlap with the opening OP in plan view, and the wiring L7a is formed at the same height as the wiring L7 in a region that overlaps with the opening OP in plan view. Note that a part of the wiring L7 may overlap with the opening OP in plan view.

  As shown in FIG. 17, both the wirings L7 and L7a are films of the same layer formed in contact with the upper surface of the interlayer insulating film IL7a. Similar to the wiring L7, the wiring L7a is a pattern including a barrier conductor film BL1, a main conductor film M1, and a barrier conductor film BU1 that are sequentially stacked on the interlayer insulating film IL7a. That is, the wiring L7a is the uppermost layer wiring constituting the multilayer wiring, and the wirings L7 and L7a have the same film thickness. That is, the wiring L7a is arranged alongside the wiring L7 in the direction along the main surface of the semiconductor substrate (not shown). In other words, the wiring L7a and the wiring L7 are formed at the same height.

  Here, the wirings L7 and L7a are separated from each other. Further, the wirings L7 and L7a are insulated from each other. However, the wirings L7 and L7a may be integrated in a region not shown, or may be electrically connected to each other. The wiring L7a as described above can be formed by appropriately processing the barrier conductor film BL1, the main conductor film M1, and the barrier conductor film BU1 in the patterning step described with reference to FIG.

  In the present embodiment, the same effect as in the first embodiment can be obtained. In addition, since the wiring L7a different from the wiring L7 can be provided immediately below the pad PD, the degree of freedom in wiring layout can be improved. Therefore, since the semiconductor chip can be miniaturized, the performance of the semiconductor device can be improved.

(Embodiment 3)
In this embodiment, a structure in which no wiring is arranged immediately below an opening where a pad is exposed will be described with reference to FIGS. FIG. 18 is a plan layout of the semiconductor device of this embodiment, and FIG. 19 is a cross-sectional view of the semiconductor device of this embodiment. 19 is a cross-sectional view taken along the line CC of FIG.

  As shown in FIG. 18, the layout of the pad PD, the opening OP, and the via V2 is the same as that in the first embodiment. However, the wiring L7 is formed in a region that does not overlap with the opening OP in plan view, and no wiring is formed in the region that overlaps with the opening OP in plan view at the same height as the wiring L7.

  As shown in FIG. 19, the uppermost layer wiring of the multilayer wiring is not formed immediately below the opening OP of the passivation film PS. That is, a wiring in the same layer as the wiring L7 is not formed immediately below the opening OP. That is, immediately below the opening OP, no wiring is formed between the interlayer insulating film IL7a and the interlayer insulating film IL7b. Therefore, immediately below the opening OP, the bottom surface of the interlayer insulating film IL7b and the top surface of the interlayer insulating film IL7a are all in contact.

  Here, when the uppermost layer wiring including the Al film having a relatively large film thickness is formed immediately below the opening OP and the film thickness of the interlayer insulating film IL7b immediately below the opening OP is small, the probe inspection is performed. When the inspection needle is pressed against the upper surface of the pad PD in the process, there is a possibility that a crack may occur in the interlayer insulating film IL7b immediately below the opening OP. In this case, even when a Cu wire or the like is connected to the pad PD with a large pressure, a crack may occur in the interlayer insulating film IL7b immediately below the opening OP. When such a crack occurs, there arises a problem that an accurate inspection result cannot be obtained in the probe inspection, and a problem that the reliability of the semiconductor device is lowered occurs.

  On the other hand, in the semiconductor device of the present embodiment, the uppermost layer wiring of a multilayer wiring including a relatively soft material such as Al (aluminum) and having a large film thickness is not disposed immediately below the opening OP. That is, the film thickness of the interlayer insulating film IL7b immediately below the opening OP is larger than the region where the wiring L7 is formed. Further, immediately below the opening OP, the bottom surface of the interlayer insulating film IL7b is in contact with the interlayer insulating film IL7a that is harder than the uppermost wiring. That is, the strength of the film directly under the opening OP and directly under the pad PD can be increased.

  Therefore, when the probe needle is pressed against the upper surface of the pad PD, it is possible to prevent a crack from occurring in the interlayer insulating film or the like under the pad PD. Similarly, when a Cu wire or the like is pressure-bonded to the pad PD, it is possible to prevent a crack from occurring in an interlayer insulating film or the like under the pad PD. Thereby, the reliability of the semiconductor device can be improved. In the present embodiment, the same effect as in the first embodiment can be obtained.

(Embodiment 4)
In this embodiment, formation of a dummy pad that is not used as a pad at the same height as the pad will be described with reference to FIGS. FIG. 20 is a cross-sectional view of the semiconductor device of this embodiment.

  As shown in FIG. 20, the semiconductor device of the present embodiment has the same structure as that of the first embodiment. However, in this embodiment, in addition to the structure described with reference to FIG. 2, a dummy pad DPD different from the pad PD is formed on the interlayer insulating film IL7b. Similar to the pad PD, the dummy pad DPD includes a barrier conductor film BL2, a main conductor film M2, and a barrier conductor film BU2 that are sequentially stacked on the interlayer insulating film IL7b. That is, the pad PD and the dummy pad DPD are second conductor films in the same layer. In other words, the pad PD and the dummy pad DPD are formed at the same height.

  That is, the dummy pad DPD is arranged side by side with the pad PD in the direction along the main surface of the semiconductor substrate (not shown). The dummy pad DPD and the pad PD are separated from each other, and a passivation film PS is embedded between the dummy pad DPD and the pad PD. The dummy pad DPD can be formed separately from the pad PD by appropriately processing the barrier conductor film BL2, the main conductor film M2, and the barrier conductor film BU2 in the patterning step described with reference to FIG.

  The upper surface of the dummy pad DPD is not exposed from the passivation film PS. That is, the upper surface of the dummy pad DPD is entirely covered with the passivation film PS. Further, the dummy pad DPD does not constitute a circuit. Further, the dummy pad DPD is not connected to other conductor films such as the uppermost layer wiring under the dummy pad DPD. That is, the dummy pad DPD is completely covered with the insulating film. The dummy pad DPD may be connected to other wiring such as the uppermost layer wiring, but even with such a configuration, the dummy pad DPD does not constitute a circuit.

  Here, the pad PD is a pattern formed using a dry etching method. When the area occupied by the pattern such as the pad PD on the semiconductor substrate differs depending on the product, it is necessary to change the etching conditions such as the dry etching time for each product. That is, the etching conditions for forming the pad PD by processing must be changed according to the ratio of the area occupied by the pad PD to be formed on the semiconductor substrate, that is, the occupation ratio.

  However, since it is not easy to change the etching conditions and perform patterning with high accuracy, if the etching conditions are changed for each product, the amount of the conductor film removed by dry etching tends to vary. In particular, the variation in the wafer surface becomes large. For this reason, there is a possibility that the dimensions of the pad formed by the patterning process may vary. Further, when the etching conditions are changed for each product in this way, there is a problem that the manufacturing cost of the semiconductor device increases.

  Therefore, in this embodiment, a dummy pad DPD is provided. Thereby, in each of the plurality of products, the occupation ratio of the conductor pattern in the same layer including the pad PD and the dummy pad DPD on the semiconductor substrate can be made constant. Therefore, the etching conditions for forming the pad PD by patterning can be made uniform in each patterning step of the plurality of types of products.

  Therefore, since it is possible to suppress variation in the etching amount in the patterning process of the pad PD, it is possible to prevent variation in the size of the pad PD. Thereby, the pad PD can be accurately formed with a desired dimension, and characteristics such as the resistance value of the pad PD can be obtained with a desired value. Therefore, the reliability of the semiconductor device can be improved. Further, it is possible to prevent the manufacturing cost of the semiconductor device from increasing due to changing the etching conditions for each product. In the present embodiment, the same effect as in the first embodiment can be obtained.

  Here, when the dummy pad DPD is not formed, since there is a wide area on the interlayer insulating film IL7b where no pad is present beside the pad PD, the area immediately above the interlayer insulating film IL7b exposed from the pad PD is present. There is a problem that a large step is generated between the upper surface of the passivation film PS and the upper surface of the passivation film PS immediately above the pad PD. That is, the level difference on the upper surface of the passivation film PS becomes large, and the upper surface of the passivation film PS cannot be made as flat as possible. In this case, as described with reference to FIG. 23, the stress received from the resin film covering the semiconductor chip concentrates on a portion where the level difference of the passivation film PS (see FIG. 20) is large, and there is a possibility that a crack may occur.

  Further, when a large step is generated on the upper surface of the passivation film PS (see FIG. 20), when a resin film such as a polyimide film is formed on the passivation film PS, or when the semiconductor chip is covered with the resin film after the bonding process In addition, there is a possibility that a gap is formed in the resin film or between the resin film and the passivation film PS in the vicinity of the portion where the step is generated. The presence of voids causes a decrease in strength of the semiconductor device, and also causes a decrease in reliability of the semiconductor device due to intrusion of moisture or the like into the resin film.

  On the other hand, in the present embodiment, the dummy pad DPD is formed side by side with the pad PD to prevent a large step from occurring on the upper surface of the passivation film PS in the region between the pad PD and the dummy pad DPD. it can. As a result, the upper surface of the passivation film PS can be flattened, and stress can be prevented from concentrating on the passivation film PS due to the step.

  In addition, since it is possible to prevent the generation of a step on the upper surface of the passivation film PS and make the upper surface of the passivation film PS flatter, it is possible to prevent a void from being formed when the passivation film PS is covered with a resin film. Can do. As a result, the strength of the semiconductor device can be prevented from being lowered, and moisture and the like can be prevented from entering the resin film. Therefore, the reliability of the semiconductor device can be improved.

  Although the invention made by the present inventors has been specifically described based on the embodiment, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  For example, in the first to fourth embodiments, Al (aluminum) is used as the main material of the wiring L7 that is the uppermost layer wiring, but the main material of the wiring L7 is a conductor material other than Al (aluminum). May be.

  In the first to fourth embodiments, Al (aluminum) is used as the main material of the pad PD. However, the main material of the pad PD is not limited to this, and for example, an alloy reaction with an Au wire or the like is easy. Any other conductive material may be used as long as the material is softer than Cu (copper).

ALL Reaction layer BU1, BU2, BL1, BL2 Barrier conductor film BW Bonding wire CL Interlayer insulating film CR Crack DPD Dummy pads IL1 to IL5, IL6a, IL6b, IL7a, IL7b Interlayer insulating films L1 to L7, L7a Wiring M1, M2 Main conductor Film OP Opening PD Pad PDa Wiring PL1-PL6 Plug PS, PSa Passivation film Q1 MISFET
RP1, RP2 Resist pattern RS Resin film SB Semiconductor substrate SF Barrier insulating film STI Element isolation region V1, V2 Via VH1, VH2 Via hole

Claims (18)

A multilayer wiring including a lower layer wiring and an uppermost layer wiring formed on the lower layer wiring;
A first conductor film for pads electrically connected to the uppermost layer wiring and formed on the uppermost layer wiring;
A first insulating film formed on the first conductor film, the opening of which exposes the upper surface of the first conductor film;
Have
The thickness of the said 1st conductor film is a semiconductor device smaller than the thickness of the said uppermost layer wiring. The semiconductor device according to claim 1,
The film thickness of the uppermost layer wiring is the largest among the thicknesses of the plurality of wirings constituting the multilayer wiring. The semiconductor device according to claim 1,
The first conductor film is a semiconductor device mainly containing Al. The semiconductor device according to claim 1,
The uppermost layer wiring and the first insulating film are separated from each other,
A semiconductor device, wherein a second insulating film is formed between the uppermost layer wiring and the first insulating film. The semiconductor device according to claim 1,
The semiconductor device, wherein the uppermost layer wiring and the first conductor film are not in contact with each other immediately below the opening, and the bottom surface of the first conductor film is in contact with the second insulating film. The semiconductor device according to claim 1,
The first conductor film is a semiconductor device that is used as the pad for connecting a wire mainly containing Au, Ag, or Cu on an upper surface thereof. The semiconductor device according to claim 1,
A semiconductor device, wherein wiring is provided in a layer immediately below the first conductor film and at the same height as the uppermost wiring. The semiconductor device according to claim 1,
A semiconductor device, wherein no wiring is provided in a layer having the same height as the uppermost layer wiring in a region immediately below the opening. The semiconductor device according to claim 1,
A second conductor film disposed at the same height as the first conductor film;
The film thickness of the second conductor film is smaller than the film thickness of the uppermost layer wiring,
The second conductor film is a semiconductor device that does not constitute a circuit. (A1) forming a multilayer wiring including the uppermost layer wiring and the lower layer wiring under the uppermost layer wiring
(B1) forming a first conductor film for pads electrically connected to the uppermost layer wiring on the uppermost layer wiring;
(C1) covering the upper surface of the first conductor film with a first insulating film;
(D1) exposing the upper surface of the first conductor film by removing part of the first insulating film to form an opening;
Have
The method for manufacturing a semiconductor device, wherein the film thickness of the first conductor film is smaller than the film thickness of the uppermost wiring layer. The method of manufacturing a semiconductor device according to claim 10.
The method of manufacturing a semiconductor device, wherein the film thickness of the uppermost layer wiring is the largest among the film thicknesses of the plurality of wirings constituting the multilayer wiring. The method of manufacturing a semiconductor device according to claim 10.
The method of manufacturing a semiconductor device, wherein the first conductor film mainly contains Al. The method of manufacturing a semiconductor device according to claim 10.
(A2) a step of covering the upper surface of the uppermost layer wiring with a second insulating film after the step (a1);
Further comprising
In the step (b1), the first conductor film is formed on the second insulating film. The method of manufacturing a semiconductor device according to claim 10.
The method for manufacturing a semiconductor device, wherein the uppermost layer wiring and the first conductor film are not in contact directly under the opening, and the bottom surface of the first conductor film is in contact with the second insulating film. The method of manufacturing a semiconductor device according to claim 10.
The method of manufacturing a semiconductor device, wherein the first conductor film is used as the pad for connecting a wire mainly containing Au, Ag, or Cu on an upper surface thereof. The method of manufacturing a semiconductor device according to claim 10.
The step (a1)
(A3) forming the lower layer wiring;
(A4) forming a third conductor film on the lower layer wiring;
(A5) forming the uppermost layer wiring and the first wiring by processing the third conductor film;
Have
In the step (b1), the first conductor film is formed immediately above the first wiring. The method of manufacturing a semiconductor device according to claim 10.
A method for manufacturing a semiconductor device, wherein no wiring is provided in a layer having the same height as the uppermost wiring layer in a region immediately below the opening. The method of manufacturing a semiconductor device according to claim 10.
The step (b1)
(B2) forming a fourth conductor film on the uppermost layer wiring;
(B3) forming the first conductor film and the second conductor film by processing the fourth conductor film;
Have
In the step (c1), the upper surfaces of the first conductor film and the second conductor film are covered with the first insulating film,
The method for manufacturing a semiconductor device, wherein the second conductor film does not constitute a circuit.

Images