TWI423329B - Passivation structure and fabricating method thereof - Google Patents

Description

Protective layer structure and manufacturing method thereof

The present invention relates to a protective layer structure and a method of fabricating the same, and more particularly to a method for fabricating an opening therein by using a two-stage protective layer structure.

The fabrication of the integrated circuit includes a number of elaborate and complex processes, such as a semiconductor process for forming various components on a wafer; and the formation of an inter-metal dielectric (IMD) layer and a metal layer. A plurality of inner interconnect layers are used to connect the end of the semiconductor component to the metal interconnect process of the pad layer above the uppermost interconnect layer. The pad layer disposed above the uppermost metal interconnect layer serves as an input/output terminal of the integrated circuit, which is usually protected by a passivation to isolate moisture, scratches, and other contamination. Wait.

In some special applications, such as fingerprint printers, the protective layer on the surface of the wafer must not only effectively insulate moisture, scratches and contamination. The protective layer must be pressed against the fingers and resistant to the environment. Salt layer, and film structure of electrostatic discharge (hereinafter referred to as ESD). In order to achieve the above object, conventional techniques employ a hard dielectric material such as tantalum nitride as a protective layer; and in view of the fact that the mechanical strength of the film is proportional to the cube of its thickness, and the protective layer must be able to withstand The test voltage of 10,000 volts and the ESD breakdown voltage requirements, the conventional technology also increases the thickness of the protective layer and the like to enhance the pressure resistance of the protective layer and the ability to resist ESD.

Please refer to FIG. 1 and FIG. 2 . FIG. 1 and FIG. 2 are schematic cross-sectional views of a conventional wafer having a thickened protective layer. As shown in FIG. 1, at least one main die region 102 and a scribe line region 104 are defined on the wafer 100, and the wafer 100 of the main die region 102 includes unillustrated Integrated circuit. An inter-metal dielectric (IMD) layer 110 is formed on the wafer 100, and a plurality of metal pads 112 are disposed on the IMD layer 110. The metal pad 112 in the main die region 102 can serve as an input/output terminal for the integrated circuit; and the metal pad 112 in the scribe region 104 can be used for testing. A protective layer 120 is formed on the metal pad 112 and the wafer 100, and then the protective layer 120 is patterned by a photo-etching-process (hereinafter referred to as PEP) to respectively correspond to the main grain region 102. An opening 122 exposing the metal pad 112 is formed in the scribe line region 104.

Please refer to Figure 2. Next, a protective layer 130 having a thicker thickness than the general application is formed on the wafer 100. After forming the thickened protective layer 130, another PEP patterned protective layer 130 is formed by the same mask used in the front PEP, and a plurality of corresponding openings 122 are formed in the protective layer 130. The opening 132 of the metal pad 112 can be exposed for subsequent fabrication of metal wiring. However, in the prior art, the crack of the protective layer 130 is often found at the opening 132, and the crack is particularly likely to occur in the protective layer 130 at the corner of the opening 132, and the occurrence of the crack often leads to protection. Layer 130 is less effective against ESD.

In addition, please continue to see Figure 2. In general, when the protective layer 120 is patterned, the deep trench is formed by etching down the metal pad 112 in the scribe region 104 to reduce the thickness of the scribe region 104, which is beneficial to the subsequent cutting process. And avoiding the stress generated during subsequent cutting to affect the main grain region 102. However, after forming such a thickened protective layer 130, the height difference between the main grain region 102 and the scribe line region 104 will inevitably increase, which easily affects the alignment of subsequent processes and causes the metal of the main grain region 102. The pad 112 easily causes the metal wire 140 to flow to the opening 132 in the scribe line region 104 to cause a short circuit when subsequently forming a gold bond 140 or even wire bonding.

Accordingly, it is an object of the present invention to provide a protective layer structure and a method of fabricating the same that prevent defects such as cracks and short circuits.

According to the scope of the invention provided by the present invention, there is provided a method of fabricating a protective layer structure, which first provides a wafer having a surface defining at least one main grain region and a dicing street, and the main grain region and the dicing A plurality of metal pads are respectively arranged in the road zone. Forming a patterned first protective layer on the surface of the wafer, the patterned first protective layer respectively having a plurality of first openings exposing the metal pads in the main die region and the scribe region The second opening. After the patterned first protective layer is formed, a patterned second protective layer is formed on the patterned first protective layer, and the patterned second protective layer fills the second regions in the scribe region Opening, and the patterned second protective layer has a plurality of third openings respectively corresponding to the first openings in the main die region to expose the metal pads.

According to the scope of the invention provided by the present invention, there is also provided a protective layer structure disposed on a wafer having a plurality of metal pads. The protective layer structure includes a patterned first protective layer disposed on the wafer, and the patterned first protective layer has a plurality of first circular openings for exposing the metal pads. The protective layer structure also includes a patterned second protective layer disposed on the patterned first protective layer, and the patterned second protective layer has a plurality of second corresponding to the first circular openings, respectively. Round opening.

According to the patent application scope provided by the present invention, there is further provided a protective layer structure disposed on a wafer, wherein the wafer surface defines at least one main grain region and a scribe channel region, the main grain region and the scribe line a plurality of metal pads are disposed in the region, the protective layer structure includes a patterned first protective layer disposed on the wafer, and the patterned first protective layer is in the main die region and the dicing region The system has a plurality of first openings and second openings respectively for exposing a plurality of metal pads. The protective layer structure further includes a patterned second protective layer disposed on the patterned first protective layer and filling the second openings in the scribe region, the patterned second protective layer having a plurality of And a third opening corresponding to the first openings in the main die region.

According to the protective layer structure and the manufacturing method thereof provided by the present invention, the protective layer structure and the opening therein are formed by the step of forming the patterned first protective layer and the patterned second protective layer in two stages, and the main crystal grains thereof The openings in the area are all rounded to avoid cracks in the corners of the protective layer structure in subsequent processes, which may result in the protective layer structure being unable to effectively resist ESD. In addition, the patterned second protective layer has a corresponding opening formed only in the opening in the main grain region to expose the metal pad in the main grain region for input/output of the integrated circuit; The opening in the scribe line area that was originally used to expose the metal pad is still filled with the patterned second protective layer. Therefore, it is possible to avoid that the height difference between the main grain area and the place where the metal pad is disposed in the scribe line area is too obvious, and the wire joint is overflowed to the scribe line area or the opening in the scribe line area to cause a short circuit.

Please refer to FIG. 3 to FIG. 9 . FIG. 3 to FIG. 9 are schematic diagrams showing a preferred embodiment of a method for fabricating an opening in a protective layer according to the present invention, wherein FIG. 3 is a partial view of a wafer. 4 to 6 are cross-sectional views taken along line A-A' in Fig. 3; and Figs. 7 to 9 are cross-sectional views taken along line BB' in Fig. 3 Figure. As shown in FIG. 4, a wafer 200 is first provided, the wafer 200 wafer surface defining at least one main grain region 202 and a scribe region 204. The wafer 200 includes completed semiconductor elements (not shown) and a plurality of interconnect layers not shown. For convenience of description, the uppermost metal inter-layer dielectric (IMD) layer 210 is illustrated. And the IMD layer 210 is a film layer having a thickness of about 13,000 (13K) angstrom. On the IMD layer 210, a plurality of metal pads 212, 214 made of conductors such as copper or aluminum are disposed in the main die region 202 and the scribe channel region 204, respectively.

Please continue to see Figure 4. Next, a patterned first protective layer 220 is formed on the surface of the wafer 200. The patterned first protective layer 220 is a dielectric film layer of a bi-layer structure, and the double-layer structure may include a hafnium oxide layer from bottom to top, for example, used in the preferred embodiment. A tetraethylorthosilicate (hereinafter referred to as TEOS) layer 222 and a tantalum nitride layer 224. One of the patterned first protective layers 220 has a thickness of between 7,000 angstroms and 13,000 angstroms. In the preferred embodiment, the thickness of the TEOS layer 222 is about 6,000 angstroms; and the thickness of the tantalum nitride layer 224 is 7,000 angstroms.

Please refer to FIG. 4 and FIG. 7 simultaneously, and the patterned first protective layer 220 can be patterned by a first lithography and etching process (PEP). After the first PEP, the patterned first protective layer 220 has a plurality of first openings 232 and second openings 234 exposing the metal pads 212, 214 in the main die region 202 and the dicing region 204, respectively. In the preferred embodiment, a test step may be further included after the patterned first protective layer 220 is formed and exposed by the second opening 234 in the scribe line region 204 for use as a test pad. Metal pad 214 was tested. In addition, as shown in FIG. 4 and FIG. 7, where the metal pad 214 is not disposed in the scribe line region 204, at least the first protective layer 220, IMD in the scribe region 204 is simultaneously etched by the first PEP. A dielectric layer or the like below the layer 210 and the IMD layer 210 forms a deep trench 236 around the metal pad 214 in the scribe region 204. In addition, in the preferred embodiment, the first opening 232 is circular; for the convenience of the process, the second opening 234 may also be circular without being limited thereto.

Please refer to Figure 5 and Figure 8. Subsequently, a second protective layer 240 is formed on the patterned first protective layer 220, and the second protective layer 240 fills the first opening 232, the second opening 234 and the deep trench 236. In the preferred embodiment, the second protective layer 240 is a tantalum nitride layer, but is not limited to other hard material layers such as tantalum carbide, diamond-like carbon, barium titanate, barium titanate. And a thickness of one of the second protective layers 240 may be between 20,000 angstroms and 150,000 angstroms.

Please refer to Figures 6 and 9. A second PEP is patterned to form the second protective layer 240 to obtain a patterned second protective layer 250. The patterned second protective layer 250 has a plurality of third openings 252 respectively corresponding to the first openings 232 in the main die region 202, and respectively exposing the metal pads 212, and the third openings 252 are also A circular opening. The exposed metal pad 212 serves as an input/output terminal of the integrated circuit after completing the subsequent steps of making a gold connection, bumping, or wire bonding. It should be noted that in the second PEP, no openings will be formed in the scribe line region 204, that is, the second opening 234 and the deep trench 236 are still completely the second protective layer 240 / patterned second protective layer. 250 is filled. Therefore, the thickened second protective layer 240 / patterned second protective layer 250 does not have any effect on the height difference between the main grain region 202 and the scribe region 204, particularly the adjacent scribe region 204 in the main grain region 202. . Therefore, in the subsequent step of wire bonding, the gold wire, the bump or the wire is prevented from overflowing to the scribe line region 204, and the opening of the wire bonding to the opening in the scribe channel region 204 can be fundamentally avoided. Causes a short circuit.

In addition, as shown in FIG. 9, the method of fabricating the protective layer provided by the present invention does not affect the deep trench 236 formed after the first and second PEPs in the scribe line region 204 where the metal pad 214 is not disposed. The location. Therefore, in the subsequent process, the scribe line region 204 can still avoid the damage caused by the stress generated during the cutting to the main grain region 202 by the arrangement of the deep groove 236.

Please refer back to Figures 3 and 6. According to the method of fabricating a protective layer structure provided by the present invention, a protective layer structure disposed on a wafer 200 can be provided. The protective layer structure includes a patterned first protective layer 220 disposed on the wafer 200, and the patterned first protective layer 220 has a plurality of circular openings 232 for exposing the plurality of metal pads 212. The protective layer structure further includes a patterned second protective layer 250 disposed on the patterned first protective layer 220, and the patterned second protective layer 250 also has a plurality of circular openings 252, and the circular opening 252 is Corresponding to the circular opening 232.

According to the protective layer structure provided by the present invention, the patterned first protective layer 220 is a two-layer structure and has a thickness of 7000 angstroms to 13,000 angstroms. As previously mentioned, the two-layer structure may include a hafnium oxide layer such as TEOS layer 222 and a tantalum nitride layer 224 from bottom to top. The thickness of the TEOS layer 222 is about 6000 angstroms; the thickness of the tantalum nitride layer 224 is 7000 angstroms. The patterned second protective layer 250 may comprise tantalum nitride, tantalum carbide, diamond-like carbon, barium titanate, barium titanate, cerium oxide, etc.; the thickness thereof is between 20,000 angstroms and 150,000 angstroms.

It should be noted that in the protective layer structure provided by the present invention, the openings 232 and 242 are circular, so that the crack of the protective layer structure at the corners in the subsequent process can be avoided. Of course, the opening 234 can be circular without being limited thereto.

In addition, in accordance with the method provided by the present invention, the wafer 200 defines a main die region 202 and a scribe region 204, and openings 232, 234 in the protective layer structure are disposed in the main die region 202 for exposing the main die. The metal pad 212 in the region 202 is used as an input/output terminal of the integrated circuit after the subsequent fabrication of gold wires, bumps or wire bonds. The opening 234 in the scribe line region 204 allows the metal pad 214 to be used as a test pad in the test step. However, it is worth noting that the patterned second protective layer 240 in the protective layer structure fills the opening 234, so that in the subsequent steps of making gold wires, bumps or wire bonding, the gold wire and the like can be prevented from overflowing to The kerf zone 204 can also substantially avoid the situation where the wire bond overflows into the opening in the scribe channel region 204 to cause a short circuit.

In summary, the method for fabricating a protective layer structure and the protective layer structure provided by the present invention form a protective layer structure by forming a patterned first protective layer and a patterned second protective layer in two stages. The opening therein has an opening in the main grain region to avoid the crack of the protective layer structure at the corners in the subsequent process, and the protective layer cannot effectively resist the ESD. According to the method of the present invention, the first protective layer is patterned by the first PEP to have an opening to expose the metal pad in the main die region and the scribe region, and to make the metal pad in the scribe region Can be used as a test pad. And patterning the second protective layer by the second PEP so as to have a corresponding opening only in the opening in the main grain region to expose the metal pad in the main grain region for use as an integrated circuit The input/output terminal; and the opening in the dicing area is still filled with the patterned second protective layer, so that the height difference between the main grain region and the metal pad in the scribe line region is prevented from being too obvious, resulting in gold When the connection or the like overflows into the scribe line area, it is fundamentally avoided that the gold connection or the like overflows into the opening in the dicing area to cause a short circuit.

The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should be within the scope of the present invention.

100. . . Wafer

102. . . Main grain zone

104. . . Cutting road area

110. . . Metal interlayer dielectric layer

112. . . Metal pad

120. . . Cover

122. . . Opening

130. . . The protective layer

132. . . Opening

140. . . Metal connection

200. . . Wafer

202. . . Main grain zone

204. . . Cutting road area

210. . . Metal interlayer dielectric layer

212. . . Metal pad

214. . . Metal pad

220. . . Patterned first protective layer

222. . . TEOS layer

224. . . Tantalum nitride layer

232. . . First opening

234. . . Second opening

236. . . Deep groove

240. . . Second protective layer

250. . . Patterned second protective layer

252. . . Third opening

1 and 2 are schematic cross-sectional views of a conventional wafer having a thickened protective layer;

3 to 9 are schematic views of a preferred embodiment of a method for fabricating an opening in a protective layer according to the present invention, wherein FIG. 3 is a partial top view of a wafer, and FIGS. 4 to 6 are Fig. 3 is a cross-sectional view taken along line A-A'; Fig. 7 through Fig. 9 are cross-sectional views taken along line BB' in Fig. 3.

200. . . Wafer

202. . . Main grain zone

204. . . Cutting road area

210. . . Metal interlayer dielectric layer

212. . . Metal pad

214. . . Metal pad

220. . . Patterned first protective layer

222. . . TEOS layer

224. . . Tantalum nitride layer

232. . . First opening

234. . . Second opening

250. . . Patterned second protective layer

252. . . Third opening

Claims (16)

A method of fabricating a protective layer structure, comprising the steps of: providing a wafer having at least one main grain region and a dicing region defined, and wherein the main grain region and the scribe region are respectively disposed Forming a plurality of metal pads; forming a patterned first protective layer on the surface of the wafer, the patterned first protective layer having a plurality of exposed metal pads in the main die region and the dicing region respectively An opening and a second opening; and forming a patterned second protective layer on the patterned first protective layer, the patterned second protective layer filling the second openings in the scribe region, and the The patterned second protective layer has a plurality of third openings that respectively expose the metal pads corresponding to the first openings in the main die region. The method of claim 1, wherein the metal pads disposed in the second opening of the scribe line region are used as test pads. The method of claim 2, further comprising a test step after forming the patterned first protective layer. The method of claim 1, wherein the patterned first protective layer is a bi-layer structure. The method of claim 4, wherein the two-layer structure comprises a tetraethylorthosilicate (TEOS) layer and a tantalum nitride layer. The method of claim 4, wherein the patterned first protective layer has a thickness ranging from 7000 angstroms to 13,000 angstroms. The method of claim 1, wherein the patterned second protective layer comprises a tantalum nitride layer. The method of claim 7, wherein one of the patterned second protective layers has a thickness of from 20,000 angstroms to 150,000 angstroms. The method of claim 1, wherein the first opening and the third opening are both circular. A protective layer structure disposed on a wafer, wherein the surface of the wafer defines at least one main grain region and a scribe region, and the main grain region and a scribe region are respectively provided with a plurality of metal pads, The protective layer structure includes: a patterned first protective layer disposed on the wafer, and the patterned first protective layer has a plurality of first openings in the main die region and the scribe region respectively And a second opening for exposing the metal pads; a patterned second protective layer disposed on the patterned first protective layer and filling the second openings in the scribe region, the patterned second protective layer having a plurality of third openings, respectively Corresponding to the first openings in the main grain region. The protective layer structure of claim 10, wherein the patterned first protective layer is a two-layer structure. The protective layer structure of claim 11, wherein the two-layer structure comprises a tetraethyl oxoane (TEOS) layer and a tantalum nitride layer. The protective layer structure of claim 11, wherein one of the patterned first protective layers has a thickness of between 7,000 angstroms and 13,000 angstroms. The protective layer structure of claim 10, wherein the patterned second protective layer comprises a tantalum nitride layer. The protective layer structure of claim 14, wherein one of the patterned second protective layers has a thickness of from 20,000 angstroms to 150,000 angstroms. The protective layer structure of claim 10, wherein the third openings and the first openings are both circular.