JP2013055189A - Manufacturing method of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a manufacturing method of a semiconductor device forming a pad having a thickness which is equal to or thicker than a predetermined value with a small number of processes.SOLUTION: According to this invention, an aluminum layer 22 is deposited above an interlayer insulation film 1 formed on a semiconductor substrate. An aluminum layer 24 is deposited on the aluminum layer 22. A photo-resist 7 is formed above the aluminum layer 24 of a pad region 102. Etching is performed by using the photo-resist 7 and thereby forming a pad upper layer 52 at the pad region 102 and removing the aluminum layer 24 of a wiring region 101. Then, a photo-resist 8 is formed so as to cover the pad upper layer 52 of the pad region 102 and form a wiring pattern at the wiring region 101. Etching is performed using the photo-resist 8 and thereby forming a pad lower layer 51 at the pad region 102 and forming wiring 2 at the wiring region 101.

Description

  The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device having resistance to damage during wire bonding.

  Generally, a semiconductor device is connected to an external circuit via a bonding wire. This bonding wire is bonded to a pad formed on the semiconductor substrate. The pad is connected to a wiring formed on the semiconductor substrate.

  The structure of the wiring and the pad in the semiconductor device is already widely known. For example, an example in which the pad is formed together with the uppermost wiring is disclosed (Patent Document 1). Hereinafter, a normal semiconductor device 400 according to this example will be described. FIG. 10 is a cross-sectional view showing a configuration of a normal semiconductor device 400. As shown in FIG. 10, the semiconductor device 400 is provided with a circuit portion 402 and a bonding pad portion 403. In the circuit portion 402, a circuit (not shown) is formed on a substrate (not shown), and an interlayer insulating film 401 is provided so as to cover the circuit. A wiring 407 is formed on the interlayer insulating film 401. The wiring 407 is formed by sequentially providing a titanium nitride layer 404, an aluminum layer 405, and a titanium nitride layer 406 in this order from the substrate side. The titanium nitride layers 404 and 406 are made of titanium nitride or titanium, and the aluminum layer 405 is made of aluminum or an aluminum alloy containing 0.1 to 1% by mass of copper.

  An interlayer insulating film 408 is provided so as to cover the wiring 407, and a through hole 410 in which a conductive member 413 is embedded is formed in the interlayer insulating film 408. The thickness of the interlayer insulating film 408 on the wiring 407 is, for example, less than 1 μm. The through hole 410 penetrates the interlayer insulating film 408 and the titanium nitride layer 406 and reaches the aluminum layer 405. Alternatively, the through hole 410 may penetrate the interlayer insulating film 408 and reach the titanium nitride layer 406. As a result, the conductive member 413 is connected to the aluminum layer 405. A wiring 418 is formed on the interlayer insulating film 408. The wiring 418 is connected to the conductive member 413 and thus connected to the wiring 407. The wiring 418 is formed by sequentially providing a titanium nitride layer 415, an aluminum layer 416, and a titanium nitride layer 417 in this order from the interlayer insulating film 408 side. The titanium nitride layers 415 and 417 are made of titanium nitride or titanium, and the aluminum layer 416 is made of aluminum or an aluminum alloy containing 0.1 to 1% by mass of copper. The aluminum layer 416 has a thickness of 0.3 to 1 μm, for example, and the titanium nitride layers 415 and 417 have a thickness of 0.01 to 0.1 μm, respectively. Further, a passivation film 420 is provided so as to cover the wiring 418. The passivation film 420 is made of, for example, a silicon oxide film, a silicon nitride film, or a silicon oxynitride film.

  On the other hand, in the bonding pad portion 403, interlayer insulating films 401 and 408 are provided on the substrate, and a recess 411 is formed on the surface of the interlayer insulating films 401 and 408. The bottom of the recess 411 may be located in the interlayer insulating film 408, may be located at the interface between the interlayer insulating film 401 and the interlayer insulating film 408, or may be located in the interlayer insulating film 401. A reinforcing layer 414 made of tungsten is embedded in the recess 411. The upper surface of the reinforcing layer 414 has the same height position as the upper surface of the interlayer insulating film 408. Therefore, the upper surface of the conductive member 413 in the circuit portion 402 has the same height position. The length of the reinforcing layer 414 is, for example, 100 to 120 μm, and the thickness is 1 μm or more.

  A bonding pad 419 is provided on the reinforcing layer 414. The bonding pad 419 is formed by sequentially providing a titanium nitride layer 415, an aluminum layer 416, and a titanium nitride layer 417 in this order from the interlayer insulating film 408 side. Therefore, the bonding pad 419 is in the same layer as the wiring 418 in the circuit portion 402. The width of the bonding pad 419 is 60 to 120 μm, for example. Then, a passivation film 420 is provided so as to cover the bonding pad 419. An opening 421 is formed at a position corresponding to the upper side of the aluminum layer 416 in the passivation film 420, and the aluminum layer 416 is exposed in the opening 421. The bonding pad 419 is connected to a circuit (not shown) of the circuit unit 402, and is a portion to which a probe needle is brought into contact at the time of a wafer test, and is connected to a stitch by wire bonding at the time of mounting. Part.

  In addition, examples of semiconductor devices having pads to which bonding wires are bonded have been proposed (Patent Documents 2 to 4). Patent Document 2 discloses a configuration in which a pad has two metal layers. The pad is bonded to the bonding wire through an opening provided in an insulating film covering the pad. Patent Document 3 discloses a configuration in which pads are formed on a wiring. In Patent Document 4, when a wiring is formed, a lower layer film for forming a wiring is left in a region where a pad is formed, and an upper layer film is formed thereon. Thereby, the lower layer film and the upper layer film are formed as a pad portion.

JP 2003-324122 A JP 2005-19493 A Japanese Patent Laid-Open No. 10-340920 JP-A-9-17792

  However, the inventor has found that the above-described example has the following problems. Until now, bonding wires made mainly of Au have been mainly used because of the ease of bonding work. However, in recent years, the use of bonding wires made of Cu has been progressing for the purpose of cost reduction and the like.

  Although the Cu bonding wire is advantageous in terms of cost, it is necessary to apply a larger amount of energy when bonding to the pad. For example, an ultrasonic wave is used for bonding a bonding wire and a pad, but a Cu bonding wire needs to introduce a higher intensity ultrasonic wave than an Au bonding wire. For this reason, when a Cu bonding wire is used, since the intensity of ultrasonic waves is large, the semiconductor substrate under the pad may be damaged, leading to a failure of the semiconductor device. Therefore, in order to use the Cu bonding wire, it is necessary to increase the thickness of the pad as compared with the case of using the Au bonding wire.

  However, in order to increase the thickness of the pad, it is necessary to increase the thickness of the conductive film for forming the pad. As a result, the film formation time of the conductive film and the etching time of the conductive film are extended. Therefore, for example, in the configurations of Patent Documents 1 to 4, throughput decreases.

  In the method for manufacturing a semiconductor device which is one embodiment of the present invention, a first aluminum layer is deposited over an interlayer insulating film formed over a semiconductor substrate, and a second aluminum layer is formed on the first aluminum layer. A first etching mask is deposited on the second aluminum layer in the pad region, and etching is performed using the first etching mask to form a pad upper layer in the pad region. In addition, the second aluminum layer in the wiring region is removed, and a second etching mask is formed so as to cover the pad upper layer in the pad region and to form a wiring pattern in the wiring region. By performing etching using the etching mask 2, a pad lower layer is formed in the pad region and a wiring is formed in the wiring region. In the method for manufacturing a semiconductor device which is one embodiment of the present invention, a pad can be formed using a pad lower layer and a pad upper layer. Therefore, a pad having a sufficient thickness can be formed with a small number of steps.

  ADVANTAGE OF THE INVENTION According to this invention, the manufacturing method of the semiconductor device which can form the pad which has thickness more than a predetermined value with few processes can be provided.

1 is a cross-sectional view schematically showing a configuration of a semiconductor device 100 according to a first embodiment. It is sectional drawing which shows the aspect by which the semiconductor device 100 concerning Embodiment 1 and a copper bonding wire are connected. 1 is a plan view schematically showing a configuration of a semiconductor device 100 according to a first embodiment. FIG. 6 is a cross-sectional view schematically showing a manufacturing process of the semiconductor device 100 according to the first embodiment. FIG. 6 is a cross-sectional view schematically showing a manufacturing process of the semiconductor device 100 according to the first embodiment. FIG. 6 is a cross-sectional view schematically showing a manufacturing process of the semiconductor device 100 according to the first embodiment. FIG. 6 is a cross-sectional view schematically showing a manufacturing process of the semiconductor device 100 according to the first embodiment. FIG. 6 is a cross-sectional view schematically showing a manufacturing process of the semiconductor device 100 according to the first embodiment. FIG. 6 is a cross-sectional view schematically showing a manufacturing process of the semiconductor device 100 according to the first embodiment. FIG. 6 is a cross-sectional view schematically showing a manufacturing process of the semiconductor device 100 according to the first embodiment. FIG. 6 is a cross-sectional view schematically showing a manufacturing process of the semiconductor device 100 according to the first embodiment. FIG. 6 is a cross-sectional view schematically showing a manufacturing process of the semiconductor device 100 according to the first embodiment. FIG. 5 is a cross-sectional view schematically showing a configuration of a semiconductor device 200 according to a second embodiment. 7 is a cross-sectional view schematically showing a manufacturing process of the semiconductor device 200 according to the second embodiment; FIG. 7 is a cross-sectional view schematically showing a manufacturing process of the semiconductor device 200 according to the second embodiment; FIG. 7 is a cross-sectional view schematically showing a manufacturing process of the semiconductor device 200 according to the second embodiment; FIG. FIG. 6 is a cross-sectional view schematically showing a configuration of a semiconductor device 300 according to a third embodiment. FIG. 6 is a plan view schematically showing a configuration of a semiconductor device 300 according to a third embodiment. 12 is a cross-sectional view schematically showing a manufacturing process of the semiconductor device 300 according to the third embodiment. FIG. 12 is a cross-sectional view schematically showing a manufacturing process of the semiconductor device 300 according to the third embodiment. FIG. 12 is a cross-sectional view schematically showing a manufacturing process of the semiconductor device 300 according to the third embodiment. FIG. 12 is a cross-sectional view schematically showing a manufacturing process of the semiconductor device 300 according to the third embodiment. FIG. 12 is a cross-sectional view schematically showing a manufacturing process of the semiconductor device 300 according to the third embodiment. FIG. 12 is a cross-sectional view schematically showing a manufacturing process of the semiconductor device 300 according to the third embodiment. FIG. 12 is a cross-sectional view schematically showing a manufacturing process of the semiconductor device 300 according to the third embodiment. FIG. 12 is a cross-sectional view schematically showing a manufacturing process of the semiconductor device 300 according to the third embodiment. FIG. 12 is a cross-sectional view schematically showing a manufacturing process of the semiconductor device 300 according to the third embodiment. FIG. 12 is a cross-sectional view schematically showing a manufacturing process of the semiconductor device 300 according to the third embodiment. FIG. 12 is a cross-sectional view schematically showing a manufacturing process of the semiconductor device 300 according to the third embodiment. FIG. 2 is a cross-sectional view showing a configuration of a normal semiconductor device 400. FIG.

  Embodiments of the present invention will be described below with reference to the drawings. In the drawings, the same elements are denoted by the same reference numerals, and redundant description is omitted as necessary.

Embodiment 1
A semiconductor device 100 according to a first embodiment of the present invention will be described. First, a cross-sectional configuration of the semiconductor device 100 will be described with reference to FIG. FIG. 1 is a cross-sectional view schematically showing the configuration of the semiconductor device 100 according to the first embodiment. Since the semiconductor device 100 according to the present embodiment focuses on the configuration of the uppermost wiring layer and the pad to which the bonding wire is bonded, the structure below the wiring layer such as the lower wiring, the substrate, and the well layer is omitted. doing.

  As shown in FIG. 1, the semiconductor device 100 is divided into a wiring region 101 and a pad region 102. The wiring region 101 is a region other than the pad region 102 described later, and is a region where the wiring 2 connected to an element such as a transistor is disposed. Hereinafter, unless otherwise specified, the wiring region 101 indicates a similar region. In the wiring region 101, the wiring 2 is formed on the interlayer insulating film 1 formed on the semiconductor substrate (not shown). The wiring 2 is a wiring formed in an element such as a transistor, and is composed of conductive layers 21 and 23 and an aluminum layer 22. The width of the wiring 2 is, for example, 0.24 μm. The aluminum layer 22 corresponds to the first aluminum layer.

  The conductive layer 21 is made of, for example, a laminated film of titanium and titanium nitride, and is formed on the interlayer insulating film 1. The aluminum layer 22 functions as an aluminum wiring in the wiring region 101 and is formed on the conductive layer 21. The thickness of the aluminum layer 22 is, for example, 450 nm. In addition, the aluminum layer 22 should just be aluminum in the main composition, for example, may contain copper (Cu) and silicon (Si). The conductive layer 23 is made of a laminated film of titanium and titanium nitride, for example, like the conductive layer 21, and is formed on the aluminum layer 22. The exposed interlayer insulating film 1 and the wiring 2 are covered with an insulating layer 3. The insulating layer 3 is made of, for example, silicon oxynitride (SiON). A protective film 4 made of, for example, photosensitive polyimide is formed on the insulating layer 3.

  The pad region 102 is a region used for connecting a bonding wire to the semiconductor device 100 from the outside of the semiconductor device 100. Therefore, the pad 5 to which the bonding wire is bonded is formed in the pad region 102. The pad 5 includes a pad lower layer 51 and a pad upper layer 52. The width W2 of the pad upper layer 52 is smaller than the width W1 of the pad lower layer 51. The pad upper layer 52 is preferably formed on the inner side by 2 μm or more from the outer periphery of the pad lower layer 51. In other words, the horizontal distance L1 between the side wall of the pad upper layer 52 and the side wall of the pad lower layer 51 is preferably 2 μm or more. Thereby, as described later, the coverage of the insulating film 3 can be improved. Since the pad lower layer 51 has the same layered structure as the wiring 2 in the wiring region 101, the description thereof is omitted.

  The pad upper layer 52 is composed of the aluminum layer 24 and the conductive layer 25. The aluminum layer 24 corresponds to the second aluminum layer. The aluminum layer 24 is formed on the conductive layer 23. The thickness of the aluminum layer 24 is, for example, 450 nm. In addition, the aluminum layer 24 should just be an aluminum main composition similarly to the aluminum layer 22, for example, may contain copper (Cu) and silicon (Si). The conductive layer 25 is made of, for example, titanium nitride and is formed on the aluminum layer 24.

  Further, the pad region 102 is covered with the insulating layer 3 similarly to the wiring region 101, and the protective film 4 is formed on the insulating layer 3. However, in the pad region 102, an opening 6 that penetrates the protective film 4, the insulating layer 3, and the conductive layer 25 is formed above the central portion of the aluminum layer 24. The opening 6 corresponds to the first opening. The opening 6 is formed 2 μm or more inside from the outer periphery of the aluminum layer 24. That is, the horizontal distance L2 between the side wall of the opening 6 and the side wall of the aluminum layer 24 is 2 μm or more. Note that the interface between the insulating layer 3 exposed in the opening 6 and the conductive layer 25 is parallel to the main surface of the interlayer insulating film 1. In general, the interface between the insulating layer and the conductive layer perpendicular to the main surface of the exposed interlayer insulating film 1 is vulnerable to thermal stress. Therefore, a phenomenon such as peeling may occur due to the thermal history. However, in this configuration, the interface between the insulating layer and the conductive layer perpendicular to the main surface of the interlayer insulating film 1 is not exposed through the opening. Therefore, this structure is excellent in the heat stress tolerance of the interface between an insulating layer and a conductive layer.

  FIG. 2 is a cross-sectional view illustrating an aspect in which the semiconductor device 100 according to the first embodiment is connected to a copper bonding wire. As shown in FIG. 2, the copper bonding wire 103 is bonded to the aluminum layer 24 through the opening 6. An alloy layer 26 is formed between the copper bonding wire 103 and the aluminum layer 24 at the time of bonding.

  Note that the total thickness of the pads 5 is required to be a predetermined value or more in order to suitably protect the semiconductor device 100 from damage applied when a copper bonding wire is bonded to the semiconductor device 100. In the semiconductor device 100 according to the present embodiment, if the thickness of the pad 5 is 800 nm or more, it is possible to suitably protect the semiconductor device 100 from damage during bonding of the copper bonding wire. In the above example, the thickness of the aluminum layers 22 and 24 is 450 nm, so the thickness of the pad 5 is 900 nm or more. Therefore, in the above-described example, it is possible to suitably protect the semiconductor device 100 from damage at the time of bonding the copper bonding wire.

  Further, as described above, since the interface between the insulating layer in the pad opening and the aluminum of the pad is exposed to the outside in parallel to the surface of the semiconductor device, peeling at the interface hardly occurs due to thermal stress.

  Next, a planar configuration of the semiconductor device 100 will be described with reference to FIG. FIG. 3 is a plan view schematically showing the configuration of the semiconductor device 100 according to the first embodiment. In FIG. 3, the insulating layer 3 and the protective film 4 are omitted to facilitate understanding of the planar structure of the semiconductor device 100. As shown in FIG. 3, wiring 2 and a pad layer are formed on the interlayer insulating film 1. In FIG. 3, the conductive layer 23 that is the uppermost layer of the pad lower layer 51 and the wiring 2, the conductive layer 25 that is the uppermost layer of the upper pad layer 52, and the aluminum layer 24 exposed by the opening 6 are displayed.

  As shown in FIG. 3, the pad upper layer 52 is formed in the center on the pad lower layer 51 with a smaller area. The opening 6 is formed in a smaller area at the center on the pad upper layer 52.

  Next, a method for manufacturing the semiconductor device 100 will be described. 4A to 4I are cross-sectional views schematically showing manufacturing steps of the semiconductor device 100 according to the first embodiment. First, the conductive layer 21, the aluminum layer 22, the conductive layer 23, the aluminum layer 24, and the conductive layer 25 are laminated in this order on the interlayer insulating film 1 by, for example, sputtering (FIG. 4A).

  Next, a photoresist 7 for forming the pad upper layer 52 is formed in the pad region 102 by, for example, photolithography (FIG. 4B). Photoresist 7 corresponds to the first etching mask. Then, the conductive layer 25 and the aluminum layer 24 are removed by performing etching such as RIE using the photoresist 7 as an etching mask. Thereby, the pad upper layer 52 is formed (FIG. 4C). At this time, the conductive layer 23 functions as an etching stopper layer. After the etching is completed, the photoresist 7 is removed by, for example, ashing (FIG. 4D).

  Next, a photoresist 8 for forming the wiring 2 and the pad lower layer 51 is formed in the wiring region 101 and the pad region 102 by, for example, photolithography. The photoresist 8 corresponds to the second etching mask. In order to protect the already produced pad upper layer 52, the photoresist 8 is formed so as to cover the pad upper layer 52 (FIG. 4E). At this time, the photoresist 8 is desirably formed so as to cover from the outer periphery of the pad upper layer 52 to the outside by 2 μm or more. Thereby, the horizontal distance L1 between the side wall of the pad upper layer 52 and the side wall of the pad lower layer 51 can be separated by 2 μm or more, and the level difference between the upper surface of the pad upper layer 52 and the upper surface of the interlayer insulating film 1 can be made in two stages can do. Thereby, the influence of a level | step difference can be relieve | moderated and the coverage of the insulating film 3 mentioned later can be improved.

  Then, the conductive layer 23, the aluminum layer 22, and the conductive layer 21 are removed by performing etching such as RIE using the photoresist 8 as an etching mask. Thereby, the wiring 2 and the pad lower layer 51 are formed (FIG. 4F). After the etching is completed, the photoresist 8 is removed by, for example, ashing (FIG. 4G).

  Next, the insulating layer 3 that covers the wiring region 101 and the pad region 102 is formed by, eg, CVD (FIG. 4H). Then, the protective film 4 is formed on the insulating layer 3 by, for example, photolithography. For example, the protective film 4 is formed by applying photosensitive polyimide, and then performing exposure and development. As a result, an opening 10 is formed in the protective film 4 above the pad upper layer 52 (FIG. 4I).

  Next, the insulating layer 3 and the conductive layer 25 are removed by performing etching such as RIE using the protective film 4 as an etching mask. Thereby, the opening 6 is formed. At this time, the opening 6 is formed 2 μm or more inside from the outer periphery of the aluminum layer 24. Thereby, the interface between the insulating film 3 exposed to the opening 6 and the conductive layer 25 can be parallel to the main surface of the interlayer insulating film 1. As described above, the semiconductor device 100 illustrated in FIG. 1 can be manufactured.

  Therefore, according to the method of manufacturing a semiconductor device according to the present embodiment, the wiring 2 and the pad 5 can be formed by collectively forming the aluminum layer and the conductive layer, and the total thickness of the pad 5 can be increased. It is possible to easily exceed the desired value.

  Further, according to the method of manufacturing a semiconductor device according to the present embodiment, there is no need to form a via that connects the wiring and the pad layer. Furthermore, it is not necessary to form separate conductive layers for forming wirings and conductive layers for forming pads. Therefore, according to the method for manufacturing a semiconductor device according to the present embodiment, the number of steps can be reduced as compared with a normal manufacturing method.

Embodiment 2
Next, the semiconductor device 200 according to the second embodiment of the present invention will be described. FIG. 5 is a cross-sectional view schematically showing the configuration of the semiconductor device 200 according to the second embodiment.

  As shown in FIG. 5, the semiconductor device 200 has a configuration in which an insulating layer 20 is added below the insulating layer 3 of the semiconductor device 100. The insulating layer 20 is made of, for example, silicon oxide (SiON). Since other cross-sectional configurations of the semiconductor device 100 are the same as those of the semiconductor device 100, description thereof is omitted.

  Next, a method for manufacturing the semiconductor device 200 will be described. Since the steps until the wiring 2 and the pad lower layer 51 are formed, that is, the steps shown in FIGS. 4A to 4G are the same as those of the semiconductor device 100 according to the first embodiment, the description thereof is omitted. Therefore, the steps different from those in Embodiment 1 will be described below. 6A to 6C are cross-sectional views schematically showing manufacturing steps of the semiconductor device 200 according to the second embodiment.

  After the formation of the wiring 2 and the pad lower layer 51 (FIG. 4G), the insulating layer 20 that covers the wiring region 101 and the pad region 102 is formed by, eg, bias plasma CVD. Thereby, the insulating layer 20 reduces the level | step difference produced by the wiring 2 and the pad 5 (FIG. 6A).

  Next, the insulating layer 3 is formed on the insulating layer 20 by, eg, CVD. Thereby, the step is embedded, and the upper layer of the insulating layer 3 is parallel to the main surface of the interlayer insulating film 1 (FIG. 6B). Then, the protective film 4 is formed on the insulating layer 3 by, for example, photolithography. For example, the protective film 4 is formed by applying photosensitive polyimide, and then performing exposure and development. As a result, the opening 10 is formed in the protective film 4 above the pad upper layer 52 (FIG. 6C).

  Next, the insulating layer 3 and the conductive layer 25 are removed by performing etching such as RIE using the protective film 4 as an etching mask. Thereby, the opening 6 is formed. As described above, the semiconductor device 200 illustrated in FIG. 4 can be manufactured.

  As described above, the manufacturing method of the semiconductor device according to the present embodiment can achieve the same effects as the manufacturing method of the semiconductor device according to the first embodiment. In addition, by providing the insulating layer 20, it is possible to further improve the coverage of the insulating layer 3 thereon.

Embodiment 3
Next, a semiconductor device 300 according to the third embodiment of the present invention will be described. First, a cross-sectional configuration of the semiconductor device 300 will be described with reference to FIG. The semiconductor device 300 according to the present embodiment is a configuration change example in which a lower layer wiring and a via are formed. FIG. 7 is a cross-sectional view schematically showing the configuration of the semiconductor device 300 according to the third embodiment.

  As shown in FIG. 7, the semiconductor device 300 includes a semiconductor substrate 32 under the interlayer insulating film 1. A lower layer wiring 31 is formed on the upper portion of the semiconductor substrate 32. A via 33 is formed between the lower surface of the conductive layer of the pad lower layer 51 and the upper surface of the lower layer wiring 31 so as to penetrate the interlayer insulating film 1. The via 33 is located below the pad lower layer 51, but is located outside the pad upper layer 52. Since other configurations of the semiconductor device 300 are the same as those of the semiconductor device 100, description thereof is omitted.

  Next, a planar configuration of the semiconductor device 300 will be described with reference to FIG. FIG. 8 is a plan view schematically showing the configuration of the semiconductor device 300 according to the third embodiment. In FIG. 8, the insulating layer 3 and the protective film 4 are omitted for easy understanding of the planar structure of the semiconductor device 300. In FIG. 8, the position of the via 33 is indicated by a broken line. As shown in FIG. 8, when viewed from above, the via 33 is located below the pad lower layer 51 outside the pad upper layer 52.

  Next, a method for manufacturing the semiconductor device 300 will be described. 9A to 9K are cross-sectional views schematically showing manufacturing steps of the semiconductor device 300 according to the third embodiment. First, the lower layer wiring 31 is formed on the semiconductor substrate 32 by a known method. Then, an interlayer insulating film 1 that covers the wiring region 101 and the pad region 102 is formed by, eg, CVD (FIG. 9A). Thereafter, an opening 34 is provided in the interlayer insulating film 1 by, for example, lithography, and a via 33 is formed by filling with a conductive material (FIG. 9B). The opening 34 of the interlayer insulating film 1 corresponds to the second opening. Thereafter, the conductive layer 21, the aluminum layer 22, the conductive layer 23, the aluminum layer 24, and the conductive layer 25 are stacked in this order on the interlayer insulating film 1 and the via 33 by, for example, sputtering (FIG. 9C).

  Next, a photoresist 7 for forming the pad upper layer 52 is formed in the pad region 102 by, for example, photolithography. At this time, the photoresist 7 is formed so as not to overlap with the via 33, that is, the via 33 is not located below the photoresist 7 (FIG. 9D). Then, the conductive layer 25 and the aluminum layer 24 are removed by performing etching such as RIE using the photoresist 7 as an etching mask. Thereby, the pad upper layer 52 is formed (FIG. 9E). At this time, the conductive layer 23 functions as an etching stopper layer. After the etching is completed, the photoresist 7 is removed by, for example, ashing (FIG. 9F).

  Next, a photoresist 8 for forming the wiring 2 and the pad lower layer 51 is formed in the wiring region 101 and the pad region 102 by, for example, photolithography. Note that the photoresist 8 is formed so as to cover the pad upper layer 52 in order to protect the already prepared pad upper layer 52. The photoresist 8 is formed so as to overlap with the via 33, that is, the via 33 is positioned below the photoresist 8 (FIG. 9G). Then, the conductive layer 23, the aluminum layer 22, and the conductive layer 21 are removed by performing etching such as RIE using the photoresist 8 as an etching mask. Thereby, the wiring 2 and the pad lower layer 51 are formed (FIG. 9H). After the etching is completed, the photoresist 8 is removed by, for example, ashing (FIG. 9I).

  Next, the insulating layer 3 that covers the wiring region 101 and the pad region 102 is formed by, eg, CVD (FIG. 9J). Then, the protective film 4 is formed on the insulating layer 3 by, for example, photolithography. For example, the protective film 4 is formed by applying photosensitive polyimide, and then performing exposure and development. As a result, an opening 10 is formed in the protective film 4 above the pad upper layer 52 (FIG. 9K).

  Next, the insulating layer 3 and the conductive layer 25 are removed by performing etching such as RIE using the protective film 4 as an etching mask. Thereby, the opening 6 is formed. As described above, the semiconductor device 300 illustrated in FIG. 7 can be manufactured.

  As mentioned above, according to the manufacturing method of the semiconductor device concerning this embodiment, even when there are other structures in a semiconductor substrate, it is possible to show the same operation effect as the manufacturing method of the semiconductor device concerning Embodiment 1. It is. In the manufacturing method of the semiconductor device according to the present embodiment, the via can be formed at a position where the pad upper layer does not exist. Therefore, when the copper bonding wire is bonded to the upper layer of the pad, the load applied to the via can be reduced and damage to the via can be prevented.

Other Embodiments The present invention is not limited to the above-described embodiments, and can be appropriately changed without departing from the spirit of the present invention. For example, the conductive layers 21 and 23 are made of a laminated film of titanium and titanium nitride, but can be replaced with other laminated films or a single-layer film made of, for example, titanium nitride. In addition, the conductive layers 21, 23, and 25 are not essential, and each of the conductive layers 21, 23, and 25 can be omitted as appropriate.

The insulating layer 3 is not limited to silicon oxynitride (SiON), and other insulating materials such as silicon oxide (SiO ₂ ) and silicon nitride (SiN) or a stacked layer thereof can also be used.

  The protective film 4 is made of photosensitive polyimide, but other photosensitive resins can also be used. Alternatively, a non-photosensitive resin may be applied and formed using photolithography and etching.

DESCRIPTION OF SYMBOLS 1 Interlayer insulating film 2 Wiring 3, 20 Insulating layer 4 Protective film 5 Pad 6, 10, 34 Opening 7, 8 Photoresist 21, 23, 25 Conductive layer 22, 24 Aluminum layer 26 Alloy layer 31 Lower layer wiring 32 Semiconductor substrate 33 Via 51 Pad lower layer 52 Pad upper layer 100, 200, 300, 400 Semiconductor device 101 Wiring region 102 Pad region 103 Copper bonding wire 401, 408 Interlayer insulating film 402 Circuit portion 403 Bonding pad portion 404 Titanium nitride layer 405, 416 Aluminum layer 406, 415, 417 Titanium nitride layers 407, 418 Wiring 410 Through hole 411 Recess 413 Conductive member 414 Reinforcing layer 419 Bonding pad 420 Passivation film 421 Opening

Claims (18)

Depositing a first aluminum layer over an interlayer insulating film formed on a semiconductor substrate;
Depositing a second aluminum layer on the first aluminum layer;
Forming a first etching mask on the second aluminum layer in the pad region;
Etching using the first etching mask to form a pad upper layer in the pad region, and to remove the second aluminum layer in the wiring region,
Forming a second etching mask so as to cover the pad upper layer of the pad region and to form a wiring pattern in the wiring region;
Etching using the second etching mask to form a pad lower layer in the pad region and to form a wiring in the wiring region;
A method for manufacturing a semiconductor device. The total thickness of the pad lower layer and the pad upper layer is 800 nm or more,
A method for manufacturing a semiconductor device according to claim 1. The thickness of the pad lower layer is 450 nm or more,
A method for manufacturing a semiconductor device according to claim 2. The pad upper layer has a thickness of 450 nm or more,
A method for manufacturing a semiconductor device according to claim 2. The pad upper layer has a thickness of 450 nm or more,
The thickness of the pad lower layer is 450 nm or more,
A method for manufacturing a semiconductor device according to claim 2. Depositing a first conductive layer on the first aluminum layer;
Depositing the second aluminum layer on the first conductive layer;
Removing the second aluminum layer by using the first conductive layer as an etching stopper layer;
A method for manufacturing a semiconductor device according to claim 1. Etching the first aluminum layer and the first conductive layer to form the pad lower layer and the wiring.
A method for manufacturing a semiconductor device according to claim 6. The pad upper layer has a smaller area on the interlayer insulating film than the pad lower layer,
A method for manufacturing a semiconductor device according to claim 1. The side wall of the pad upper layer is located inside the side wall of the pad lower layer,
A method for manufacturing a semiconductor device according to claim 8. The side wall of the upper layer of the pad is separated from the side wall of the lower layer of the pad by 2 μm or more.
A method for manufacturing a semiconductor device according to claim 9. Further forming a first insulating layer covering the pad lower layer, the pad upper layer and the wiring;
A first opening penetrating from an upper surface of the first insulating layer to an upper surface of the pad upper layer is formed in the first insulating layer;
The method for manufacturing a semiconductor device according to claim 1. The opening area of the first opening is smaller than the area of the pad upper layer,
A method for manufacturing a semiconductor device according to claim 11. The side wall of the first opening is located inside the side wall of the pad upper layer,
A method for manufacturing a semiconductor device according to claim 12. The sidewall of the first opening is separated from the sidewall of the pad upper layer by 2 μm or more.
A method for manufacturing a semiconductor device according to claim 13. A copper boarding wire is bonded to the upper surface of the pad upper layer,
The method for manufacturing a semiconductor device according to claim 1. A copper boarding wire is bonded to the upper surface of the pad upper layer through the first opening.
The method for manufacturing a semiconductor device according to claim 11. Forming a second insulating layer covering the pad lower layer, the pad upper layer and the wiring by a bias plasma CVD method;
Forming the first insulating layer on the second insulating layer;
Forming the first opening through the first and second insulating layers;
The method for manufacturing a semiconductor device according to claim 11. Forming a lower layer wiring on the semiconductor substrate;
Forming a second opening in the interlayer insulating film;
Forming a via in contact with the lower layer wiring filled in the second opening;
Forming the first aluminum layer so as to cover the interlayer insulating film and the via;
The pad upper layer is formed at a position where the via is not formed in the lower part,
The method for manufacturing a semiconductor device according to claim 1.

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