JP2016219749A - Semiconductor device and method of manufacturing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device and a method of manufacturing the same capable of suppressing generation of cracks in an insulating film located below wiring while suppressing increase in wiring resistance.SOLUTION: A semiconductor device 1 includes a semiconductor substrate 12. A passivation film 14 is formed on the semiconductor substrate 12. On the passivation film 14, wiring 15 that has a marginal part 42 and an inner part 43 located at an inner side from the marginal part 42 is formed. The marginal part 42 of the wiring 15 includes a thin-film part 44 (an inclined part 45) having a thickness smaller than that of the inner part 43.SELECTED DRAWING: Figure 4

Description

  The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device.

  Patent Document 1 discloses a semiconductor device including a semiconductor substrate, an insulating film formed on the semiconductor substrate, and a copper wiring formed on the insulating film.

JP 2010-171386 A

  One object of the present invention is to provide a semiconductor device and a method for manufacturing the same that can suppress the occurrence of cracks in an insulating film located under the wiring while suppressing an increase in wiring resistance.

  When a semiconductor device in which a wiring having a uniform thickness is formed on an insulating film is heated, the wiring and the insulating film are expanded by the applied heat. The wiring usually has a higher thermal expansion coefficient than that of the insulating film, and stress is generated in the direction along the surface of the insulating film by the thermal expansion. This stress may cause cracks in the insulating film. Insulating film cracks tend to occur around the wiring edge where stress from the wiring concentrates. Further, since the stress due to thermal expansion increases as the wiring becomes thicker, the risk of occurrence of cracks increases. Such a crack may be avoided by making the wiring thin, but in this case, there is a tradeoff in that the resistance value of the wiring increases.

Therefore, a semiconductor device according to the present invention includes a semiconductor substrate, an insulating film formed on the semiconductor substrate, an edge formed on the insulating film, and an inward portion located on the inner side of the edge. And the edge portion of the wiring includes a thin film portion having a thickness smaller than that of the inner portion.
According to the configuration of the present invention, the edge portion of the wiring located in the portion where the crack of the insulating film is likely to occur includes the thin film portion. As a result, the stress due to thermal expansion at the edge of the wiring can be reduced and the stress in the direction along the surface of the insulating film can be reduced, so that the occurrence of cracks in the insulating film around the edge of the wiring can be suppressed. Moreover, since generation | occurrence | production of a crack can be suppressed by a thin film part, since an inner part can be thickened, the high resistance of wiring can be suppressed.

In the semiconductor device, the thin film portion may include an inclined portion whose thickness gradually decreases in a direction away from the inward portion. According to this configuration, since the stress in the direction along the surface of the insulating film can be reduced satisfactorily, the occurrence of cracks in the insulating film can be well suppressed.
In the semiconductor device, it is preferable that the inclined portion has a surface that curves toward the inner portion of the wiring. According to this configuration, since the stress in the direction along the surface of the insulating film can be effectively reduced, it is possible to effectively suppress the occurrence of cracks in the insulating film around the edge of the wiring.

  In the semiconductor device, the wiring may include a first conductor layer formed on the insulating film and a second conductor layer formed on the first conductor layer. In this case, the first conductive layer may have a protruding portion that protrudes from the periphery of the second conductive layer, and the thin film portion may be formed by the protruding portion. Also with this configuration, the stress in the direction along the surface of the insulating film can be satisfactorily reduced, so that the occurrence of cracks in the insulating film can be well suppressed.

In the semiconductor device, it is preferable that the thin film portion is formed over the entire edge portion of the wiring. According to this configuration, since the stress in the direction along the surface of the insulating film can be reduced in the entire wiring, the occurrence of cracks in a wide range of the insulating film can be suppressed.
The semiconductor device may include a plurality of the wirings formed on the insulating film at intervals. In this case, the thin film portion may be formed in a portion of the edge portion where at least the plurality of wirings face each other between the plurality of wirings adjacent to each other.

  For example, when a plurality of wirings having no thin film portion are formed on the insulating film with a space therebetween, the insulating film positioned between the plurality of adjacent wirings receives stress from both wirings. Therefore, the risk of occurrence of cracks in the insulating film located between the plurality of wirings is higher than that of other portions. Therefore, by forming a thin film portion in a portion where at least a plurality of wirings are opposed to each other among the edge portions of the wiring, it is possible to reduce the risk of occurrence of cracks in the insulating film between the plurality of adjacent wirings.

  The semiconductor device may include a plurality of the wirings formed on the insulating film at intervals. In this case, the thin film portion may be formed at a portion where at least a plurality of the wirings are opposed to each other at a distance of 20 μm or less among the plurality of adjacent wirings. Even in such a configuration, it is possible to suppress the occurrence of cracks in the insulating film located between a plurality of adjacent wirings. In particular, if the configuration is such that the thin film portion is disposed at the edge of the wiring limited to a portion where the distance between the wirings is short, an increase in wiring resistance can be suppressed because the wiring cross-sectional area at other portions can be increased.

  In the semiconductor device, the wiring may include a metal containing copper as a main component, and the insulating film may include a nitride film or an oxide film. There is a difference in coefficient of thermal expansion between the copper-based metal and the nitride film or oxide film, but since the cracks can be suppressed by the thin film part, wiring is formed well on the nitride film or oxide film it can. In addition, by including a metal whose main component is copper, the resistance of the wiring can be reduced.

In the semiconductor device, the wiring may include a metal whose main component is aluminum, and the insulating film may include an oxide film. Although there is a difference in coefficient of thermal expansion between the metal containing aluminum as a main component and the oxide film, cracks can be suppressed by the thin film portion, so that the wiring can be satisfactorily formed on the oxide film.
The semiconductor device may further include a barrier film interposed between the wiring and the insulating film.

In the semiconductor device, the inner portion of the wiring may have a thickness of 20 μm or less.
The semiconductor device may further include a multilayer wiring structure formed on the semiconductor substrate and having a plurality of wiring layers stacked via an interlayer insulating film. In this case, the insulating film may be formed on the multilayer wiring structure so as to cover the multilayer wiring structure, and the wiring may be formed on the insulating film as a top layer wiring.

When the side surface of the uppermost layer wiring is not supported by a protective film or the like, the insulating film cracks due to the thermal expansion of the wiring are likely to occur. In such a case, the occurrence of cracks can be avoided while suppressing an increase in the wiring resistance value by applying a wiring structure having a thin film portion at the edge of the wiring.
The semiconductor device may further include a bonding wire electrically connected to the wiring. For example, when a bonding wire is connected to a wiring, the semiconductor substrate or the like may be heated to a temperature of 200 ° C. or higher (for example, about 260 ° C.). The applied heat is transferred to the wiring directly or via a semiconductor substrate or the like, and causes thermal expansion thereof. At this time, the thin film portion of the wiring relieves stress concentration at the edge portion of the wiring, so that generation of cracks in the insulating film can be suppressed.

The bonding wire may include a copper wire or a gold wire.
The semiconductor device includes an on-wiring insulating film formed on the insulating film so as to cover the wiring, and a rewiring formed on the on-wiring insulating film so as to be electrically connected to the wiring. May further be included. The said structure WHEREIN: The bonding wire electrically connected to the said rewiring may further be included. For example, when connecting the bonding wire to the rewiring, the semiconductor substrate or the like may be heated to a temperature of 200 ° C. or higher (for example, about 260 ° C.). The applied heat is transferred to the wiring through the semiconductor substrate, rewiring, or the like. At this time, since the concentration of stress at the edge of the wiring is alleviated by the thin film portion of the wiring, cracks in the insulating film can be suppressed.

  The semiconductor device may further include a connection electrode electrically connected to the wiring and a wiring substrate having a bonding surface in which the semiconductor substrate is flip-chip bonded via the connection electrode. For example, when the connection electrode is connected to the wiring substrate, the semiconductor substrate may be heated to a temperature of 200 ° C. or higher (for example, about 260 ° C.). The applied heat is transmitted to the wiring through the semiconductor substrate, the connection electrode, and the like. At this time, since the stress concentration at the wiring edge is alleviated by the thin film portion of the wiring, cracks in the insulating film can be suppressed.

  The semiconductor device may further include a land disposed on a surface opposite to the bonding surface of the wiring substrate and electrically connected to the wiring via a via electrode. For example, the semiconductor device is mounted on a mounting board via solder that contacts the land. During this mounting, the semiconductor device is heated to melt the solder. Thereby, the wiring is also heated, but the concentration of stress at the edge of the wiring is alleviated by the action of the thin film portion. Thereby, the crack of the insulating film resulting from the heating at the time of mounting can be suppressed.

  The semiconductor device may further include a connection electrode electrically connected to the wiring, and a sealing resin that covers a front surface, a back surface, and a side surface of the semiconductor substrate so as to expose the connection electrode. . For example, the connection electrode may be formed as an external terminal for achieving electrical connection with the outside. In this case, the semiconductor device may be mounted on the mounting substrate via solder in contact with the connection electrode. During this mounting, the semiconductor device is heated to melt the solder. Thereby, although the wiring is also heated, the concentration of stress at the edge of the wiring is alleviated by the action of the thin film portion of the wiring. Thereby, the crack of the insulating film resulting from the heating at the time of mounting can be suppressed.

  The method for manufacturing a semiconductor device according to one aspect of the present invention includes a step of forming an insulating film on a semiconductor substrate, an opening for selectively exposing the insulating film, and the direction along the direction toward the insulating film. A cover film forming step of forming on the insulating film a cover film having an inclined surface that partitions the opening so that the opening width of the opening gradually widens; and a conductor is buried in the opening to form the cover film Forming a wiring including an inclined portion aligned with the inclined surface.

  According to this method, a semiconductor substrate, an insulating film formed on the semiconductor substrate, a wiring formed on the insulating film and having an edge portion and an inner portion located on the inner side of the edge portion, Is manufactured. An inclined portion having a thickness that gradually decreases in the direction away from the inner portion is formed at the edge of the wiring. This inclined portion provides a thin film portion having a thickness smaller than the inner portion at the edge of the wiring. Thereby, even if heat applied to the semiconductor substrate or the like is transferred to the wiring during the manufacturing process after the wiring is formed, the thermal expansion of the edge of the wiring can be reduced, so that the edge is along the surface of the insulating film. Stress generated in the direction can be reduced. As a result, it is possible to suppress the occurrence of cracks in the insulating film around the edge of the wiring. Moreover, since generation | occurrence | production of a crack can be suppressed by a thin film part, since an inner part can be thickened, the resistance value increase of wiring can be suppressed.

  In the method, the cover film having the curved inclined surface that curves toward the opening is formed in the cover film forming step, and the curve that matches the inclined surface of the cover film is formed in the wiring forming step. It is preferable that the wiring including the inclined portion having a surface is formed. According to this method, the wiring including the inclined portion having the surface curved toward the inward side is formed on the insulating film. Thereby, since the stress in the direction along the surface of the insulating film can be effectively reduced, it is possible to effectively suppress the occurrence of cracks in the insulating film around the edge of the wiring.

In the method, the cover film may include a photosensitive resin, and the opening may be formed by selectively exposing the cover film.
The method may further include a step of connecting a bonding wire to the wiring by setting the semiconductor substrate to a temperature of 200 ° C. or higher after the wiring forming step. Even when the temperature of the semiconductor substrate is increased as in this method, it is possible to suppress the occurrence of cracks in the insulating film.

  A method of manufacturing a semiconductor device according to another aspect of the present invention includes a step of forming an insulating film on a semiconductor substrate, and a step of forming a first cover film having a first opening that selectively exposes the insulating film. Burying a conductor in the first opening to form a first conductor layer in the first opening; removing the first cover film; and selectively exposing the first conductor layer. Forming a second cover film having a second opening, and filling the second opening with a conductor to form a second conductor layer in the second opening. In the step of forming the second cover film, the second opening is formed so that the first conductor layer protrudes from the periphery of the second opening.

  According to this method, a semiconductor substrate, an insulating film formed on the semiconductor substrate, a wiring formed on the insulating film and having an edge portion and an inner portion located on the inner side of the edge portion, Is manufactured. More specifically, the wiring includes a first conductor layer and a second conductor layer. The inner portion of the wiring includes the first conductor layer and the second conductor layer, and has a thickness corresponding to the total thickness of these. On the other hand, the edge portion of the wiring includes a protruding portion of the first conductor layer, and this protruding portion provides a thin film portion having a smaller film thickness than the inner portion. Thereby, during the manufacturing process, when the wiring is heated, the thermal expansion of the edge of the wiring (the protruding portion of the first conductor layer) can be reduced, so that the direction along the surface of the insulating film in the edge It is possible to avoid the occurrence of a large stress. As a result, the generation of cracks in the insulating film around the edge of the wiring can be suppressed. Moreover, since generation | occurrence | production of a crack can be suppressed by the thin film part of a wiring edge part, since an inner part can be thickened, the increase in wiring resistance can be suppressed.

FIG. 1 is a bottom view showing the semiconductor device according to the first embodiment of the present invention. FIG. 2 is a plan view showing the internal structure of the semiconductor device of FIG. FIG. 3 is a cross-sectional view taken along section line III-III in FIG. FIG. 4 is an enlarged view of a portion surrounded by a broken-line circle IV in FIG. 3, and is a diagram showing an example of wiring. FIG. 5A is a diagram for explaining a part of the manufacturing process of the wiring of FIG. 4. FIG. 5B is a diagram showing a step subsequent to FIG. 5A. FIG. 5C is a diagram showing a step subsequent to FIG. 5B. FIG. 5D is a diagram showing a step subsequent to FIG. 5C. FIG. 5E is a diagram showing a step subsequent to that in FIG. 5D. FIG. 5F is a diagram showing a step subsequent to that in FIG. 5E. FIG. 5G is a diagram showing a step subsequent to that in FIG. 5F. FIG. 5H is a diagram showing a step subsequent to that in FIG. 5G. FIG. 6 is a cross-sectional view showing another embodiment of the wiring. FIG. 7A is a diagram for explaining a part of the manufacturing process of the wiring of FIG. 6. FIG. 7B is a diagram showing a step subsequent to FIG. 7A. FIG. 7C is a diagram showing a step subsequent to FIG. 7B. FIG. 7D is a diagram showing a step subsequent to FIG. 7C. FIG. 7E is a diagram showing a step subsequent to FIG. 7D. FIG. 7F is a diagram showing a step subsequent to that in FIG. 7E. FIG. 7G is a diagram showing a step subsequent to that in FIG. 7F. FIG. 7H is a diagram showing a step subsequent to FIG. 7G. FIG. 7I is a diagram showing a step subsequent to that in FIG. 7H. FIG. 8 is an enlarged cross-sectional view showing a portion where the wiring of the semiconductor device according to the second embodiment of the present invention is formed. FIG. 9 is a sectional view showing a semiconductor device according to the third embodiment of the present invention. FIG. 10 is a sectional view showing a semiconductor device according to the fourth embodiment of the present invention. FIG. 11 is a sectional view showing a semiconductor device according to the fifth embodiment of the present invention. FIG. 12 is an enlarged cross-sectional view showing a portion where the wiring of the semiconductor device according to the sixth embodiment of the present invention is formed. FIG. 13A is a diagram for explaining a part of the manufacturing process of the wiring of FIG. FIG. 13B is a diagram showing a step subsequent to FIG. 13A. FIG. 13C is a diagram showing a step subsequent to FIG. 13B. FIG. 13D is a diagram showing a step subsequent to FIG. 13C. FIG. 13E is a diagram showing a step subsequent to that in FIG. 13D. FIG. 13F is a diagram showing a step subsequent to that in FIG. 13E. FIG. 13G is a diagram showing a step subsequent to that in FIG. 13F. FIG. 14 is a cross-sectional view showing a first modification of the wiring. FIG. 15 is a cross-sectional view showing a second modification of the wiring. FIG. 16 is a cross-sectional view showing a third modification of the wiring. FIG. 17 is a cross-sectional view showing a fourth modification of the wiring.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.
<First Embodiment>
FIG. 1 is a bottom view showing a semiconductor device 1 according to the first embodiment of the present invention. FIG. 2 is a plan view showing the internal structure of the semiconductor device 1 of FIG. FIG. 3 is a cross-sectional view taken along section line III-III in FIG.

  The semiconductor device 1 is a semiconductor device to which QFN (Quad Flat Non-leaded Package) is applied. The semiconductor device 1 includes a semiconductor chip 2, a die pad 3, leads 4, bonding wires 5, and a resin package 6 that seals them. The outer shape of the resin package 6 (semiconductor device 1) is a flat rectangular parallelepiped shape. A plurality of pads 7 are arranged on the surface of the semiconductor chip 2. Each pad 7 is formed, for example, at the peripheral edge of the semiconductor chip 2. Each pad 7 is electrically connected to, for example, a semiconductor element. A back metal 8 made of a metal layer such as gold (Au), nickel (Ni), or silver (Ag) is formed on the back surface of the semiconductor chip 2.

  The die pad 3 and the lead 4 are formed by punching a metal thin plate (for example, a copper thin plate). A plated layer 9 made of silver is formed on the surfaces of the die pad 3 and the leads 4. The die pad 3 has a square shape in plan view, and the semiconductor chip 2 is disposed at the center thereof. At the peripheral edge of the back surface of the die pad 3, a recess having a substantially elliptical cross section is formed over the entire circumference by crushing from the back surface side. A sealing resin constituting the resin package 6 enters the recess.

  Thereby, the peripheral part of the die pad 3 is sandwiched by the sealing resin (resin package 6) from above and below, so that the die pad 3 is prevented from falling off from the resin package 6 (preventing detachment). The back surface of the die pad 3 is exposed from the back surface of the resin package 6 except for a portion recessed in an approximately elliptical cross section. A plating layer 10 made of solder is formed on the back surface of the die pad 3 exposed from the resin package 6.

  The same number (for example, nine) of leads 4 is provided at a position facing each side surface of the die pad 3. At each position facing the side surface of the die pad 3, the lead 4 extends in a direction perpendicular to the facing side surface and is arranged at equal intervals in a direction parallel to the side surface. At the end of the back surface of the lead 4 on the die pad 3 side, a recess having an approximately elliptical cross section is formed by crushing from the back surface side. A sealing resin constituting the resin package 6 enters the recess.

  As a result, the end of the lead 4 on the die pad 3 side is sandwiched from above and below by the sealing resin (resin package 6), and the lead 4 is prevented from falling off (resining) from the resin package 6. The back surface of the lead 4 is exposed from the back surface of the resin package 6 except for a portion recessed in a substantially elliptical cross section. Further, the side surface of the lead 4 opposite to the die pad 3 side is exposed from the side surface of the resin package 6. A plating layer 10 made of solder is formed on a portion of the back surface of the lead 4 exposed from the resin package 6.

  In this embodiment, the back surface of the semiconductor chip 2 is bonded to the surface of the die pad 3 (plating layer 9) via the bonding material 11 with the surface on which the pads 7 are disposed facing upward. . The bonding material 11 is, for example, a solder paste. When electrical connection between the semiconductor chip 2 and the die pad 3 is not required, the back metal 8 is omitted, and the back surface of the semiconductor chip 2 is placed on the surface of the die pad 3 with a bonding material made of an insulating paste or the like. May be joined together. In this case, the plating layer 9 on the surface of the die pad 3 may be omitted.

The bonding wire 5 has one end bonded to the pad 7 of the semiconductor chip 2 and the other end bonded to the surface of the lead 4. The bonding wire 5 includes, for example, a copper wire or a gold wire.
FIG. 4 is an enlarged view of a portion surrounded by a broken-line circle IV in FIG.

The semiconductor chip 2 includes a semiconductor substrate 12, a multilayer wiring structure 13, a passivation film 14 as an example of an insulating film of the present invention, and a wiring 15. The semiconductor substrate 12 is made of, for example, a silicon substrate having an element formation surface 16 on which semiconductor elements (diodes, transistors, resistors, capacitors, etc.) are formed.
The multilayer wiring structure 13 has a plurality of wiring layers stacked in order from the element formation surface 16 of the semiconductor substrate 12 via an interlayer insulating film. In the present embodiment, the multilayer wiring structure 13 includes a first metal layer 18 stacked on the element formation surface 16 of the semiconductor substrate 12 via the first interlayer insulating film 17 and a first metal via the second interlayer insulating film 19. A second metal layer 20 stacked on the metal layer 18 and a third interlayer insulating film 21 covering the second metal layer 20 are included. The first interlayer insulating film 17, the second interlayer insulating film 19, and the third interlayer insulating film 21 include an insulating material such as silicon oxide (SiO ₂ ) and silicon nitride (SiN), for example. The first metal layer 18 and the second metal layer 20 contain aluminum.

  An upper surface barrier film 22 and a lower surface barrier film 23 are formed on the upper and lower surfaces of the first metal layer 18 to prevent diffusion of impurities into the first interlayer insulating film 17 and the second interlayer insulating film 19, respectively. Similarly, an upper barrier film 22 and a lower barrier film 23 that prevent diffusion of impurities into the second interlayer insulating film 19 and the third interlayer insulating film 21 are formed on the upper and lower surfaces of the second metal layer 20, respectively. . Upper surface barrier film 22 formed on each upper surface of first metal layer 18 and second metal layer 20 may include, for example, titanium nitride. On the other hand, the lower surface barrier film 23 formed on each lower surface of the first metal layer 18 and the second metal layer 20 is formed by stacking titanium nitride and titanium sequentially from the lower surfaces of the first metal layer 18 and the second metal layer 20, for example. It may have a two-layer structure.

  The passivation film 14 is formed on the multilayer wiring structure 13 so as to cover the multilayer wiring structure 13. More specifically, the passivation film 14 is formed on the third interlayer insulating film 21. The passivation film 14 may be, for example, silicon oxide, BPSG (Boron Phosphorus Silicon Glass), or silicon nitride. The passivation film 14 may have a stacked structure in which silicon nitride and silicon oxide are stacked in order from the surface of the third interlayer insulating film 21.

  A first via 24 a penetrating through the second interlayer insulating film 19 is connected to the upper surface of the first metal layer 18. The first via 24 a passes through the second interlayer insulating film 19 and is connected to the lower surface of the second metal layer 20. The first via 24a includes tungsten. A first barrier film 25a containing, for example, titanium nitride is interposed between the first via 24a and the second interlayer insulating film 19.

  On the other hand, a second via 24 b penetrating the third interlayer insulating film 21 and the passivation film 14 is connected to the upper surface of the second metal layer 20. The second via 24 b is exposed from the surface of the passivation film 14. The second via 24 b is formed flush with the surface of the passivation film 14. The second via 24b includes tungsten. Between each of the second via 24b and the third interlayer insulating film 21 and the passivation film 14, a second barrier film 25b containing, for example, titanium nitride is interposed.

  With reference to the enlarged view of FIG. 2 and FIG. 4, a plurality of wirings 15 are formed on the passivation film 14 at intervals. Each wiring 15 is disposed so as to cover the second via 24 b exposed from the surface of the passivation film 14. Each wiring 15 integrally has a connection part 40 electrically connected to the bonding wire 5 and a lead part 41 selectively drawn from the connection part 40. In the present embodiment, the connection portion 40 is formed in a substantially rectangular shape in plan view as a part of the pad 7 (see FIG. 3). In each wiring 15, the lead portions 41 adjacent to each other may be formed so as to run in parallel with each other at a predetermined interval.

Each wiring 15 has an edge portion 42 and an inner portion 43 located on the inner side of the edge portion 42. In the enlarged view of FIG. 2, the boundary between the edge portion 42 and the inward portion 43 is indicated by a broken line. The inner portion 43 of each wiring 15 has a flat upper surface 27 along the surface of the passivation film 14. This upper surface 27 is also the upper surface 27 of each wiring 15. The width W of the inner portion 43 of each wiring 15 is, for example, 7 μm or more and 20 μm or less. Further, the thickness T of the inner portion 43 is, for example, not less than 7 μm and not more than 20 μm. In these numerical ranges, the aspect ratio R ₄₃ (= thickness T / width W) of the inner portion 43 of each wiring 15 may be 0 <R ₄₃ ≦ 1. Edge 42 wiring 15 overall aspect ratio _{R 15,} including the 0 _{<R 15} <1, less than the aspect ratio _{R 43.}

  A thin film portion 44 having a smaller thickness than the inner portion 43 is formed at the edge portion 42 of each wiring 15. The thin film portion 44 of the wiring 15 is preferably formed in a portion of the edge portion 42 where at least the plurality of wirings 15 face each other between the plurality of adjacent wirings 15. More specifically, the thin film portion 44 of the wiring 15 is formed between the plurality of adjacent wirings 15 at a portion where at least the plurality of wirings 15 of the edge portion 42 face each other with an inter-wiring distance L of 20 μm or less. It is preferable. In the present embodiment, the thin film portion 44 is formed on the entire edge portion 42 of each wiring 15.

  With reference to FIG. 4, in this embodiment, the thin film portion 44 of each wiring 15 includes an inclined portion 45 whose thickness gradually decreases in a direction away from the inner portion 43. Each wiring 15 has a tapered (tapered, substantially trapezoidal) cross-sectional shape that becomes narrower toward the direction away from the semiconductor substrate 12 at a cut surface that intersects the direction in which the wiring 15 extends. In this embodiment, the inclined portion 45 has a surface that curves in a concave shape toward the inner portion 43 side. The surface of the inclined portion 45 is the side surface 28 of the wiring 15, and the end portion 46 of the inclined portion 45 is the end portion 46 of the wiring 15. The end portion 46 of the wiring 15 is formed extremely thin as compared with other portions.

The wiring 15 may contain a metal whose main component is copper. The metal having copper as a main component means a metal having the highest mass ratio (mass%) of copper with respect to other components (hereinafter the same). For example, when the wiring 15 is made of an aluminum-copper (Al—Cu) alloy, an aluminum-silicon-copper (Al—Si—Cu) alloy, or the like, the copper mass ratio R _Cu is equal to the aluminum mass ratio R _Al or silicon. The mass ratio is higher than R _Si (R _Cu > R _Al, R _Cu > R _Si ). Although the metal which has copper as a main component may contain a trace amount of impurities, high purity copper with a purity of 99.9999% (6N) or higher, high purity copper with a purity of 99.99% (4N) or higher, etc. included. When the wiring 15 includes a metal mainly composed of copper, the passivation film 14 preferably includes one or more insulating materials selected from the group including silicon oxide, BPSG, and silicon nitride.

On the other hand, the wiring 15 may contain a metal whose main component is aluminum. The metal having aluminum as a main component means a metal having the highest aluminum mass ratio (mass%) relative to other components (hereinafter the same). For example, when the wiring 15 is made of an aluminum-copper (Al-Cu) alloy, an aluminum-silicon (Al-Si) alloy, an aluminum-silicon-copper (Al-Si-Cu) alloy, the mass ratio R _Al of _aluminum is , Higher than the mass ratio R _{Cu of copper} and the mass ratio R _{Si of} silicon (R _Al > R _Cu, R _Al > R _Si ). The metal mainly composed of aluminum may contain a small amount of impurities, but high purity aluminum having a purity of 99.9999% (6N) or higher, high purity aluminum having a purity of 99.99% (4N) or higher, etc. included. When the wiring 15 contains a metal whose main component is aluminum, the passivation film 14 preferably contains an oxide film such as SiO ₂ or BPSG. The passivation film 14 preferably contains at least one of silicon oxide and BPSG.

  A barrier metal film 26 and a copper seed film (not shown) are arranged between each wiring 15 and the passivation film 14. That is, each wiring 15 is electrically connected to the second via 24 b through the copper seed film (not shown) and the barrier metal film 26. The barrier metal film 26 is formed on the passivation film 14, and a copper seed film (not shown) is formed on the barrier metal film 26. In the present embodiment, a copper seed film (not shown) is integrated with each wiring 15. The barrier metal film 26 is formed so that both end portions thereof are located inside the end portion 46 of the wiring 15 in a sectional view.

  The end portion of the barrier metal film 26 is located, for example, in a region between the end portion 46 of the wiring 15 and the inner portion 43 of the wiring 15 in plan view. The width of the barrier metal film 26 is, for example, larger than the width W of the inner portion 43 of the wiring 15 and smaller than the width of the entire wiring 15 including the edge 42. The barrier metal film 26 has a thickness smaller than the thickness of the wiring 15. The thickness of the barrier metal film 26 may be, for example, not less than 0.1 μm and not more than 0.3 μm. The barrier metal film 26 may include a titanium film, or may include a stacked film of a titanium nitride film and a titanium film stacked in order from the surface of the passivation film 14.

  In addition to or instead of the titanium film, the barrier metal film 26 may include a metal film made of a metal material having a rigidity higher than that of copper or a coefficient of thermal expansion lower than that of copper. The metal film includes one or more metal species selected from the group including, for example, tantalum, tungsten, molybdenum, chromium, and ruthenium. All of these metal species have a higher rigidity than copper and a lower coefficient of thermal expansion than copper. Furthermore, these metal species have an electrical resistivity smaller than that of titanium.

  When it has a laminated structure of a titanium film and a metal film, the metal film may be formed on the titanium film. In this case, the thickness of the titanium film may be, for example, 0.1 μm or more and 0.3 μm or less, and the thickness of the metal film may be, for example, 0.1 μm or more and 0.3 μm or less. In this configuration, the passivation film 14 may be a nitride film, and the metal film may be a tungsten film. If the passivation film 14 is a nitride film, a titanium film can be formed on the passivation film 14 while maintaining good adhesion. In addition, a tungsten film can be formed on the titanium film while maintaining good adhesion.

  A laminated film of a Ni (nickel) film 29, a Pd (palladium) film 30 and an Au (gold) film 31 is formed on the surface of each wiring 15. The Ni film 29 is formed along the upper surface 27 and the side surface 28 of each wiring 15 so that one surface and the other surface of the Ni film 29 cover each wiring 15. In the present embodiment, a portion of the Ni film 29 formed on the upper surface 27 of each wiring 15 is formed thicker than the other portions. The Ni film 29 may have a uniform thickness. The thickness of the Ni film 29 may be, for example, 2 μm or more and 4 μm or less.

  The Pd film 30 covers the entire area of the Ni film 29 with a uniform thickness (for example, 0.1 μm or more and 0.5 μm or less). The Au film 31 covers the entire area of the Pd film 30 with a uniform thickness (for example, 0 μm to 0.05 μm) thinner than that of the Pd film 30, for example. The laminated film of the Ni film 29, the Pd film 30, and the Au film 31 functions as a protective film that protects the wiring 15. The bonding wire 5 is connected to the Au film 31. That is, in this embodiment, the pad 7 is formed by the connection portion 40 of each wiring 15, the Ni film 29, the Pd film 30, and the Au film 31.

5A to 5H are diagrams for explaining a part of the manufacturing process of the wiring 15 of FIG. In the following description, FIG. 4 is referred to as necessary. Hereinafter, a case where the wiring 15 is made of high-purity copper will be described as an example.
First, prior to the formation of the wiring 15, the multilayer wiring structure 13 (see FIG. 4) is formed on the semiconductor substrate 12. Next, a passivation film 14 is formed on the multilayer wiring structure 13. Next, the second via 24b (see FIG. 4) penetrating the passivation film 14 is formed.

  Next, as shown in FIG. 5A, a barrier metal film 26 and a copper seed film 32 are formed in this order on the surface of the passivation film 14 by, eg, sputtering. Next, as shown in FIG. 5B, a cover film 33 is formed on the copper seed film 32. The cover film 33 is a photosensitive resin such as a polyimide resin. Next, the cover film 33 is selectively exposed and developed, and as shown in FIG. 5C, openings 34 are selectively formed in the cover film 33 in regions where the wirings 15 are to be formed.

  When the cover film 33 is exposed, the photoreaction rate of the cover film 33 decreases as the distance from the light source increases. Therefore, in the cover film 33, the part that reacts gradually spreads as the copper seed film 32 is approached. As a result, an opening 34 having a reverse taper shape in cross section is formed by exposure and development. That is, the cover film 33 is formed (exposure / development) so as to have an inclined surface 33 a that partitions the opening 34 so that the opening width of the opening 34 gradually increases along the direction toward the passivation film 14. In this step, the inclined surface 33 a is formed in a curved shape that curves convexly toward the opening 34.

  Next, as shown in FIG. 5D, copper is grown by electrolytic plating from the surface of the copper seed film 32 exposed from the opening 34. Copper is grown (buried) to the middle of the opening 34. In this step, the plated copper is integrated with the copper seed film 32. As a result, the wiring 15 including the inner portion 43 exposed from the opening 34 and the inclined portion 45 having the concavely curved surface (side surface 28) that matches the inclined surface 33 a of the cover film 33 is formed.

  Next, as shown in FIG. 5E, Ni is grown from the upper surface 27 of the wiring 15 by electroless plating using the opening 34 of the cover film 33. Thereby, a part of the Ni film 29 is formed. Next, as shown in FIG. 5F, the cover film 33 is removed. Next, as shown in FIG. 5G, the copper seed film 32 and the barrier metal film 26 are selectively removed by wet etching, for example.

  In this step, the end portion of the barrier metal film 26 is etched (over-etched) inside the end portion 46 of the wiring 15, and the end portion of the barrier metal film 26 is positioned inside the end portion 46 of the wiring 15. To be formed. As a result, a step is formed between the end of the barrier metal film 26 and the end 46 of the wiring 15. Further, in this step, a part of the side surface 28 of the wiring 15 is etched together with the copper seed film 32 so that the side surface 28 of the wiring 15 is located inside the end portion of the Ni film 29.

  Next, as shown in FIG. 5H, Ni, Pd, and Au are plated and grown in this order from the side surface 28 of the wiring 15 and the Ni film 29 by electroless plating. Thereby, a laminated film of the Ni film 29, the Pd film 30, and the Au film 31 is formed. Thereafter, the temperature of the semiconductor substrate 12 is set to 200 ° C. or higher (for example, 260 ° C.), and the bonding wire 5 is connected to the wiring 15 (Au film 31) (see also FIG. 4).

  Here, as a reference example, a semiconductor device in which the wiring 15 having a uniform thickness without the thin film portion 44 is formed on the passivation film 14 is considered. In this semiconductor device, when the semiconductor substrate 12 or the like is heated, the wiring 15 and the passivation film 14 are expanded by the applied heat. The wiring 15 has a higher coefficient of thermal expansion than that of the passivation film 14, and generates stress in a direction along the surface of the passivation film 14 by thermal expansion. This stress may cause a crack (crack) to be formed in the passivation film 14.

  Cracks in the passivation film 14 tend to occur around the edge of the wiring 15 where stress from the wiring 15 is concentrated. In addition, since the stress due to thermal expansion increases as the thickness of the wiring 15 increases, the risk of occurrence of cracks increases. Such a crack may be avoided by making the wiring 15 thin, but in this case, there is a tradeoff in that the resistance value of the wiring 15 increases.

  Further, when the plurality of wirings 15 are formed on the passivation film 14 with a space between each other, the passivation film 14 positioned between the plurality of adjacent wirings 15 receives stress from both of the wirings. Therefore, the risk of occurrence of cracks in the passivation film 14 located between the plurality of wirings 15 is higher than that of other portions. Furthermore, when the wiring 15 is formed as the uppermost layer wiring and the side surface 28 is not supported by a protective film or the like, cracks of the passivation film 14 due to thermal expansion of the wiring 15 are particularly likely to occur.

  On the other hand, in the present embodiment, the edge portion 42 of the wiring 15 located in a portion where the crack of the passivation film 14 is likely to include the thin film portion 44. More specifically, the thin film portion 44 includes an inclined portion 45 having a surface (side surface 28) that curves in a concave shape toward the inner portion 43 side of the wiring 15. The end portion 46 of the inclined portion 45 (that is, the end portion 46 of the wiring 15) is formed to be extremely small compared to other portions. As a result, the stress caused by thermal expansion at the edge 42 of the wiring 15 can be reduced and the stress in the direction along the surface of the passivation film 14 can be reduced, so that cracks are generated in the passivation film 14 around the edge 42 of the wiring 15. It can be suppressed from occurring. In particular, in this embodiment, since the inclined portion 45 (thin film portion 44) is formed in the entire wiring 15, the stress in the direction along the surface of the passivation film 14 can be effectively reduced in the entire wiring 15. Thereby, it can suppress effectively that a crack arises in the wide range of the passivation film 14. FIG. Moreover, since generation | occurrence | production of a crack can be suppressed by the thin film part 44, since the inner part 43 can be thickened, the high resistance of the wiring 15 can be suppressed.

  For example, an inclined portion 45 (thin film portion 44) may be formed in a portion of the edge portion 42 where at least the plurality of wirings 15 face each other between the plurality of adjacent wirings 15. As a result, the risk of cracks occurring in the passivation film 14 between the plurality of adjacent wirings 15 can be reduced. In particular, if the configuration in which the thin film portion 44 is disposed on the edge 42 of the wiring 15 is limited to a portion where the inter-wiring distance L is short (for example, a portion where the inter-wiring distance L is 20 μm or less), wiring in other portions Since the cross-sectional area of 15 can be increased, an increase in resistance of the wiring 15 can be suppressed.

  In the present embodiment, the wiring 15 includes a metal containing copper as a main component or a metal containing aluminum as a main component. Although there is a difference in coefficient of thermal expansion between the metal mainly composed of copper or the metal mainly composed of aluminum and the passivation film 14, cracks can be suppressed by the inclined portion 45 (thin film portion 44) of the wiring 15. Therefore, the wiring 15 can be satisfactorily formed on the passivation film 14. In particular, if the metal is mainly composed of copper, the resistance of the wiring 15 can be reduced.

  In the present embodiment, when the bonding wire 5 is connected to the wiring 15, the semiconductor substrate 12 and the like are heated to a temperature of 200 ° C. or higher (for example, about 260 ° C.). The applied heat is transmitted to the wiring 15 directly or via the semiconductor substrate 12 or the like, and causes thermal expansion thereof. At this time, the thin film portion 44 of the wiring 15 relieves stress concentration at the edge 42 of the wiring 15, so that the generation of cracks in the passivation film 14 can be suppressed.

FIG. 6 is a cross-sectional view showing another embodiment of the wiring 15 of FIG. In FIG. 6, only the configuration of the wiring 15 and its periphery is shown. In FIG. 6, parts corresponding to those shown in FIG. 4 and the like described above are denoted by the same reference numerals and description thereof is omitted.
The wiring 15 is formed on the passivation film 14 as in the above-described embodiment. The wiring 15 has an edge portion 42 and an inner portion 43 located on the inner side of the edge portion 42. The edge portion 42 of the wiring 15 includes a thin film portion 44 having a thickness smaller than that of the inner portion 43.

  More specifically, the wiring 15 includes a first conductor layer 51 formed on the passivation film 14 (barrier metal film 26), and a second conductor layer 52 formed on the first conductor layer 51. including. The inner portion 43 of the wiring 15 is formed by a laminated structure of the first conductor layer 51 and the second conductor layer 52. The inner portion 43 of the wiring 15 has a thickness corresponding to the total thickness T of the first conductor layer 51 and the second conductor layer 52.

  The first conductor layer 51 is formed with a larger area than the second conductor layer 52 in plan view, and is formed with a thickness smaller than that of the second conductor layer 52. The first conductor layer 51 has a protruding portion 53 that protrudes from the periphery of the second conductor layer 52. A thin film portion 44 of the wiring 15 is formed by the protruding portion 53. Note that the upper surface of the protruding portion 53 may be formed so as to be located below (on the passivation film 14 side) the connecting portion (boundary portion) between the first conductor layer 51 and the second conductor layer 52. .

  The first conductor layer 51 may include a metal containing copper as a main component or a metal containing aluminum as a main component. The second conductor layer 52 may include a metal containing copper as a main component or a metal containing aluminum as a main component. The first conductor layer 51 and the second conductor layer 52 may be formed integrally by being formed of the same metal, or may be formed of metals different from each other. When the first conductor layer 51 includes a metal whose main component is copper, the passivation film 14 preferably includes one or more insulating materials selected from the group including silicon oxide, BPSG, and silicon nitride. . On the other hand, when the 1st conductor layer 51 contains the metal which has aluminum as a main component, it is preferable that the passivation film 14 contains at least one of silicon oxide and BPSG.

  In this embodiment, the barrier metal film 26 is formed so that both end portions thereof are located inside the end portions of the first conductor layer 51 in a cross-sectional view. The end of the barrier metal film 26 is located, for example, in a region between the end of the first conductor layer 51 and the end of the second conductor layer 52 in plan view. The width of the barrier metal film 26 is, for example, smaller than the width of the first conductor layer 51 and larger than the width of the second conductor layer 52. The barrier metal film 26 has a thickness (for example, 0.1 μm or more and 0.3 μm or less) smaller than the thickness of the first conductor layer 51.

The laminated film of the Ni film 29, the Pd film 30, and the Au film 31 covers the surfaces of the first conductor layer 51 and the second conductor layer 52 so that the first conductor layer 51 and the second conductor layer 52 are covered. It is formed along. In the present embodiment, the Ni film 29 covers the entire region of the protruding portion 53 of the first conductor layer 51.
7A to 7I are diagrams for explaining a part of the manufacturing process of the wiring 15 of FIG. Hereinafter, description will be made with reference to FIG. 4 and FIGS. 5A to 5G as appropriate.

First, prior to the formation of the wiring 15, the multilayer wiring structure 13 (see FIG. 4) is formed on the semiconductor substrate 12. Next, a passivation film 14 is formed on the multilayer wiring structure 13. Next, the second via 24b (see FIG. 4) penetrating the passivation film 14 is formed.
Next, as shown in FIG. 7A, a barrier metal film 26 and a copper seed film 32 are formed in this order on the surface of the passivation film 14 through the same steps as in FIG. 5A described above. Next, as shown in FIG. 7B, a first cover film 54 having an opening 54 a that selectively exposes the copper seed film 32 is formed on the copper seed film 32. The first cover film 54 may be an insulating film or a resin film, for example. FIG. 7B shows an example in which a first cover film 54 made of a resin film is formed.

  Next, as shown in FIG. 7C, copper is plated and grown by electrolytic plating from the surface of the copper seed film 32 exposed from the opening 54a. Copper is grown (embedded) from the copper seed film 32 to the middle of the opening 54a. In this step, the plated copper is integrated with the copper seed film 32. Thereby, the first conductor layer 51 is formed. Thereafter, the first cover film 54 is removed.

  Next, as shown in FIG. 7D, a second cover film 55 having an opening 55 a that selectively exposes the first conductor layer 51 is formed on the copper seed film 32. Second cover film 55 may be, for example, an insulating film or a resin film. FIG. 7D shows an example in which the second cover film 55 made of a resin film is formed. Next, as shown in FIG. 7E, copper is grown by electrolytic plating from the surface of the first conductor layer 51 exposed from the opening 55a. Copper is grown (embedded) from the first conductor layer 51 to the middle of the opening 55a. As a result, the second conductor layer 52 is formed on the first conductor layer 51 and becomes the wiring 15.

Next, as shown in FIG. 7F, a part of the Ni film 29 is formed on the upper surface 27 of the wiring 15 through the same process as in FIG. 5E described above. Next, as shown in FIG. 7G, the second cover film 55 is removed. Next, as shown in FIG. 7H, the copper seed film 32 and the barrier metal film 26 are selectively removed by wet etching, for example.
In this step, the end of the barrier metal film 26 is etched (over-etched) inside the end of the first conductor layer 51, and the end of the barrier metal film 26 is the end of the first conductor layer 51. It forms so that it may be located inside a part. Thereby, a step is formed between the end of the barrier metal film 26 and the end of the first conductor layer 51. In this step, a part of the surface (including the upper surface and the side surface) of the protruding portion 53 of the first conductor layer 51 and a part of the side surface of the second conductor layer 52 are etched together with the copper seed film 32. The side surface of the second conductor layer 52 is formed so as to be located inside the end portion of the Ni film 29. The upper surface of the protruding portion 53 is formed by etching so as to be located below (passivation film 14 side) below the connection portion (boundary portion) between the first conductor layer 51 and the second conductor layer 52. Also good.

Next, as shown in FIG. 7I, a laminated film of the Ni film 29, the Pd film 30, and the Au film 31 is formed through the same process as in FIG. 5H described above. Thereafter, the temperature of the semiconductor substrate 12 is set to 200 ° C. or higher (for example, 260 ° C.), and the bonding wire 5 is connected to the wiring 15 (Au film 31) (see also FIG. 4).
As described above, according to this embodiment, the wiring 15 includes the first conductor layer 51 formed on the passivation film 14 and the second conductor layer 52 formed on the first conductor layer 51. The first conductor layer 51 has a protruding portion 53 that protrudes from the periphery of the second conductor layer 52. A thin film portion 44 of the wiring 15 is formed by the protruding portion 53. The protruding portion 53 of the first conductor layer 51 has a smaller thickness than the inner portion 43 of the wiring 15. Thereby, the stress in the direction along the surface of the passivation film 14 can be effectively reduced. As a result, the generation of cracks in the passivation film 14 can be effectively suppressed.
Second Embodiment
FIG. 8 is an enlarged cross-sectional view showing a portion where the wiring 15 of the semiconductor device 61 according to the second embodiment of the present invention is formed. FIG. 8 corresponds to an enlarged view of a portion surrounded by the broken line circle IV in FIG. In FIG. 8, parts corresponding to those shown in FIG. 4 and the like described above are denoted by the same reference numerals and description thereof is omitted.

  The semiconductor device 61 includes a first resin film 62 as an example of an on-wiring insulating film of the present invention formed on the passivation film 14 so as to cover the wiring 15 and a first resin film 62 so as to be electrically connected to the wiring 15. 1 and a rewiring 63 formed on the resin film 62. The first resin film 62 includes, for example, a polyimide resin. The first resin film 62 has a pad opening 65 that exposes a part of the wiring 15 as an electrode pad 64. On the first resin film 62, the rewiring 63 is routed.

  The rewiring 63 is formed so as to enter the pad opening 65 from the surface of the first resin film 62. The rewiring 63 is electrically connected to the electrode pad 64 in the pad opening 65. In this embodiment, the rewiring 63 has a two-layer structure including a UBM (under bump metal) film 66 and a wiring film 67 formed on the UBM film 66. The UBM film 66 has one surface and the other surface formed along the surface of the first resin film 62 and the surface of the electrode pad 64. The UBM film 66 may have a two-layer structure including a titanium film and a copper film formed on the titanium film. The wiring film 67 is formed along the UBM film 66 so that the UBM film 66 enters the concave space formed by entering the pad opening 65. The wiring film 67 may contain a metal whose main component is copper. A second resin film 68 is formed on the rewiring 63 so as to cover the rewiring 63.

  The second resin film 68 has a rewiring pad opening 70 that exposes a part of the rewiring 63 as a rewiring pad 69. An electrode post 71 is formed on the rewiring pad 69. The electrode post 71 corresponds to the pad 7 (see FIG. 2). The electrode post 71 is formed so as to enter the rewiring pad opening 70 from the surface of the second resin film 68. The electrode post 71 is electrically connected to the rewiring pad 69 in the rewiring pad opening 70. In the present embodiment, the electrode post 71 has a two-layer structure including a UBM film 72 and a wiring film 73 formed on the UBM film 72.

  The UBM film 72 has one surface and the other surface formed along the surface of the second resin film 68 and the surface of the rewiring pad 69. The UBM film 72 may have a two-layer structure including a titanium film and a copper film formed on the titanium film. The wiring film 73 is formed along the UBM film 72 so that the UBM film 72 enters a concave space formed by entering the pad opening 65. The wiring film 73 may contain a metal whose main component is copper. A bonding wire 5 is connected to the electrode post 71.

  As described above, according to the present embodiment, the bonding wire 5 is electrically connected to the rewiring 63 via the electrode post 71. For example, when the bonding wire 5 is connected to the electrode post 71, the semiconductor substrate 12 or the like may be heated to a temperature of 200 ° C. or higher (for example, about 260 ° C.). The applied heat is transmitted to the wiring 15 through the semiconductor substrate 12, the electrode post 71, the rewiring 63, and the like. At this time, the inclined portion 45 (thin film portion 44) of the wiring 15 relieves stress concentration at the edge 42 of the wiring 15, so that cracks in the passivation film 14 due to the stress from the wiring 15 can be suppressed (FIG. (See also 4). The wiring 15 may have the above-described protruding portion 53 instead of the inclined portion 45 (see FIG. 6).

In the present embodiment, by forming a thin film portion 44 similar to the thin film portion 44 (the inclined portion 45 or the protruding portion 53) of the wiring 15 in the rewiring 63, the occurrence of cracks in the first resin film 62 is suppressed. It may be. Further, by forming a thin film portion 44 similar to the thin film portion 44 (the inclined portion 45 or the protruding portion 53) of the wiring 15 on the electrode post 71, the occurrence of cracks in the second resin film 68 may be suppressed. Good.
<Third Embodiment>
FIG. 9 is a sectional view showing a semiconductor device 81 according to the third embodiment of the present invention. 9, parts corresponding to those shown in FIG. 2 and the like described above are denoted by the same reference numerals and description thereof is omitted.

  The semiconductor device 81 includes a connection electrode 82 connected to each of a plurality of pads 7 (wiring 15) formed on the surface of the semiconductor chip 2, and the semiconductor chip 2 (semiconductor substrate 12) is flip-chip bonded via the connection electrode 82. And a wiring board 83 having a bonded surface 83a. The connection electrode 82 may be a block-like or columnar conductor, or may be solder. A plurality of lands 84 and solder balls 85 that are electrically connected to the lands 84 are formed on the back surface 83b of the wiring board 83 that is located on the opposite side of the bonding surface 83a. Each land 84 and each solder ball 85 is electrically connected to the corresponding connection electrode 82 and pad 7 (wiring 15) via a via electrode 86 formed on the wiring board 83. A sealing resin 88 is formed in the gap 87 between the semiconductor chip 2 and the wiring board 83 so as to fill the gap 87.

  As described above, according to the present embodiment, the semiconductor chip 2 is connected to the wiring substrate 83 via the connection electrode 82. For example, when connecting the connection electrode 82 to the wiring substrate 83, the semiconductor chip 2 (semiconductor substrate 12) or the like may be heated to a temperature of 200 ° C. or higher (for example, about 260 ° C.). The applied heat is transmitted to the wiring 15 through the semiconductor substrate 12, the connection electrode 82, and the like. At this time, since the stress concentration at the edge 42 of the wiring 15 is relieved by the thin film portion 44 (the inclined portion 45 or the protruding portion 53) of the wiring 15, cracks in the passivation film 14 can be suppressed (FIGS. 4, 6, etc.). See also).

Further, according to the present embodiment, the semiconductor device 81 is mounted on a mounting board (not shown) via the solder balls 85 that are in contact with the lands 84. During this mounting, the semiconductor device 81 is heated to melt the solder balls 85. Thereby, although the wiring 15 is also heated, the concentration of stress at the edge 42 of the wiring 15 is alleviated by the action of the thin film portion 44 (the inclined portion 45 or the protruding portion 53). Thereby, the crack of the passivation film 14 resulting from the heating at the time of mounting can be suppressed (refer also to FIG. 4, FIG. 6 etc.).
<Fourth embodiment>
FIG. 10 is a sectional view showing a semiconductor device 91 according to the fourth embodiment of the present invention. In FIG. 10, parts corresponding to those shown in FIG. 2 and the like described above are denoted by the same reference numerals and description thereof is omitted.

The semiconductor device 91 includes a connection electrode 92 connected to each of the plurality of pads 7 (wirings 15) formed on the surface of the semiconductor chip 2, and the semiconductor chip 2 (semiconductor substrate 12) so as to expose the connection electrode 92. Element forming surface 16, sealing resin 93 covering the back surface and the side surface. The sealing resin 93 also serves as the resin package 6.
As described above, according to the present embodiment, the connection electrode 92 is formed as an external terminal for achieving electrical connection with the outside. In this case, the semiconductor device 91 is mounted on a mounting substrate (not shown) via solder in contact with the connection electrode 92. At the time of mounting, the semiconductor device 91 is heated to melt the solder. Thereby, although the wiring 15 is also heated, the stress concentration at the edge of the wiring 15 is alleviated by the action of the thin film portion 44 (the inclined portion 45 or the protruding portion 53) of the wiring 15. Thereby, the crack of the passivation film 14 resulting from the heating at the time of mounting can be suppressed (refer also to FIG. 4, FIG. 6 etc.).

Further, a rewiring 63 as shown in FIG. 8 may be formed on the connection electrode 92, for example. In this case, the semiconductor device 91 is mounted on a mounting board (not shown) via solder in contact with the electrode pad 64 (see FIG. 8). During this mounting, the solder is melted by heating. The heat at the time of mounting is transmitted to the wiring 15 via the rewiring 63 etc., for example. Even in such a case, since the stress concentration at the edge 42 of the wiring 15 can be avoided by the thin film portion 44 (the inclined portion 45 or the protruding portion 53) of the wiring 15, cracks in the passivation film 14 caused by heating at the time of mounting. (See also FIG. 4, FIG. 6 and the like).
<Fifth Embodiment>
FIG. 11 is a sectional view showing a semiconductor device 101 according to the fifth embodiment of the present invention. In FIG. 11, parts corresponding to those shown in FIG. 2 and the like described above are denoted by the same reference numerals and description thereof is omitted.

  As shown in FIG. 11, the semiconductor device 101 is a semiconductor device to which an SOP (Small Outline Package) having leads 4 drawn out of the resin package 6 (sealing resin) is applied. Similar to the semiconductor device 1 described above, the semiconductor chip 2 is disposed on the die pad 3. Although the lower surface of the die pad 3 is not exposed from the resin package 6 in the present embodiment, the lower surface of the die pad 3 may be formed so as to be exposed from the resin package 6.

  The lead 4 includes an inner lead portion 4 a sealed in the resin package 6 and an outer lead portion 4 b formed integrally with the inner lead portion 4 a and drawn out of the resin package 6. The inner lead portion 4 a is electrically connected to the pad 7 (wiring 15) of the corresponding semiconductor chip 2 through the bonding wire 5 in the resin package 6. The outer lead portion 4 b is formed so as to extend toward the lower surface of the resin package 6. The outer lead portion 4b is a mounting terminal connected to the mounting substrate.

As described above, the configuration of the present embodiment can provide the same effects as those described in the first embodiment. In the present embodiment, the semiconductor device 101 to which SOP is applied has been described. However, the semiconductor device 101 may be of a type other than the SOP as long as it has the leads 4 drawn out of the resin package 6 (sealing resin). In other words, the semiconductor device 101 includes an SOJ (Small Outline J-leaded), a CFP (Ceramic Flat Package), an SOT (Small Outline Transistor), a QFP (Quad Flat Package), a DFP (Dual Flat Package), and a PLCC (Plastic leaded chip). A type such as carrier), DIP (Dual Inline Package), or SIP (Single Inline Package) may be applied.
<Sixth Embodiment>
FIG. 12 is an enlarged cross-sectional view showing a portion where the wiring 15 of the semiconductor device 111 according to the sixth embodiment of the present invention is formed. FIG. 12 corresponds to an enlarged view of the portion surrounded by the broken line circle IV in FIGS. 3, 9, 10 and 11 described above. In FIG. 12, parts corresponding to those shown in FIG. 4 and the like described above are denoted by the same reference numerals and description thereof is omitted.

  As shown in FIG. 12, in this embodiment, a metal film 112 is formed on the wiring 15. The metal film 112 is formed on the upper surface 27 (inner portion 43) of the wiring 15 so that both ends thereof are located outside the inner portion 43 of the wiring 15 in a cross-sectional view. The width of the metal film 112 is larger than the width W of the inner portion 43 of the wiring 15. That is, the width W of the inner portion 43 of the wiring 15 is smaller than the width of the metal film 112. The end portion of the metal film 112 is located, for example, in a region between the end portion 46 of the wiring 15 and the inner portion 43 of the wiring 15 in plan view.

  Both end portions of the metal film 112 have portions facing the side surfaces 28 (edge portions 42) of the wiring 15 with a space therebetween. Note that both end portions of the metal film 112 may include a portion located outside the end portion 46 of the wiring 15, and the portion may face the passivation film 14. More specifically, the metal film 112 includes a laminated film composed of a plurality of metal films. In the present embodiment, the metal film 112 includes a laminated film of a Ni (nickel) film 113 and a Pd (palladium) film 114.

  The Ni film 113 of the metal film 112 has a flat surface, and is formed on the wiring 15 so that both end portions are located outside the inner portion 43 of the wiring 15 in a sectional view. Thereby, the Ni film 113 has a portion facing the side surface 28 (edge portion 42) of the wiring 15 with the space interposed therebetween. The Ni film 113 has a thickness smaller than the thickness of the wiring 15. The Ni film 113 may be formed with a uniform thickness. The thickness of the Ni film 113 may be, for example, 2 μm or more and 4 μm or less.

  On the other hand, the Pd film 114 of the metal film 112 has a flat surface and is formed on the Ni film 113 so that both end portions are located outside the inner portion 43 of the wiring 15 in a sectional view. . The Pd film 114 is formed on the Ni film 113 so as to match the Ni film 113. That is, the end of the Pd film 114 is formed so as to be flush with the end of the Ni film 113. The Pd film 114 has a thickness smaller than the thickness of the Ni film 113. The Pd film 114 may be formed with a uniform thickness. The thickness of the Pd film 114 may be, for example, not less than 0.1 μm and not more than 0.5 μm.

The bonding wire 5 is connected to the metal film 112 (Pd film 114). That is, in the present embodiment, the pad 7 is formed by the connection portion 40 of each wiring 15 and the metal film 112 (Ni film 113 and Pd film 114).
As described above, the configuration of the present embodiment can provide the same effects as those described in the first embodiment.

13A to 13G are diagrams for explaining a part of the manufacturing process of the wiring 15 of FIG. In the following description, the above-described FIGS. 5A to 5D are referred to as necessary. Hereinafter, a case where the wiring 15 is made of high-purity copper will be described as an example.
First, as shown in FIG. 13A, a barrier metal film 26 and a copper seed film 32 are formed in this order on the surface of the passivation film 14 through a process similar to the process shown in FIG. 5A. Next, as shown in FIGS. 13B and 13C, the cover film 33 having the inclined surface 33a that defines the opening 34 is formed through the same process as the process shown in FIGS. 5B and 5C described above.

Next, as shown in FIG. 13D, the inclined portion having the inner portion 43 exposed from the opening 34 and the surface (side surface 28) aligned with the inclined surface 33 a of the cover film 33 through the process shown in FIG. 5D described above. 45 is formed.
Next, as shown in FIG. 13E, Ni is grown from the upper surface 27 of the wiring 15 by electrolytic plating using the opening 34 of the cover film 33. Thereby, the Ni film 113 is formed. Next, Pd is grown from the Ni film 113 by electrolytic plating using the opening 34 of the cover film 33. In this step, a Pd film having a thickness smaller than that of the Ni film 113 is formed. Thereby, the metal film 112 including the Ni film 113 and the Pd film 114 is formed. Thereafter, as shown in FIG. 13F, the cover film 33 is removed.

  Next, as shown in FIG. 13G, the copper seed film 32 and the barrier metal film 26 are selectively removed by wet etching, for example. In this step, the side surface 28 of the wiring 15 is etched together with the copper seed film 32 so that the inner portion 43 of the wiring 15 is located inside the end portion of the metal film 112. Thereby, a step is formed between the inner portion 43 of the wiring 15 and the end portion of the metal film 112. In this step, the end of the barrier metal film 26 is etched (over-etched) inside the end 46 of the wiring 15, and the end of the barrier metal film 26 is inside the end 46 of the wiring 15. It is formed so that it may be located in. As a result, a step is formed between the end of the barrier metal film 26 and the end 46 of the wiring 15.

Thereafter, the temperature of the semiconductor substrate 12 is set to 200 ° C. or higher (for example, 260 ° C.), and the bonding wire 5 (see FIG. 12) is connected to the Pd film 114.
As mentioned above, although embodiment of this invention was described, this invention can also be implemented with another form.
For example, in the first embodiment described above, the example in which the laminated film of the Ni film 29, the Pd film 30, and the Au film 31 that covers the wiring 15 is formed has been described. However, as shown in FIG. 14, the bonding wire 5 may be directly connected to the wiring 15 without forming the laminated film of the Ni film 29, the Pd film 30 and the Au film 31.

  In the first embodiment, the example in which the copper seed film 32 and the barrier metal film 26 are formed on the passivation film 14 has been described. However, as shown in FIG. 15, the wiring 15 may be disposed directly on the passivation film 14 without providing the copper seed film 32 and the barrier metal film 26. Such wiring 15 can be formed by performing electroless plating instead of electrolytic plating and directly growing copper on the passivation film 14.

  In the example of the wiring 15 according to the first embodiment described above, the example in which the wiring 15 includes the inclined portion 45 having a surface curved toward the inner portion 43 has been described. However, the inclined portion 45 may have a surface that curves toward the opposite side to the inner portion 43. In this case, since the end portion 46 of the wiring 15 is formed thicker than the case where the end portion 46 is curved toward the inner portion 43, the inclined portion 45 has a surface on which the wiring 15 is curved toward the inner portion 43. It can be said that it is desirable.

  Further, in another example of the wiring 15 according to the first embodiment described above, the example in which the wiring 15 includes the first conductor layer 51 and the second conductor layer 52 has been described. However, the wiring 15 may have a structure in which two or more conductor layers are stacked. In this case, as shown in FIG. 16, a third conductor layer 56 may be formed between the first conductor layer 51 and the second conductor layer 52. The third conductor layer 56 has a thickness larger than the thickness of the first conductor layer 51 and smaller than the thickness of the second conductor layer 52. The third conductor layer 56 has an area smaller than the area of the first conductor layer 51 and larger than the area of the second conductor layer 52 in plan view. As described above, the stepped wiring 15 may be formed by the first conductor layer 51, the third conductor layer 56, and the second conductor layer 52.

Further, in another example of the wiring 15 according to the first embodiment described above, as shown in FIG. 17, the metal film 112 according to the sixth embodiment described above may be employed. Such a metal film 112 can be formed by executing the same process as the process after FIG. 13E described above instead of the process after FIG. 5E described above.
In the sixth embodiment, the example in which the metal film 112 including the stacked film of the Ni film 113 and the Pd film 114 is formed has been described. In this configuration, the metal film 112 may include an Au (gold) film formed on the Pd film 114. Furthermore, the metal film 112 may be a metal film including one or more metal species selected from the group including Ni, Pd, and Au.

  In the first embodiment, the second embodiment, the fifth embodiment, and the sixth embodiment, the example in which the semiconductor devices 1, 61, 101, and 111 include the bonding wires 5 has been described. However, the semiconductor devices 1, 61, 101, and 111 may include a wiring member having a relatively large current passage area such as a conductor plate instead of or in addition to the bonding wire 5.

  In addition, various design changes can be made within the scope of matters described in the claims.

DESCRIPTION OF SYMBOLS 1 Semiconductor device 5 Bonding wire 12 Semiconductor substrate 13 Multilayer wiring structure 14 Passivation film 15 Wiring 26 Barrier film 33 Cover film 33a Inclined surface 34 Cover film opening 42 Edge 43 Inner part 44 Thin film part 45 Inclined part 51 First conductor Layer 52 second conductor layer 53 protruding portion 54 first cover film 54a first cover film opening 55 second cover film 55a second cover film opening 61 semiconductor device 62 first resin film 63 rewiring 81 semiconductor device 82 connection Electrode 83 Wiring board 83a Bonding surface 83b Back surface 84 Land 86 Via electrode 88 Sealing resin 91 Semiconductor device 92 Connection electrode 93 Sealing resin 101 Semiconductor device 111 Semiconductor device L Distance between wirings

Claims (24)

A semiconductor substrate;
An insulating film formed on the semiconductor substrate;
A wiring formed on the insulating film and having an edge portion and an inner portion located on an inner side of the edge portion;
The edge of the wiring includes a thin film portion having a thickness smaller than that of the inner portion.   The semiconductor device according to claim 1, wherein the thin film portion includes an inclined portion whose thickness gradually decreases in a direction away from the inward portion.   The semiconductor device according to claim 2, wherein the inclined portion has a surface that curves toward the inner portion of the wiring. The wiring includes a first conductor layer formed on the insulating film, and a second conductor layer formed on the first conductor layer,
The first conductor layer has a protruding portion that protrudes from the periphery of the second conductor layer,
The semiconductor device according to claim 1, wherein the thin film portion is formed by the protruding portion.   The semiconductor device according to claim 1, wherein the thin film portion is formed over the entire edge portion of the wiring. A plurality of the wirings formed on the insulating film and spaced apart from each other;
5. The semiconductor according to claim 1, wherein the thin film portion is formed in a portion where at least a plurality of the wirings are opposed to each other among the plurality of the wirings adjacent to each other. apparatus. A plurality of the wirings formed on the insulating film and spaced apart from each other;
5. The thin film portion according to claim 1, wherein the thin film portion is formed at a portion where at least a plurality of the wirings are opposed to each other at a distance between wirings of 20 μm or less among the plurality of wirings adjacent to each other. The semiconductor device according to claim 1. The wiring includes a metal mainly composed of copper,
The semiconductor device according to claim 1, wherein the insulating film includes a nitride film or an oxide film. The wiring includes a metal mainly composed of aluminum,
The semiconductor device according to claim 1, wherein the insulating film includes an oxide film.   The semiconductor device according to claim 1, further comprising a barrier film interposed between the wiring and the insulating film.   The semiconductor device according to claim 1, wherein the inner portion of the wiring has a thickness of 20 μm or less. A multilayer wiring structure formed on the semiconductor substrate, wherein a plurality of wiring layers are stacked via an interlayer insulating film;
The insulating film is formed on the multilayer wiring structure so as to cover the multilayer wiring structure;
The semiconductor device according to claim 1, wherein the wiring is formed on the insulating film as an uppermost layer wiring.   The semiconductor device according to claim 1, further comprising a bonding wire electrically connected to the wiring.   The semiconductor device according to claim 13, wherein the bonding wire includes a copper wire or a gold wire. An on-wiring insulating film formed on the insulating film so as to cover the wiring;
The semiconductor device according to claim 1, further comprising a rewiring formed on the insulating film on the wiring so as to be electrically connected to the wiring.   The semiconductor device according to claim 15, further comprising a bonding wire electrically connected to the rewiring. A connection electrode electrically connected to the wiring;
The semiconductor device according to claim 1, further comprising a wiring substrate having a bonding surface on which the semiconductor substrate is flip-chip bonded via the connection electrode.   The semiconductor device according to claim 17, further comprising a land disposed on a surface of the wiring board opposite to the bonding surface and electrically connected to the wiring through a via electrode. A connection electrode electrically connected to the wiring;
The semiconductor device according to claim 1, further comprising a sealing resin that covers a front surface, a back surface, and a side surface of the semiconductor substrate so as to expose the connection electrode. Forming an insulating film on the semiconductor substrate;
An opening that selectively exposes the insulating film; and a cover film having an inclined surface that partitions the opening so that an opening width of the opening gradually increases along a direction toward the insulating film. A cover film forming step to be formed thereon;
A wiring forming step of filling a conductor in the opening and forming a wiring including an inclined portion aligned with the inclined surface of the cover film. In the cover film forming step, the cover film having the curved inclined surface that curves toward the opening is formed,
21. The method of manufacturing a semiconductor device according to claim 20, wherein in the wiring formation step, the wiring including the inclined portion having a curved surface that matches the inclined surface of the cover film is formed. The cover film includes a photosensitive resin,
The method for manufacturing a semiconductor device according to claim 20, wherein the opening is formed by selectively exposing the cover film.   The method for manufacturing a semiconductor device according to any one of claims 20 to 22, further comprising a step of connecting a bonding wire to the wiring by setting the semiconductor substrate to a temperature of 200 ° C or higher after the wiring forming step. . Forming an insulating film on the semiconductor substrate;
Forming a first cover film having a first opening for selectively exposing the insulating film;
Filling the first opening with a conductor and forming a first conductor layer in the first opening;
Removing the first cover film;
Forming a second cover film having a second opening for selectively exposing the first conductor layer;
Filling the second opening with a conductor and forming a second conductor layer in the second opening,
The method of manufacturing a semiconductor device, wherein, in the step of forming the second cover film, the second opening is formed so that the first conductor layer protrudes from a peripheral edge of the second opening.

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