JP4238694B2 - Manufacturing method of semiconductor wafer and semiconductor chip - Google Patents

Manufacturing method of semiconductor wafer and semiconductor chip Download PDF

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JP4238694B2
JP4238694B2 JP2003359303A JP2003359303A JP4238694B2 JP 4238694 B2 JP4238694 B2 JP 4238694B2 JP 2003359303 A JP2003359303 A JP 2003359303A JP 2003359303 A JP2003359303 A JP 2003359303A JP 4238694 B2 JP4238694 B2 JP 4238694B2
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insulating film
opening
electrode
bump
substrate
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JP2004179635A (en
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朋子 名古
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Seiko Epson Corp
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Seiko Epson Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/1147—Manufacturing methods using a lift-off mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/049—Nitrides composed of metals from groups of the periodic table
    • H01L2924/0494—4th Group
    • H01L2924/04941—TiN
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06—Polymers
    • H01L2924/078—Adhesive characteristics other than chemical
    • H01L2924/0781—Adhesive characteristics other than chemical being an ohmic electrical conductor
    • H01L2924/07811—Extrinsic, i.e. with electrical conductive fillers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19041—Component type being a capacitor

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  • Non-Metallic Protective Coatings For Printed Circuits (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Description

本発明は、電子素子、電子素子の製造方法、回路基板、回路基板の製造方法、電子装置及び電子装置の製造方法に関する。   The present invention relates to an electronic element, a method for manufacturing an electronic element, a circuit board, a method for manufacturing a circuit board, an electronic device, and a method for manufacturing an electronic device.

図９に示すように、電極６２を有する回路基板６０上に電子素子５７を実装する方法にフリップチップ方式がある。フリップチップ方式では、電子素子５７の表面にバンプ５６を設けて、回路基板６０に対してバンプ５６を介して電子素子５７を搭載することにより、回路基板６０に電子素子５７を実装するものである。電子素子５７には、表面に電極５２と、電極５２に電気的に接続されたバンプ５６と、電子素子５７と電極５２との表面を保護する絶縁膜５３が形成されている。   As shown in FIG. 9, there is a flip chip method as a method of mounting the electronic element 57 on the circuit board 60 having the electrode 62. In the flip-chip method, the bump 56 is provided on the surface of the electronic element 57 and the electronic element 57 is mounted on the circuit board 60 by mounting the electronic element 57 on the circuit board 60 via the bump 56. . In the electronic element 57, an electrode 52, a bump 56 electrically connected to the electrode 52, and an insulating film 53 that protects the surface of the electronic element 57 and the electrode 52 are formed.

しかしながら、近年、電子素子５７が小型化、高集積化しており、それに伴いバンプ５６間の距離が短くなってきている。また、バンプ５６は、回路基板６０と電子素子５７の本体との間に一定の間隔を確保するために、ある程度高さを有する。
電子素子５７には、回路基板６０への実装後に封止されるまでは、絶縁膜５３上のバンプ５６間は樹脂等で絶縁されていない。このため、バンプ５６間の距離が短い電子素子５７の絶縁膜５３上で、バンプ５６を構成する金属のマイグレーションが起こり、バンプ５６間でショートが起こるおそれがある。また、電子素子５７を回路基板６０に実装する際には、バンプ５６が横方向に潰れやすく、バンプ５６間がさらにショートしやすくなるおそれもある。従って、図９に示す構造の電子素子５７の場合、電子素子５７の信頼性が低下する場合がある。 However, in recent years, the electronic element 57 has been downsized and highly integrated, and accordingly, the distance between the bumps 56 has been shortened. In addition, the bump 56 has a certain height in order to ensure a certain distance between the circuit board 60 and the main body of the electronic element 57.
Until the electronic element 57 is sealed after being mounted on the circuit board 60, the bumps 56 on the insulating film 53 are not insulated by a resin or the like. For this reason, migration of the metal constituting the bump 56 occurs on the insulating film 53 of the electronic element 57 having a short distance between the bumps 56, and there is a possibility that a short circuit may occur between the bumps 56. Further, when the electronic element 57 is mounted on the circuit board 60, the bumps 56 are liable to be crushed in the lateral direction, and the bumps 56 may be further short-circuited. Therefore, in the case of the electronic element 57 having the structure shown in FIG. 9, the reliability of the electronic element 57 may be reduced.

本発明は、このような状況に鑑みてなされたものであり、電子素子、回路基板及び電子装置の信頼性を高めることができる電子素子、電子素子の製造方法、回路基板、回路基板の製造方法、電子装置及び電子装置の製造方法を提供することができるようにするものである。   The present invention has been made in view of such circumstances, and an electronic element, a method for manufacturing an electronic element, a circuit board, and a method for manufacturing a circuit board that can improve the reliability of an electronic element, a circuit board, and an electronic device An electronic device and a method for manufacturing the electronic device can be provided.

本発明の半導体ウエハの製造方法によれば、半導体集積回路と、前記半導体集積回路を切断するスクライブ領域と、を含む半導体ウエハの製造方法であって、前記半導体集積回路と、その表面に設けられ前記半導体集積回路に電気的に接続した第１の電極と、前記スクライブ領域に形成された素子と、前記表面に設けられ前記スクライブ領域の素子と電気的に接続した第２の電極を形成する工程、前記表面に設けられ、前記第１の電極上に第１の開口部を有するとともに、前記第２の電極上に第２の開口部を有する第１の絶縁膜を形成する工程、前記第２の開口部上にレジスト膜を形成する工程、前記第１の絶縁膜上に第２の絶縁膜を形成する工程、前記第２の絶縁膜を除去して、前記第１の開口部上に第３の開口部を形成するとともに、前記第２の開口部上に前記レジスト膜を残して第４の開口部を形成する工程、前記第１の電極に電気的に接続するバンプを形成する工程、前記第２の開口部上のレジスト膜を除去する工程、を備えることを特徴とする。
また、本発明の半導体チップの製造方法は、前記半導体ウエハのスクライブ領域を切断することにより形成されることを特徴とする。
 According to the semiconductor wafer manufacturing method of the present invention, a semiconductor wafer manufacturing method including a semiconductor integrated circuit and a scribe region for cutting the semiconductor integrated circuit, the semiconductor integrated circuit being provided on the surface thereof. Forming a first electrode electrically connected to the semiconductor integrated circuit; an element formed in the scribe region; and a second electrode provided on the surface and electrically connected to the element in the scribe region. Forming a first insulating film provided on the surface and having a first opening on the first electrode and a second opening on the second electrode; Forming a resist film on the opening, forming a second insulating film on the first insulating film, removing the second insulating film, and forming a second insulating film on the first opening. 3 opening and front Forming a fourth opening while leaving the resist film on the second opening, forming a bump for electrically connecting to the first electrode, the resist film on the second opening And a step of removing.
Also, the semiconductor chip manufacturing method of the present invention is formed by cutting a scribe region of the semiconductor wafer.

これにより、スクライブ領域上に電極が形成されている場合においても、電極上にバンプが形成されないようにすることができる。このため、基板の切断時にスクライブ領域上のバンプが飛び散ることを防止することが可能となり、基板上の電子素子に損傷が及ぶことを防止することができる。
Thereby, even when the electrode is formed on the scribe region , the bump can be prevented from being formed on the electrode. For this reason, it becomes possible to prevent the bumps on the scribe region from scattering when the substrate is cut, and it is possible to prevent the electronic elements on the substrate from being damaged.

以下、本発明の実施の形態について説明する。
図１は、本発明の電子素子又は回路基板の一実施の形態を示す図、図２は、本発明の電子素子又は回路基板の製造方法の一実施の形態を説明するための工程図、図３は、本発明の電子装置及びその製造方法を説明するための図である。
図１（ａ）〜（ｃ）に示す電子素子又は回路基板は、表面に電極２と電極２上に第１の開口部８を有する第１の絶縁膜３を含む基板１（１ａ）の表面に、第１の絶縁膜３よりも厚く設けられた第２の絶縁膜４が設けられている。第２の絶縁膜４には、第１の開口部８を有する。第２の開口部５は、第１の開口部８の上方に位置する。第１の開口部８及び第２の開口部５内に、電極２に電気的に接続するバンプ６が設けられる。 Embodiments of the present invention will be described below.
FIG. 1 is a diagram showing an embodiment of an electronic element or circuit board according to the present invention. FIG. 2 is a process diagram for explaining an embodiment of a method for manufacturing an electronic element or circuit board according to the present invention. FIG. 3 is a diagram for explaining the electronic device and the manufacturing method thereof according to the present invention.
The electronic device or circuit board shown in FIGS. 1A to 1C has a surface of a substrate 1 (1a) including an electrode 2 on the surface and a first insulating film 3 having a first opening 8 on the electrode 2. In addition, a second insulating film 4 provided thicker than the first insulating film 3 is provided. The second insulating film 4 has a first opening 8. The second opening 5 is located above the first opening 8. A bump 6 that is electrically connected to the electrode 2 is provided in the first opening 8 and the second opening 5.

基板１（１ａ）は、内部に半導体集積回路を有しているチップ１ａ又はウエハ１であってもよい。基板１（１ａ）は、半導体基板を含んでもよい。また、基板１（１ａ）は、絶縁性基材と絶縁性基材上に電極２を有する基板であってもよい。基板１（１ａ）は、表面に電極２を有する。電極２は、導電材料からなり、内部の半導体集積回路に、内部配線を介して、電気的に接続している。内部配線は、内部配線間に設けられた層間絶縁膜により絶縁されている。たとえば、内部配線及び電極２は銅やアルミ等の導電材料からなる。この場合には、電極２は、層間絶縁膜の最表層上に位置することとなる。電極２上には、電極２上に第１の開口部８を有する第１の絶縁膜３が設けられている。電極２の表面が、第１の開口部８内で第１の絶縁膜３から露出して設けられている。第１の絶縁膜３は、少なくとも一部が電極２に被着していてもよい。   The substrate 1 (1a) may be a chip 1a or a wafer 1 having a semiconductor integrated circuit therein. The substrate 1 (1a) may include a semiconductor substrate. Moreover, the board | substrate which has the electrode 2 on an insulating base material and an insulating base material may be sufficient as the board | substrate 1 (1a). The substrate 1 (1a) has an electrode 2 on the surface. The electrode 2 is made of a conductive material and is electrically connected to an internal semiconductor integrated circuit via an internal wiring. The internal wiring is insulated by an interlayer insulating film provided between the internal wirings. For example, the internal wiring and the electrode 2 are made of a conductive material such as copper or aluminum. In this case, the electrode 2 is located on the outermost layer of the interlayer insulating film. On the electrode 2, a first insulating film 3 having a first opening 8 is provided on the electrode 2. The surface of the electrode 2 is exposed from the first insulating film 3 in the first opening 8. The first insulating film 3 may be at least partially attached to the electrode 2.

第２の絶縁膜４には、少なくとも電極２上に第２の開口部５が設けられている。第２の開口部５は、少なくとも第１の開口部８の上方に位置している。第１の開口部８と第２の開口部５とは、連続して設けられていてもよい。基板１（１ａ）上には、第１の絶縁膜３上に第２の絶縁膜４が設けられている。第２の絶縁膜４は、第１の絶縁膜３に被着していてもよい。図１に示すとおり、第２の開口部５の開口面積は第１の開口部８の開口面積よりも大きくてもよい。この場合、第１の開口部８外の第１の絶縁膜３上に、バンプ６の少なくとも一部を設けることができる。第１の絶縁膜３とバンプ６の界面から、電極２にめっき液等の不純物が侵入しにくくなる。また、第２の開口部５の開口面積は、第１の開口部８の開口面積と同じか、第１の開口部８の開口面積よりも小さくてもよい。また、第１の開口部８及び第２の開口部５の少なくともいずれか一方は、開口部の側面が傾斜して設けられていてもよい。   The second insulating film 4 is provided with a second opening 5 on at least the electrode 2. The second opening 5 is located at least above the first opening 8. The first opening 8 and the second opening 5 may be provided continuously. A second insulating film 4 is provided on the first insulating film 3 on the substrate 1 (1a). The second insulating film 4 may be attached to the first insulating film 3. As shown in FIG. 1, the opening area of the second opening 5 may be larger than the opening area of the first opening 8. In this case, at least a part of the bump 6 can be provided on the first insulating film 3 outside the first opening 8. Impurities such as a plating solution are less likely to enter the electrode 2 from the interface between the first insulating film 3 and the bump 6. The opening area of the second opening 5 may be the same as the opening area of the first opening 8 or may be smaller than the opening area of the first opening 8. In addition, at least one of the first opening 8 and the second opening 5 may be provided such that the side surface of the opening is inclined.

第１の絶縁膜３が無機物からなるとき、第２の絶縁膜４は樹脂からなるものであってもよい。たとえば、第１の絶縁膜３はシリコン酸化膜やシリコン窒化膜等から形成されてなり、第２の絶縁膜４はポリイミド樹脂やポリエチレンテレフタレート樹脂等から形成されてなる。第２の絶縁膜４は、感光性樹脂から構成されるものであってもよい。
バンプ６は、第１の開口部８と第２の開口部５内に形成されている。バンプ６は、電極２に電気的に接続する。バンプ６は、第１の開口部８外の第１の絶縁膜３上と第１の開口部８内とに設けられていてもよい。バンプ６は側面と、電極２側の底面と、底面と対向する側の先端部と、を有する。バンプ６は、単層又は複数層の導電層からなる。導電層は、金、ニッケル、錫、鉛等の金属、金−錫合金等の合金、窒化チタン等の金属化合物、銀ペースト等の導電ペースト、その他公知の材料を用いることができる。導電層の少なくとも一層は、無電解めっき法で形成されてもよい。 When the first insulating film 3 is made of an inorganic material, the second insulating film 4 may be made of a resin. For example, the first insulating film 3 is formed from a silicon oxide film, a silicon nitride film, or the like, and the second insulating film 4 is formed from a polyimide resin, a polyethylene terephthalate resin, or the like. The second insulating film 4 may be made of a photosensitive resin.
The bump 6 is formed in the first opening 8 and the second opening 5. The bump 6 is electrically connected to the electrode 2. The bumps 6 may be provided on the first insulating film 3 outside the first opening 8 and in the first opening 8. The bump 6 has a side surface, a bottom surface on the electrode 2 side, and a tip portion on the side facing the bottom surface. The bump 6 is composed of a single layer or a plurality of conductive layers. For the conductive layer, metals such as gold, nickel, tin, and lead, alloys such as gold-tin alloys, metal compounds such as titanium nitride, conductive pastes such as silver paste, and other known materials can be used. At least one layer of the conductive layer may be formed by an electroless plating method.

第１の絶縁膜３から露出したバンプ６の側面には、少なくとも一部が第２の絶縁膜４によって覆われている。図１（ｂ），（ｃ）に示すように、第２の絶縁膜４と第１の絶縁膜３によって、バンプ６の全側面が覆われてもよいし、図１（ａ）に示すように、一部が覆われてもよい。
バンプ６の先端部が、図１（ａ）に示すように、第２の絶縁膜４の表面から突出もよい。バンプ６の先端部は、図１（ａ）〜（ｃ）に示すように、平面になっていてもよい。この場合、図１（ｂ）に示すように、バンプ６の先端部は、第２の絶縁膜４の表面と面一になっていてもよい。バンプ６の先端部は、一部が凸状又は凹状になっていてもよい。バンプの先端部６は、平面でなくともよい。また、バンプ６は、図１（ｃ）に示すように、第２の絶縁膜４の表面に対して、バンプ６の先端部が凹んで設けられていてもよい。 At least a part of the side surface of the bump 6 exposed from the first insulating film 3 is covered with the second insulating film 4. As shown in FIGS. 1B and 1C, the entire side surface of the bump 6 may be covered with the second insulating film 4 and the first insulating film 3, or as shown in FIG. In addition, a part may be covered.
The tip of the bump 6 may protrude from the surface of the second insulating film 4 as shown in FIG. The tip of the bump 6 may be a flat surface as shown in FIGS. In this case, as shown in FIG. 1B, the tip of the bump 6 may be flush with the surface of the second insulating film 4. A part of the tip of the bump 6 may be convex or concave. The tip 6 of the bump need not be flat. Further, as shown in FIG. 1C, the bump 6 may be provided with the tip of the bump 6 being recessed with respect to the surface of the second insulating film 4.

次に、このような構成の電子素子又は回路基板の製造方法について説明する。
まず、図２（ａ）に示すように、複数の電極２と、電極２上に第１の開口部８を有する第１の絶縁膜３と、を有する基板１を用意する。基板１は、ウエハであってもよいし、絶縁性の基材上に電極２を有する基板であってもよい。第１の絶縁膜３は、シリコン酸化膜、シリコン窒化膜等の無機物からなるものであってもよい。 Next, a method for manufacturing the electronic element or circuit board having such a configuration will be described.
First, as shown in FIG. 2A, a substrate 1 having a plurality of electrodes 2 and a first insulating film 3 having a first opening 8 on the electrodes 2 is prepared. The substrate 1 may be a wafer or a substrate having the electrode 2 on an insulating base material. The first insulating film 3 may be made of an inorganic material such as a silicon oxide film or a silicon nitride film.

次いで、図２（ｂ）に示すように、その第１の絶縁膜３上に、第２の絶縁膜４を第１の絶縁膜３よりも厚く形成し、それぞれの電極２上の第２の絶縁膜４に第２の開口部５を形成する。第２の絶縁膜４に第２の開口部５を形成するに際しては、ドライエッチング又はウェットエッチングを用いてもよい。また、第２の絶縁膜４が感光性樹脂からなる場合、感光させて現像をすることにより、第２の開口部５を設けてもよい。   Next, as shown in FIG. 2B, the second insulating film 4 is formed on the first insulating film 3 to be thicker than the first insulating film 3, and the second insulating film 4 on each electrode 2 is formed. A second opening 5 is formed in the insulating film 4. In forming the second opening 5 in the second insulating film 4, dry etching or wet etching may be used. Moreover, when the 2nd insulating film 4 consists of photosensitive resin, you may provide the 2nd opening part 5 by exposing and developing.

次いで、図２（ｃ）に示すように、その第２の開口部５により露出する第１の絶縁膜３の少なくとも一部を除去して、第２の開口部５内の第１の絶縁膜３に第１の開口部８を形成する。この場合、第２の開口部５の開口面積より小さい開口部を有するマスクを用いて、第１の開口部８を設けてもよい。第１の開口部８は、ウェットエッチングやドライエッチングにより形成してもよい。第１の開口部８は、電極２の表面の少なくとも一部を露出させる。この後、めっき法によってバンプ６を形成する場合には、基板１を図示しないめっき槽内の所定の温度のめっき液に所定時間浸漬すると、電極２上に導電層が析出される。すなわち、第２の絶縁膜４の第２の開口部５の形状に沿った所定の高さのバンプ６が形成される。バンプ６の形成は、無電解めっき法により行ってもよい。   Next, as shown in FIG. 2C, at least a part of the first insulating film 3 exposed through the second opening 5 is removed, and the first insulating film in the second opening 5 is removed. 3, the first opening 8 is formed. In this case, the first opening 8 may be provided using a mask having an opening smaller than the opening area of the second opening 5. The first opening 8 may be formed by wet etching or dry etching. The first opening 8 exposes at least a part of the surface of the electrode 2. Thereafter, when the bump 6 is formed by plating, the conductive layer is deposited on the electrode 2 when the substrate 1 is immersed in a plating solution at a predetermined temperature in a plating tank (not shown) for a predetermined time. That is, the bump 6 having a predetermined height is formed along the shape of the second opening 5 of the second insulating film 4. The bump 6 may be formed by an electroless plating method.

次いで、図２（ｄ）に示すように、第２の絶縁膜４は、第２の絶縁膜４の少なくとも一部を第１の絶縁膜３上に残して、第２の絶縁膜４を厚み方向に除去してもよい。この場合、図１（ａ）に示したように、バンプ６の先端部が第２の絶縁膜４の表面より突出するように第２の絶縁膜４をエッチングしてもよい。
ここで、たとえば図１（ｂ）に示した電子素子７を形成する場合には、図２（ｄ）において、バンプ６の先端部が第２の絶縁膜４の表面と面一となるように第２の絶縁膜４をエッチングする。また、たとえば図１（ｃ）に示した電子素子７を形成する場合には、図２（ｄ）において、バンプ６の先端部が第２の絶縁膜４の表面より低くなる（凹む）ように第２の絶縁膜４をエッチングする。この場合、図１（ａ）や（ｂ）に記載されたものと異なり、第２の絶縁膜４は少量除去されるか、除去されずに済むので、製造工程時間の短縮を図ることができる。 Next, as shown in FIG. 2D, the second insulating film 4 has a thickness of the second insulating film 4 while leaving at least a part of the second insulating film 4 on the first insulating film 3. It may be removed in the direction. In this case, as shown in FIG. 1A, the second insulating film 4 may be etched so that the tip of the bump 6 protrudes from the surface of the second insulating film 4.
Here, for example, when the electronic device 7 shown in FIG. 1B is formed, the tip of the bump 6 is flush with the surface of the second insulating film 4 in FIG. The second insulating film 4 is etched. Further, for example, when the electronic element 7 shown in FIG. 1C is formed, the tip of the bump 6 is lower (dented) than the surface of the second insulating film 4 in FIG. The second insulating film 4 is etched. In this case, unlike the one described in FIGS. 1A and 1B, the second insulating film 4 is removed in a small amount or may not be removed, so that the manufacturing process time can be shortened. .

その後、図２（ｅ）に示すように、基板１を切断してもよい。これにより、たとえば、図１（ａ）〜（ｃ）に示したような、バンプ６と個片化された基板１ａとを有する複数の電子素子７又は回路基板７が形成される。基板１の切断は、図のような切断治具１４Ａを用いて、ダイシング、スクライビング又は打ち抜き等によって行うことができる。切断工程においては、基板１の裏面に、テープ１３を設けて、切断を行ってもよい。   Thereafter, the substrate 1 may be cut as shown in FIG. Thereby, for example, as shown in FIGS. 1A to 1C, a plurality of electronic elements 7 or circuit boards 7 having the bumps 6 and the separated substrate 1a are formed. The substrate 1 can be cut by dicing, scribing, or punching using a cutting jig 14A as shown in the drawing. In the cutting step, the tape 13 may be provided on the back surface of the substrate 1 for cutting.

次に、本発明の一実施態様に係る電子装置の製造方法について説明する。
まず、図３（ａ）に示す電子装置は、図１（ａ）及び（ｂ）の電子素子７のバンプ６が回路基板１０の電極１１にフェースダウンボンディング法を用いて電気的に接続され、実装される状態を示している。ここで、回路基板１０は、基材１２と基材１２上に設けられた電極１１とを有する。電極１１は、ランドに電気的に接続されたリード線と、リード線を覆う絶縁膜とを含んでもよい。回路基板１０として、ＴＡＢ用の回路基板を用いてもよい。バンプ６と電極１１とは、接着剤接合、金属接合等の公知の方式で接合されていてもよい。 Next, a method for manufacturing an electronic device according to an embodiment of the present invention will be described.
First, in the electronic device shown in FIG. 3A, the bumps 6 of the electronic element 7 in FIGS. 1A and 1B are electrically connected to the electrodes 11 of the circuit board 10 using the face-down bonding method. The state where it is mounted is shown. Here, the circuit board 10 includes a base material 12 and an electrode 11 provided on the base material 12. The electrode 11 may include a lead wire electrically connected to the land and an insulating film covering the lead wire. As the circuit board 10, a TAB circuit board may be used. The bump 6 and the electrode 11 may be bonded by a known method such as adhesive bonding or metal bonding.

図１（ａ）の電子素子７を回路基板１０に接着剤接合を用いて実装する場合には、たとえば回路基板１０の表面に異方性導電接着剤、絶縁性接着剤等の接着剤を設ける。この接着剤を介して、電子素子７のバンプ６を回路基板１０の電極１１に位置合せした後、熱圧着することにより電子素子７のバンプ６と基板１０ａの電極１１とを接合する。さらに、電子素子７をエポキシ樹脂等によってモールドして封止するようにしてもよい。   When the electronic element 7 of FIG. 1A is mounted on the circuit board 10 using adhesive bonding, for example, an adhesive such as an anisotropic conductive adhesive or an insulating adhesive is provided on the surface of the circuit board 10. . The bump 6 of the electronic element 7 is aligned with the electrode 11 of the circuit board 10 through this adhesive, and then the bump 6 of the electronic element 7 and the electrode 11 of the board 10a are joined by thermocompression bonding. Furthermore, the electronic element 7 may be molded and sealed with an epoxy resin or the like.

電子素子７を回路基板１０に金属接合によって実装する場合には、例えば、バンプ６を構成する導電材料よりも低融点の低融点金属層１４をバンプ６の先端部に設けて接合をしてもよい。回路基板１０の電極１１上にバンプ６を構成する導電材料よりも低融点の低融点金属層１４を設けてもよい。電子素子７のバンプ６を、回路基板１０の電極１１に低融点金属層１４を介して位置合せし、加熱することにより電子素子７のバンプ６と回路基板１０の電極１１とを接合する。この後、樹脂を電子素子７と回路基板１０の間に封入して、封止してもよい。   When the electronic element 7 is mounted on the circuit board 10 by metal bonding, for example, a low melting point metal layer 14 having a lower melting point than the conductive material constituting the bump 6 may be provided at the tip of the bump 6 for bonding. Good. A low melting point metal layer 14 having a lower melting point than the conductive material constituting the bump 6 may be provided on the electrode 11 of the circuit board 10. The bumps 6 of the electronic element 7 are aligned with the electrodes 11 of the circuit board 10 via the low melting point metal layer 14, and the bumps 6 of the electronic element 7 and the electrodes 11 of the circuit board 10 are joined by heating. Thereafter, the resin may be sealed between the electronic element 7 and the circuit board 10 and sealed.

次に、図３（ｂ）に示す電子装置は、図１（ｃ）の電子素子７のバンプ６が回路基板１０の電極１１にワイヤボンディング法を用いて電気的に接続され、実装される状態を示している。図１（ｃ）の電子素子７を回路基板１０に実装する場合には、回路基板１０に、電子素子７のバンプ６が設けられていない面を固着し、バンプ６と電極１１との間を金属ワイヤ１５により接続する。さらに、電子素子７をエポキシ樹脂等によってモールドして封止するようにしてもよい。   Next, in the electronic device shown in FIG. 3B, the bump 6 of the electronic element 7 in FIG. 1C is electrically connected to the electrode 11 of the circuit board 10 by using the wire bonding method and mounted. Is shown. When the electronic element 7 of FIG. 1C is mounted on the circuit board 10, the surface of the electronic element 7 on which the bump 6 is not provided is fixed to the circuit board 10, and the gap between the bump 6 and the electrode 11 is fixed. The metal wires 15 are connected. Furthermore, the electronic element 7 may be molded and sealed with an epoxy resin or the like.

図４は、本発明の第２実施形態に係る電子素子の製造方法を示す断面図である。
図４（ａ）において、パッド電極１０２が形成された基板１０１には第１の絶縁膜１０３が形成され、第１の絶縁膜１０３にはパッド電極１０２の表面を露出させる開口部１０８が形成されている。なお、基板１０１にはトランジスタなどの能動素子またはキャパシタなどの受動素子を形成することができる。また、第１の絶縁膜１０３は、例えば、シリコン酸化膜、シリコン窒化膜またはポリイミド膜などを用いることができる。 FIG. 4 is a cross-sectional view illustrating a method for manufacturing an electronic device according to a second embodiment of the present invention.
4A, a first insulating film 103 is formed on the substrate 101 on which the pad electrode 102 is formed, and an opening 108 that exposes the surface of the pad electrode 102 is formed in the first insulating film 103. In FIG. ing. Note that an active element such as a transistor or a passive element such as a capacitor can be formed over the substrate 101. For the first insulating film 103, for example, a silicon oxide film, a silicon nitride film, a polyimide film, or the like can be used.

次に、図４（ｂ）に示すように、第１の絶縁膜１０３が形成された基板１０１上に第２の絶縁膜１０４を形成する。なお、第２の絶縁膜１０４としては、例えば、感光性樹脂層を用いることができ、スピンコート、カーテンコート、スクリーン印刷、インクジェット法などを用いて感光性樹脂層を形成することができる。そして、例えば、第２の絶縁膜１０４の露光・現像を行うことにより、パッド電極１０２上に開口部１０５を形成するとともに、スクライブラインＳＬを露出させる開口部１１５を第２の絶縁膜１０４に形成する。   Next, as shown in FIG. 4B, a second insulating film 104 is formed on the substrate 101 on which the first insulating film 103 is formed. Note that as the second insulating film 104, for example, a photosensitive resin layer can be used, and the photosensitive resin layer can be formed by spin coating, curtain coating, screen printing, an inkjet method, or the like. Then, for example, by performing exposure / development of the second insulating film 104, the opening 105 is formed on the pad electrode 102 and the opening 115 exposing the scribe line SL is formed in the second insulating film 104. To do.

次に、図４（ｃ）に示すように、無電解メッキを用いることにより、パッド電極１０２に接続されたバンプ１０６を開口部１０５内に形成する。なお、バンプ１０６としては、例えば、ニッケルＮｉ、金Ａｕ、銅Ｃｕ、半田などを用いることができる。
また、無電解メッキとしては、例えば、パッド電極１０２がアルミニウムＡｌで構成され、バンプ１０６としてニッケルＮｉを用いる場合、アルカリ性亜鉛溶液を用いて、パッド電極１０２にジンケート処理を施し、パッド電極１０２の表面に亜鉛Ｚｎを置換・析出させる。 Next, as shown in FIG. 4C, bumps 106 connected to the pad electrodes 102 are formed in the openings 105 by using electroless plating. For example, nickel Ni, gold Au, copper Cu, or solder can be used as the bump 106.
Further, as the electroless plating, for example, when the pad electrode 102 is made of aluminum Al and nickel Ni is used for the bump 106, a zincate treatment is performed on the pad electrode 102 using an alkaline zinc solution, and the surface of the pad electrode 102. Zinc Zn is substituted and deposited on the substrate.

そして、表面が亜鉛Ｚｎに置換されたパッド電極１０２を無電解ニッケルメッキ液に浸すことで、亜鉛ＺｎとニッケルＮｉとを置換させ、ニッケルＮｉで構成されるバンプ１０６をパッド電極１０２上に形成することができる。
また、ジンケート処理とは別の方法として、例えば、アルミニウムＡｌからなるパッド電極１０２をパラジウムなどの還元剤を含む溶液に浸した後、無電解ニッケルメッキ液に浸すことで、パラジウムなどを核として、ニッケルＮｉで構成されるバンプ１０６をパッド電極１０２上に析出させることもできる。 Then, by immersing the pad electrode 102 whose surface is replaced with zinc Zn in an electroless nickel plating solution, zinc Zn and nickel Ni are replaced, and a bump 106 made of nickel Ni is formed on the pad electrode 102. be able to.
In addition, as a method different from the zincate treatment, for example, after immersing the pad electrode 102 made of aluminum Al in a solution containing a reducing agent such as palladium, by immersing it in an electroless nickel plating solution, A bump 106 made of nickel Ni can be deposited on the pad electrode 102.

次に、図４（ｄ）に示すように、第２の絶縁膜１０４を薄膜化することにより、第２の絶縁膜１０４上にバンプ１０６を突出させる。なお、第２の絶縁膜１０４を薄膜化する工程は省略してもよい。
次に、図４（ｅ）に示すように、バンプ１０６が形成された基板１０１をスクライブラインＳＬに沿って切断することにより、バンプ１０６が形成された基板１０１をチップ化する。なお、基板１０１の切断は、図のような切断治具１４Ａを用いて、ダイシング、スクライビング又は打ち抜き等によって行うことができる。また、切断工程においては、基板１０１の裏面にテープ１１３を設けて、切断を行ってもよい。 Next, as shown in FIG. 4D, the second insulating film 104 is thinned, and the bumps 106 are projected on the second insulating film 104. Note that the step of thinning the second insulating film 104 may be omitted.
Next, as shown in FIG. 4E, the substrate 101 on which the bumps 106 are formed is cut along the scribe lines SL, thereby forming the substrate 101 on which the bumps 106 are formed into chips. The substrate 101 can be cut by dicing, scribing, punching, or the like using a cutting jig 14A as shown in the drawing. In the cutting process, the tape 113 may be provided on the back surface of the substrate 101 to perform cutting.

これにより、バンプ１０６の周囲に第２の絶縁膜を１０４設けた場合においても、第２の絶縁膜１０４が基板１０１の切断の邪魔になることを防止することができ、バンプ１０６間でのマイグレーションの発生を抑制することを可能としつつ、基板１０１の切断を円滑に行うことが可能となる。
図５は、本発明の第３実施形態に係る電子素子の製造方法を示す断面図である。 As a result, even when the second insulating film 104 is provided around the bump 106, the second insulating film 104 can be prevented from interfering with the cutting of the substrate 101, and migration between the bumps 106 can be prevented. It is possible to smoothly cut the substrate 101 while suppressing the occurrence of this.
FIG. 5 is a sectional view showing a method for manufacturing an electronic device according to the third embodiment of the present invention.

図５（ａ）において、基板１２１にはパッド電極１２２が形成されるとともに、基板１２１のスクライブラインＳＬ上にはモニタ用電極１３２が形成されている。そして、パッド電極１２２およびモニタ用電極１３２が形成された基板１２１には第１の絶縁膜１２３が形成されている。そして、第１の絶縁膜１２３には、パッド電極１２２の表面を露出させる開口部１２８が形成されるとともに、モニタ用電極１３２を露出させる開口部１３８が形成されている。なお、基板１２１にはトランジスタなどの能動素子またはキャパシタなどの受動素子を形成することができる。   In FIG. 5A, a pad electrode 122 is formed on the substrate 121, and a monitor electrode 132 is formed on the scribe line SL of the substrate 121. A first insulating film 123 is formed on the substrate 121 on which the pad electrode 122 and the monitor electrode 132 are formed. The first insulating film 123 has an opening 128 that exposes the surface of the pad electrode 122 and an opening 138 that exposes the monitor electrode 132. Note that an active element such as a transistor or a passive element such as a capacitor can be formed over the substrate 121.

次に、図５（ｂ）に示すように、フォトリソグラフィー技術を用いることにより、モニタ用電極１３２を覆うレジスト層１２９を基板１２１上に形成する。
次に、図５（ｃ）に示すように、第１の絶縁膜１２３が形成された基板１２１上に第２の絶縁膜１２４を形成する。なお、第２の絶縁膜１２４としては、例えば、感光性樹脂層を用いることができる。そして、例えば、第２の絶縁膜１２４の露光・現像を行うことにより、パッド電極１２２上に開口部１２５を形成するとともに、スクライブラインＳＬを露出させる開口部１１５を第２の絶縁膜１２４に形成する。 Next, as illustrated in FIG. 5B, a resist layer 129 that covers the monitor electrode 132 is formed on the substrate 121 by using a photolithography technique.
Next, as shown in FIG. 5C, a second insulating film 124 is formed on the substrate 121 on which the first insulating film 123 is formed. For example, a photosensitive resin layer can be used as the second insulating film 124. Then, for example, by performing exposure / development of the second insulating film 124, the opening 125 is formed on the pad electrode 122 and the opening 115 exposing the scribe line SL is formed in the second insulating film 124. To do.

次に、図５（ｄ）に示すように、無電解メッキを用いることにより、パッド電極１２２に接続されたバンプ１２６を開口部１２５内に形成する。ここで、モニタ用電極１３２をレジスト層１２９で覆ってから無電解メッキを行うことにより、モニタ用電極１３２上にバンプが形成されることを防止することができる。
次に、図５（ｅ）に示すように、全面のエッチングを行うことにより、第２の絶縁膜１２４を薄膜化し、第２の絶縁膜１２４上にバンプ１２６を突出させるとともに、モニタ用電極１３２を覆うレジスト層１２９を除去する。 Next, as shown in FIG. 5D, the bump 126 connected to the pad electrode 122 is formed in the opening 125 by using electroless plating. Here, the electroless plating is performed after the monitor electrode 132 is covered with the resist layer 129, whereby bumps can be prevented from being formed on the monitor electrode 132.
Next, as shown in FIG. 5E, by etching the entire surface, the second insulating film 124 is thinned, and the bumps 126 are projected on the second insulating film 124, and the monitoring electrode 132 is provided. The resist layer 129 that covers is removed.

次に、図５（ｆ）に示すように、バンプ１２６が形成された基板１２１をスクライブラインＳＬに沿って切断することにより、バンプ１２６が形成された基板１２１をチップ化する。なお、基板１２１の切断は、図のような切断治具１４Ａを用いて、ダイシング、スクライビング又は打ち抜き等によって行うことができる。また、切断工程においては、基板１２１の裏面にテープ１３３を設けて、切断を行ってもよい。   Next, as shown in FIG. 5F, the substrate 121 on which the bumps 126 are formed is cut along the scribe lines SL, thereby forming the substrate 121 on which the bumps 126 are formed into chips. The substrate 121 can be cut by dicing, scribing, or punching using a cutting jig 14A as shown in the drawing. Further, in the cutting step, the tape 133 may be provided on the back surface of the substrate 121 for cutting.

これにより、スクライブラインＳＬ上にモニタ用電極１３２が形成されている場合においても、モニタ用電極１３２上にバンプが配置された状態で、基板１２１の切断が行われることを防止することができる。このため、基板１２１の切断時にモニタ用電極１３２上のバンプが飛び散ることを防止することが可能となり、基板１２１上の電子素子に損傷が及ぶことを防止することができる。   Thereby, even when the monitor electrode 132 is formed on the scribe line SL, it is possible to prevent the substrate 121 from being cut while the bump is disposed on the monitor electrode 132. Therefore, it is possible to prevent the bumps on the monitor electrode 132 from being scattered when the substrate 121 is cut, and it is possible to prevent the electronic elements on the substrate 121 from being damaged.

図６は、本発明の第４実施形態に係る電子素子の製造方法を示す断面図である。
図６（ａ）において、パッド電極１４２が形成された基板１４１には第１の絶縁膜１４３が形成され、第１の絶縁膜１４３にはパッド電極１４２の表面を露出させる開口部１４８が形成されている。なお、基板１４１にはトランジスタなどの能動素子またはキャパシタなどの受動素子を形成することができる。 FIG. 6 is a cross-sectional view illustrating a method for manufacturing an electronic device according to a fourth embodiment of the present invention.
6A, a first insulating film 143 is formed on the substrate 141 on which the pad electrode 142 is formed, and an opening 148 that exposes the surface of the pad electrode 142 is formed in the first insulating film 143. ing. Note that an active element such as a transistor or a passive element such as a capacitor can be formed over the substrate 141.

次に、図６（ｂ）に示すように、例えば、無電解メッキ、スパッタまたは蒸着などにより、パッド電極１４２を含む第１の絶縁膜１４３上にシード電極１４９を形成する。なお、シード電極１４９としては、例えば、ニッケルＮｉ、クロムＣｒ、チタンＴｉ、タングステンＷなどの導電材料を用いることができる。ここで、シード電極１４９は、パッド電極１４２ごとに分離されるように構成することができる。   Next, as shown in FIG. 6B, a seed electrode 149 is formed on the first insulating film 143 including the pad electrode 142 by, for example, electroless plating, sputtering, or vapor deposition. For the seed electrode 149, for example, a conductive material such as nickel Ni, chromium Cr, titanium Ti, or tungsten W can be used. Here, the seed electrode 149 can be configured to be separated for each pad electrode 142.

図７は、図６のシード電極の概略構成を示す平面図である。
図７において、ウェハＷには、スクライブラインＳＬが設けられるとともに、給電電極１５０が設けられている。そして、スクライブラインＳＬで区画された各チップ領域には、パッド電極１４２ごとに分離されたシード電極１４９が設けられている。そして、各パッド電極１４２上のシード電極１４９はスクライブラインＳＬ上に延伸され、スクライブラインＳＬを介して給電電極１５０に接続されている。 FIG. 7 is a plan view showing a schematic configuration of the seed electrode of FIG.
In FIG. 7, the wafer W is provided with a scribe line SL and a power supply electrode 150. In each chip region partitioned by the scribe line SL, a seed electrode 149 separated for each pad electrode 142 is provided. The seed electrode 149 on each pad electrode 142 extends on the scribe line SL and is connected to the power supply electrode 150 via the scribe line SL.

次に、図６（ｃ）に示すように、シード電極１４９が形成された基板１４１上に第２の絶縁膜１４４を形成する。なお、第２の絶縁膜１４４としては、例えば、感光性樹脂層を用いることができる。そして、例えば、第２の絶縁膜１４４の露光・現像を行うことにより、パッド電極１４２に接続されたシード電極１４９上に開口部１４５を形成する。
次に、図６（ｄ）に示すように、シード電極１４９をメッキリードとした電解メッキを行うことにより、シード電極１４９に接続されたバンプ１４６を開口部１４５内に形成する。なお、バンプ１４６としては、例えば、ニッケルＮｉ、金Ａｕ、銅Ｃｕなどを用いることができる。また、バンプ１４６を開口部１４５内に形成する場合、バンプ１４６が開口部１４５内に沈み込むようにしてもよいし、第２の絶縁膜１４４上に盛り上がるようにしてもよい。 Next, as shown in FIG. 6C, a second insulating film 144 is formed on the substrate 141 on which the seed electrode 149 is formed. For example, a photosensitive resin layer can be used as the second insulating film 144. Then, for example, the opening 145 is formed on the seed electrode 149 connected to the pad electrode 142 by performing exposure and development of the second insulating film 144.
Next, as shown in FIG. 6D, bumps 146 connected to the seed electrodes 149 are formed in the openings 145 by performing electrolytic plating using the seed electrodes 149 as plating leads. As the bump 146, for example, nickel Ni, gold Au, copper Cu, or the like can be used. Further, when the bump 146 is formed in the opening 145, the bump 146 may sink into the opening 145 or may be raised on the second insulating film 144.

次に、図６（ｅ）に示すように、第２の絶縁膜１４４を薄膜化することにより、第２の絶縁膜１４４上にバンプ１４６を突出させる。なお、第２の絶縁膜１４４を薄膜化する工程は省略してもよい。
次に、図６（ｆ）に示すように、バンプ１４６が形成された基板１４１をスクライブラインＳＬに沿って切断することにより、バンプ１４６が形成された基板１４１をチップ化する。なお、基板１４１の切断は、図のような切断治具１４Ａを用いて、ダイシング、スクライビング又は打ち抜き等によって行うことができる。また、切断工程においては、基板１４１の裏面にテープ１５３を設けて、切断を行ってもよい。 Next, as illustrated in FIG. 6E, the second insulating film 144 is thinned to project the bumps 146 on the second insulating film 144. Note that the step of thinning the second insulating film 144 may be omitted.
Next, as shown in FIG. 6F, the substrate 141 on which the bumps 146 are formed is cut along the scribe lines SL, thereby forming the substrate 141 on which the bumps 146 are formed into chips. The substrate 141 can be cut by dicing, scribing, punching, or the like using a cutting jig 14A as shown in the drawing. In the cutting step, the tape 153 may be provided on the back surface of the substrate 141 to perform cutting.

ここで、シード電極１４９をパッド電極１４２ごとに分離してから、第２の絶縁膜１４４を形成することにより、パッド電極１４２の周囲に第２の絶縁膜１４４が連続的に形成された場合においても、パッド電極１４２同士が互いにショートしたままの状態になることを防止することができる。
また、スクライブラインＳＬを介してシード電極１４９を給電電極１５０に接続することにより、シード電極１４９をパッド電極１４２ごとに分離した場合においても、シード電極１４９に給電することが可能となる。このため、パッド電極１４２に接続されたバンプ１４６を電解メッキにて形成することが可能となり、バンプ１４６間のマイグレーション耐性を向上させることを可能としつつ、バンプ１４６を効率よく形成することが可能となる。 Here, in the case where the second insulating film 144 is continuously formed around the pad electrode 142 by forming the second insulating film 144 after separating the seed electrode 149 for each pad electrode 142. In addition, it is possible to prevent the pad electrodes 142 from being short-circuited with each other.
In addition, by connecting the seed electrode 149 to the power supply electrode 150 via the scribe line SL, power can be supplied to the seed electrode 149 even when the seed electrode 149 is separated for each pad electrode 142. For this reason, the bump 146 connected to the pad electrode 142 can be formed by electrolytic plating, and the bump 146 can be efficiently formed while improving the migration resistance between the bumps 146. Become.

図８は、本発明の第５実施形態に係る電子素子の製造方法を示す断面図である。
図８（ａ）において、パッド電極１６２が形成された半導体チップ１６１には第１の絶縁膜１６３が形成され、第１の絶縁膜１６３にはパッド電極１６２の表面を露出させる開口部１６４が形成されている。なお、半導体チップ１６１にはトランジスタなどの能動素子またはキャパシタなどの受動素子を形成することができる。また、第１の絶縁膜１６３は、例えば、シリコン酸化膜、シリコン窒化膜またはポリイミド膜などを用いることができる。 FIG. 8 is a sectional view showing a method for manufacturing an electronic device according to the fifth embodiment of the present invention.
8A, a first insulating film 163 is formed on the semiconductor chip 161 on which the pad electrode 162 is formed, and an opening 164 that exposes the surface of the pad electrode 162 is formed in the first insulating film 163. Has been. Note that an active element such as a transistor or a passive element such as a capacitor can be formed on the semiconductor chip 161. The first insulating film 163 can be formed using, for example, a silicon oxide film, a silicon nitride film, or a polyimide film.

また、半導体チップ１６１上には、パッド電極１６２が露出するようにして応力緩和層１６５が形成され、パッド電極１６２には、応力緩和層１６５上に延伸された再配置配線１６６が接続されている。
なお、応力緩和層１６５としては、例えば、ポリイミド樹脂、エポキシ樹脂、シリコーン樹脂などを用いることができ、特に、応力緩和機能を付加しつつ、ハンダ溶融時の耐熱性を持たせるためには、オレフィン系のポリイミド樹脂を用いることが好ましい。また、再配置配線１６６は、例えば、ＴｉＷスパッタ配線層、Ｃｕスパッタ配線層およびＣｕメッキ配線層の３層構造から構成することができる。 Further, a stress relaxation layer 165 is formed on the semiconductor chip 161 so as to expose the pad electrode 162, and a rearrangement wiring 166 extending on the stress relaxation layer 165 is connected to the pad electrode 162. .
As the stress relaxation layer 165, for example, a polyimide resin, an epoxy resin, a silicone resin, or the like can be used. In particular, in order to provide heat resistance during solder melting while adding a stress relaxation function, an olefin is used. It is preferable to use a polyimide resin. Further, the rearrangement wiring 166 can be constituted by, for example, a three-layer structure of a TiW sputter wiring layer, a Cu sputter wiring layer, and a Cu plating wiring layer.

次に、図８（ｂ）に示すように、再配置配線１６６が形成された半導体チップ１６１上に第２の絶縁膜１６７を形成する。なお、第２の絶縁膜１６７としては、例えば、感光性樹脂層を用いることができ、スピンコート、カーテンコート、スクリーン印刷、インクジェット法などを用いて感光性樹脂層を形成することができる。そして、例えば、第２の絶縁膜１６７の露光・現像を行うことにより、再配置配線１６６上に開口部１６８を形成する。   Next, as shown in FIG. 8B, a second insulating film 167 is formed on the semiconductor chip 161 on which the rearrangement wiring 166 is formed. Note that as the second insulating film 167, for example, a photosensitive resin layer can be used, and the photosensitive resin layer can be formed by spin coating, curtain coating, screen printing, an inkjet method, or the like. Then, for example, the opening 168 is formed on the rearrangement wiring 166 by performing exposure and development of the second insulating film 167.

次に、図８（ｃ）に示すように、例えば、無電解メッキを用いることにより、再配置配線１６６に接続されたバンプ１６９を開口部１６８内に形成する。なお、バンプ１６９としては、例えば、ニッケルＮｉ、金Ａｕ、銅Ｃｕ、半田などを用いることができる。また、第２の絶縁膜１６７を形成する前に、パッド電極１６２に接続されたシード電極を形成し、シード電極をメッキリードとした電解メッキにてバンプ１６９を形成するようにしてもよい。   Next, as shown in FIG. 8C, bumps 169 connected to the rearrangement wiring 166 are formed in the opening 168 by using, for example, electroless plating. As the bump 169, for example, nickel Ni, gold Au, copper Cu, solder, or the like can be used. In addition, before forming the second insulating film 167, a seed electrode connected to the pad electrode 162 may be formed, and the bump 169 may be formed by electrolytic plating using the seed electrode as a plating lead.

次に、図８（ｄ）に示すように、第２の絶縁膜１６７を薄膜化することにより、第２の絶縁膜１６７上にバンプ１６９を突出させる。なお、第２の絶縁膜１６７を薄膜化する工程は省略してもよい。
これにより、チップサイズを増大させることなく、パッド電極１６２の配置位置を変換することが可能となるとともに、バンプ１６９間のマイグレーション耐性を向上させることを可能となり、電子素子の信頼性の向上を図りつつ、電子素子の小型化を達成することが可能となる。 Next, as illustrated in FIG. 8D, the second insulating film 167 is thinned, so that the bumps 169 protrude on the second insulating film 167. Note that the step of thinning the second insulating film 167 may be omitted.
As a result, the arrangement position of the pad electrode 162 can be changed without increasing the chip size, the migration resistance between the bumps 169 can be improved, and the reliability of the electronic element can be improved. However, it is possible to reduce the size of the electronic element.

本発明の電子素子の一実施の形態を示す図である。It is a figure which shows one Embodiment of the electronic device of this invention. 図１（ａ）〜（ｃ）の電子素子の製造方法を説明するための工程図。Process drawing for demonstrating the manufacturing method of the electronic device of Fig.1 (a)-(c). 本発明の電子装置の一実施の形態を示す図である。It is a figure which shows one Embodiment of the electronic device of this invention. 本発明の第２実施形態に係る電子素子の製造方法を示す断面図である。It is sectional drawing which shows the manufacturing method of the electronic device which concerns on 2nd Embodiment of this invention. 本発明の第３実施形態に係る電子素子の製造方法を示す断面図である。It is sectional drawing which shows the manufacturing method of the electronic device which concerns on 3rd Embodiment of this invention. 本発明の第４実施形態に係る電子素子の製造方法を示す断面図である。It is sectional drawing which shows the manufacturing method of the electronic device which concerns on 4th Embodiment of this invention. 図６のシード電極の概略構成を示す平面図である。It is a top view which shows schematic structure of the seed electrode of FIG. 本発明の第５実施形態に係る電子素子の製造方法を示す断面図である。It is sectional drawing which shows the manufacturing method of the electronic device which concerns on 5th Embodiment of this invention. 従来の電子素子を示す工程図である。It is process drawing which shows the conventional electronic element.

符号の説明Explanation of symbols

１（１ａ）、１０１、１２１、１４１ 基板、２、１１、１０２、１２２、１３２、１４２、１６２ 電極、３、１０３、１２３、１４３、１６３ 第１の絶縁膜、４、１０４、１２４、１４４、１６７ 第２の絶縁膜、５、１０５、１２５、１４５、１６８ 第２の開口部、６、１０６、１２６、１４６、１６９ バンプ、７、１０７、１２７、１４７ 電子素子、８、１０８、１２８、１４８、１６４ 第１の開口部、１０ 回路基板、１３、１１３、１３３、１５３ テープ、１４ 低融点金属層、１５ 金属ワイヤ、１１５、１３８ 第３の開口部、１２９ 第３の絶縁膜、１３５ 第４の開口部、１４９ シード電極、Ｗ ウェハ、ＳＬ スクライブライン、１５０ 給電端子、１６１ 半導体チップ、１６５ 応力緩和層、１６６ 再配置配線   1 (1a), 101, 121, 141 Substrate, 2, 11, 102, 122, 132, 142, 162 Electrode 3, 103, 123, 143, 163 First insulating film 4, 104, 124, 144, 167 Second insulating film 5, 105, 125, 145, 168 Second opening, 6, 106, 126, 146, 169 Bump, 7, 107, 127, 147 Electronic element, 8, 108, 128, 148 164 First opening, 10 Circuit board, 13, 113, 133, 153 Tape, 14 Low melting point metal layer, 15 Metal wire, 115, 138 Third opening, 129 Third insulating film, 135 4th 149 seed electrode, W wafer, SL scribe line, 150 power supply terminal, 161 semiconductor chip, 165 stress relaxation layer, 166 relocation wiring

Claims (2)

半導体集積回路と、
前記半導体集積回路を切断するスクライブ領域と、
を含む半導体ウエハの製造方法であって、
前記半導体集積回路と、その表面に設けられ前記半導体集積回路に電気的に接続した第１の電極と、
前記スクライブ領域に形成された素子と、前記表面に設けられ前記スクライブ領域の素子と電気的に接続した第２の電極を形成する工程、
前記表面に設けられ、前記第１の電極上に第１の開口部を有するとともに、前記第２の電極上に第２の開口部を有する第１の絶縁膜を形成する工程、
前記第２の開口部上にレジスト膜を形成する工程、
前記第１の絶縁膜上に第２の絶縁膜を形成する工程、
前記第２の絶縁膜を除去して、前記第１の開口部上に第３の開口部を形成するとともに、前記第２の開口部上に前記レジスト膜を残して第４の開口部を形成する工程、
前記第１の電極に電気的に接続するバンプを形成する工程、
前記第２の開口部上のレジスト膜を除去する工程、
を備えることを特徴とする半導体ウエハの製造方法。 A semiconductor integrated circuit;
A scribe region for cutting the semiconductor integrated circuit;
A method of manufacturing a semiconductor wafer comprising:
The semiconductor integrated circuit and a first electrode provided on a surface thereof and electrically connected to the semiconductor integrated circuit;
Forming an element formed in the scribe region and a second electrode provided on the surface and electrically connected to the element in the scribe region;
Forming a first insulating film provided on the surface and having a first opening on the first electrode and a second opening on the second electrode;
Forming a resist film on the second opening;
Forming a second insulating film on the first insulating film;
The second insulating film is removed to form a third opening on the first opening, and a fourth opening is formed leaving the resist film on the second opening. The process of
Forming a bump electrically connected to the first electrode;
Removing the resist film on the second opening;
A method for producing a semiconductor wafer, comprising: 半導体集積回路と、
前記半導体集積回路を切断するスクライブ領域と、
を含む半導体ウエハを切断して形成される半導体チップの製造方法であって、
前記半導体集積回路と、その表面に設けられ前記半導体集積回路に電気的に接続した第１の電極と、
前記スクライブ領域に形成された素子と、前記表面に設けられ前記スクライブ領域の素子と電気的に接続した第２の電極を形成する工程、
前記表面に設けられ、前記第１の電極上に第１の開口部を有するとともに、前記第２の電極上に第２の開口部を有する第１の絶縁膜を形成する工程、
前記第２の開口部上にレジスト膜を形成する工程、
前記第１の絶縁膜上に第２の絶縁膜を形成する工程、
前記第２の絶縁膜を除去して、前記第１の開口部上に第３の開口部を形成するとともに、前記第２の開口部上に前記レジスト膜を残して第４の開口部を形成する工程、
前記第１の電極に電気的に接続するバンプを形成する工程、
前記第２の開口部上のレジスト膜を除去する工程、
前記スクライブ領域を切断して半導体チップを形成することを特徴とする半導体チップの製造方法。 A semiconductor integrated circuit;
A scribe region for cutting the semiconductor integrated circuit;
A method of manufacturing a semiconductor chip formed by cutting a semiconductor wafer including:
The semiconductor integrated circuit and a first electrode provided on a surface thereof and electrically connected to the semiconductor integrated circuit;
Forming an element formed in the scribe region and a second electrode provided on the surface and electrically connected to the element in the scribe region;
Forming a first insulating film provided on the surface and having a first opening on the first electrode and a second opening on the second electrode;
Forming a resist film on the second opening;
Forming a second insulating film on the first insulating film;
The second insulating film is removed to form a third opening on the first opening, and a fourth opening is formed leaving the resist film on the second opening. The process of
Forming a bump electrically connected to the first electrode;
Removing the resist film on the second opening;
A method of manufacturing a semiconductor chip, comprising cutting the scribe region to form a semiconductor chip.
JP2003359303A 2002-11-11 2003-10-20 Manufacturing method of semiconductor wafer and semiconductor chip Expired - Fee Related JP4238694B2 (en)

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JP2007149792A (en) * 2005-11-25 2007-06-14 Matsushita Electric Ind Co Ltd Semiconductor wafer and manufacturing method of semiconductor device
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DE102007057689A1 (en) * 2007-11-30 2009-06-04 Advanced Micro Devices, Inc., Sunnyvale Semiconductor device having a chip area, which is designed for an aluminum-free solder bump connection, and a test structure, which is designed for an aluminum-free wire connection
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