JP4544902B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

  The present invention relates to a chip size package type semiconductor device and a manufacturing method thereof.

  In recent years, a chip size package (CSP) has attracted attention as a three-dimensional mounting technique and as a new packaging technique. The chip size package refers to a small package having an outer dimension substantially the same as the outer dimension of a semiconductor chip.

  Conventionally, a BGA type semiconductor device is known as a kind of chip size package. In this BGA type semiconductor device, a plurality of ball-shaped conductive terminals made of a metal member such as solder are arranged in a lattice pattern on one main surface of a package, and electrically connected to a semiconductor chip mounted on the other surface of the package. Is connected to.

  When incorporating this BGA type semiconductor device into an electronic device, each conductive terminal is crimped to a wiring pattern on the printed circuit board, thereby electrically connecting the semiconductor chip and the external circuit mounted on the printed circuit board. Connected.

  Such a BGA type semiconductor device is provided with a larger number of conductive terminals than other CSP type semiconductor devices such as SOP (Small Outline Package) and QFP (Quad Flat Package) having lead pins protruding from the side. It has the advantage that it can be reduced in size. This BGA type semiconductor device has an application as an image sensor chip of a digital camera mounted on a mobile phone, for example.

  FIG. 9 shows a schematic configuration of a conventional BGA type semiconductor device, and FIG. 9A is a perspective view of the surface side of the BGA type semiconductor device. FIG. 9B is a perspective view of the back side of the BGA type semiconductor device.

  In this BGA type semiconductor device 101, a semiconductor chip 104 is sealed between first and second glass substrates 102 and 103 via epoxy resins 105a and 105b. A plurality of conductive terminals 106 are arranged in a grid pattern on one main surface of the second glass substrate 103, that is, on the back surface of the BGA type semiconductor device 101. The conductive terminal 106 is connected to the semiconductor chip 104 via the second wiring 110. The plurality of second wirings 110 are connected to the first wirings drawn from the inside of the semiconductor chip 104, respectively, and each conductive terminal 106 and the semiconductor chip 104 are electrically connected.

  The cross-sectional structure of the BGA type semiconductor device 101 will be described in more detail with reference to FIG. FIG. 10 shows a cross-sectional view of a BGA type semiconductor device 101 divided into individual chips along a dicing line.

  A first wiring 107 is provided on the insulating film 108 disposed on the surface of the semiconductor chip 104. The semiconductor chip 104 is bonded to the first glass substrate 102 by a resin layer 105a. Further, the back surface of the semiconductor chip 104 is bonded to the second glass substrate 103 by a resin layer 105b.

  One end of the first wiring 107 is connected to the second wiring 110. The second wiring 110 extends from one end of the first wiring 107 to the surface of the second glass substrate 103. A ball-shaped conductive terminal 106 is formed on the second wiring 110 extending on the second glass substrate 103.

The above-described technique is described in Patent Document 1 below, for example.
Japanese translation of PCT publication No. 2002-512436

  However, in the above-described BGA type semiconductor device 101, since the contact area between the first wiring 107 and the second wiring 110 is very small, there is a risk of disconnection at this contact portion. There was also a problem with the step coverage of the second wiring 110.

  Therefore, the present invention aims to improve the reliability of a chip size package type semiconductor device and a method for manufacturing the same.

The semiconductor device of the present invention has been made in view of the above problems, and is a pad electrode formed on the first main surface of the semiconductor chip and a support bonded to the first main surface of the semiconductor chip. A body, a via hole reaching the pad electrode from the second main surface of the semiconductor chip, and a groove having an opening diameter smaller than the via hole and formed in the second main surface of the semiconductor chip; An insulating film formed on the second main surface of the semiconductor chip including the side wall of the via hole and the inside of the groove, and the pad electrode exposed at the bottom of the via hole, and the insulating film And a wiring layer formed on the second main surface of the semiconductor chip so as to include the inside of the trench from the via hole.
Further, the semiconductor device of the present invention includes a pad electrode formed on the first main surface of the semiconductor chip, a via hole reaching the pad electrode from the second main surface of the semiconductor chip, and more than the via hole. A groove having a small opening diameter and formed on the second main surface of the semiconductor chip; and an insulating film formed on the second main surface of the semiconductor chip including the side wall of the via hole and the inside of the groove; The semiconductor chip is electrically connected to the pad electrode exposed at the bottom of the via hole and extends from the via hole to the second main surface of the semiconductor chip through the insulating film so as to include the inside of the trench. And a wiring layer.
Further, the groove is formed in a position corresponding to an end portion of the wiring layer in the second main surface of the semiconductor chip .

  In addition to the above structure, the semiconductor device of the present invention is formed on the protective layer having an opening that covers the wiring layer and exposes a part of the wiring layer, and the wiring layer that is exposed at the opening. And a conductive terminal.

According to another aspect of the present invention, there is provided a method for manufacturing a semiconductor device, comprising: preparing a semiconductor substrate on which a pad electrode is formed; and bonding a support to a first main surface of the semiconductor substrate; Forming a via hole reaching the pad electrode from the surface, and forming a groove having an opening diameter smaller than the via hole on the second main surface of the semiconductor substrate, a sidewall of the via hole, and the Forming an insulating film on the second main surface of the semiconductor chip including the inside of the trench; electrically connected to the pad electrode exposed at the bottom of the via hole; and from the via hole through the insulating film Forming a wiring layer extending on the second main surface of the semiconductor chip so as to include the inside of the groove .
According to another aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising: preparing a semiconductor substrate having a first main surface with a pad electrode formed therein; and forming a via hole reaching the pad electrode from the second main surface of the semiconductor substrate. And forming a groove having an opening diameter smaller than that of the via hole on the second main surface of the semiconductor substrate, and a second main surface of the semiconductor chip including the side wall of the via hole and the inside of the groove. Forming an insulating film on the surface; electrically connecting to the pad electrode exposed at the bottom of the via hole; and including the inside of the trench from the via hole through the insulating film. Forming a wiring layer extending on the two main surfaces.

In the method for manufacturing a semiconductor device according to the present invention, the step of forming the via hole and the groove includes a first opening and a second opening having a smaller opening diameter than the first opening. A step of forming a resist layer on the second main surface; and a step of etching the second main surface of the semiconductor substrate using the resist layer as a mask.
Furthermore, the groove is formed at a position corresponding to an end of the wiring layer in the second main surface of the semiconductor substrate.
Still further, the second opening provided in the resist layer is formed at a position corresponding to an end of the wiring layer in the second main surface of the semiconductor substrate.

  In addition to the above steps, the method for manufacturing a semiconductor device of the present invention includes a step of forming a protective layer covering the wiring layer after the step of forming the wiring layer, and a part of the wiring layer on the protective layer. And forming a conductive terminal on the wiring layer exposed through the opening, and dividing the semiconductor substrate into a plurality of semiconductor chips.

  According to the present invention, since the wiring layer from the pad electrode of the semiconductor chip to the conductive terminal on the back surface of the semiconductor chip is formed through the via hole, disconnection of the wiring layer and deterioration of the step coverage are prevented. be able to.

  Further, since a groove is formed in the second main surface, that is, the back surface of the semiconductor chip, an anchor (locking portion) for the insulating film interposed between the wiring layer and the back surface of the semiconductor chip. Become. As a result, the insulating film is prevented from being peeled off from the back surface of the semiconductor chip as much as possible due to stress or impact generated when the semiconductor chip as the main body is mounted on the printed circuit board.

  As a result, a highly reliable chip size package type semiconductor device can be obtained.

  Next, a method for manufacturing the semiconductor device according to the present embodiment will be described with reference to the drawings. The semiconductor device manufacturing method according to the present embodiment is performed, for example, as follows. 1 to 8 show a cross section of the semiconductor substrate 51, and show a cross section of a boundary between adjacent chips (that is, a dicing line DL) to be divided in a dicing process described later. 1 to 8, it is assumed that a device (not shown) is formed on the first main surface, that is, the surface of the semiconductor substrate 51.

  In the present embodiment, the device (not shown) is, for example, a CCD (Charge Coupled Device) image sensor. The device (not shown) is not limited to a CCD image sensor, and may be other light receiving elements or light emitting elements. The semiconductor substrate 51 is a semiconductor substrate made of, for example, silicon (Si), but is not limited thereto, and may be a semiconductor substrate made of another material such as GaAs, Ge, Si—Ge, or the like.

  First, as shown in FIG. 1, a pair of pad electrodes 53 are formed on the surface of a semiconductor substrate 51 via an interlayer insulating film 52 such as BPSG. The pair of pad electrodes 53 is made of a metal layer such as aluminum, an aluminum alloy, or copper, and has a thickness of about 1 μm, for example.

  Then, a passivation film (not shown) made of a silicon nitride film or the like is formed so as to cover the pair of pad electrodes 53, and a resin layer 54 made of, for example, an epoxy resin is applied on the passivation film.

  Then, the support body 55 is bonded to the surface of the semiconductor substrate 51 through the resin layer 54. The support 55 supports the semiconductor substrate 51 and has a function of protecting the semiconductor substrate 51.

  When a device (not shown) formed on the surface of the semiconductor substrate 51 is a CCD image sensor, light from the outside is received by the CCD on the surface of the semiconductor substrate 51 (to be divided into semiconductor chips 51A later). Since it is necessary, it is necessary to use a transparent substrate such as a glass substrate or a translucent substrate as the support 55. In the case where the device (not shown) does not receive light or emit light, not only the glass substrate but also an opaque substrate may be used. Further, for example, a substrate or a tape made of metal or organic material may be used.

  Then, in a state where the support body 55 is bonded, so-called back grinding is performed on the back surface of the semiconductor substrate 51 as necessary. Thereafter, the back surface of the back-ground semiconductor substrate 51 may be further etched. This etching is performed using, for example, an acid (for example, a mixed solution of HF and nitric acid) as an etchant. Thereby, the mechanical damage layer of the semiconductor substrate 51 generated by the back grinding is removed, and the characteristics of the device formed on the surface of the semiconductor substrate 51 are improved. The final thickness of the semiconductor substrate 51 can be appropriately selected according to the type of device.

  Next, as shown in FIG. 2, a first photoresist layer 56 a is selectively formed on the back surface of the semiconductor substrate 51. That is, the first photoresist layer 56a is formed to have the first opening 57r at a position corresponding to the pad electrode 53 and a desired number of second openings 58r at other positions. Yes. The second opening 58r is not particularly limited, but is preferably provided at a location corresponding to an end portion of the wiring layer 63 described later in the first photoresist layer 56a.

  Here, the opening diameter of the second opening 58r is formed smaller than the opening diameter of the first opening 57r. Furthermore, the ratio of the opening diameter of the first opening 57r and the opening diameter of the second opening 58r is preferably about 4 to 1, for example. For example, the opening diameter of the first opening 57r may be about 40 μm, and the opening diameter of the second opening 58r may be about 10 μm.

  Then, the semiconductor substrate 51 is etched using the first photoresist layer 56a as a mask. This etching is performed by dry etching using a predetermined etching gas. By this etching, a via hole 57 that penetrates the semiconductor substrate 51 is formed, and at the same time, a groove 58 that does not penetrate the semiconductor substrate 51 is formed.

  Here, the interlayer insulating film 52 is exposed at the bottom of the via hole 57, and the pad electrode 53 is in contact therewith. Further, when the second opening 58r of the first photoresist layer 56a is provided at a location corresponding to an end portion of the wiring layer 63 described later, the groove 58 is formed at the location. Further, the opening diameter of the groove 58 is smaller than the opening diameter of the via hole 57. Further, the groove 58 is extremely shallow compared to the via hole 57, that is, has a depth such that the bottom thereof is located in the vicinity of the back surface of the semiconductor substrate 51.

  Such a shallow groove 58 is formed by a so-called microloading effect during etching. That is, since the opening diameter of the second opening 58r provided in the first photoresist layer 56a, which is an etching mask, is smaller than the opening diameter of the first opening 57r, the second opening 58r The amount of etching gas that reaches the back surface of the semiconductor substrate 51 is smaller than the amount of etching gas that reaches the back surface of the semiconductor substrate 51 from the first opening 57r. Further, the amount of the residue at the time of etching released from the second opening 58r to the outside with the progress of the etching is compared with the amount of the residue at the time of etching released from the first opening 57r to the outside. And there are few.

  Therefore, the etching rate is different between the back surface of the semiconductor substrate 51 exposed through the first opening 57r and the back surface of the semiconductor substrate 51 exposed through the second opening 58r. Thereby, even when the progress of etching on the back surface of the semiconductor substrate 51 exposed through the first opening 57r penetrates the semiconductor substrate 51, the back surface of the semiconductor substrate 51 exposed through the second opening portion A shallow groove 58 having a bottom near the back surface is formed.

Next, as shown in FIG. 3, after removing the first photoresist layer 56a, the entire back surface of the semiconductor substrate including the inside of the via hole 57 and the groove 58 is covered so that, for example, 1.0 to An insulating film 59 having a thickness of about 1.5 μm is formed. The insulating film 59 is formed by, for example, a plasma CVD method, and a silicon oxide film (SiO ₂ film) or a silicon nitride film (SiN film) is suitable. Alternatively, the insulating film 59 may be formed using other materials as long as it functions as an insulating film.

Here, the groove 58 becomes an anchor, i.e. the locking part against the insulating film 59. Thereby, the adherence of the insulating film 59 to the back surface of the semiconductor substrate 51 is improved.

  Next, as shown in FIG. 4, a second photoresist layer 56 b is selectively formed on the back surface of the semiconductor substrate 51. That is, the second photoresist layer 56 b has an opening in the formation region of the via hole 57 and is formed on a part of the back surface of the semiconductor substrate 51 excluding the formation region of the via hole 57.

  Then, using the second photoresist layer 56b as a mask, the insulating film 59 and the interlayer insulating film 52 located at the bottom of the via hole 57 are selectively etched and removed. By this etching, the pad electrode 53 is exposed at the bottom of the via hole 57.

  Next, after removing the second photoresist layer 56b, a third photoresist layer 56c is selectively formed on a part of the insulating film 59 as shown in FIG. The region where the third photoresist layer 56c is formed is a region excluding the formation region of the wiring layer 63 described later. In FIG. 5, as an example, a third photoresist layer 56 c is formed in a region near the dicing line DL on the insulating film 59.

  Next, a barrier layer 61 of about 100 nm, for example, is formed on the back side of the semiconductor substrate 51 using the third photoresist layer 56c as a mask. Here, the barrier layer 61 is formed so as to be electrically connected to the pad electrode 53 exposed at the bottom of the via hole 57 and to cover the insulating film 59. The barrier layer 61 is made of, for example, titanium nitride (TiN). Alternatively, the barrier layer 61 may be made of a metal other than titanium nitride (TiN) as long as it functions as a barrier layer. For example, the barrier layer 61 may be composed of titanium tungsten (TiW), tantalum nitride (TaN), and a compound of the above metal.

  Next, a seed layer 62 of, for example, about 100 to 250 nm is formed on the back surface of the semiconductor substrate 51, that is, on the barrier layer 61 by any method such as sputtering, MOCVD, electroless plating, or a combination thereof. Form. The seed layer 62 is a metal layer that becomes a plating electrode used when a wiring layer 63 described later is formed by electrolytic plating. The seed layer 62 is made of, for example, copper (Cu).

  Here, in the via hole 57, the barrier layer 61 formed below the seed layer 62 prevents the copper (Cu) of the seed layer 62 from diffusing into the semiconductor substrate 51 through the insulating film 59. However, when the insulating film 59 is formed of a silicon nitride film (SiN film), the formation of the barrier layer 61 may be omitted because the silicon nitride film (SiN film) serves as a barrier against copper diffusion. .

  Next, as shown in FIG. 6, after removing the third photoresist layer 56c, the seed layer 62 is subjected to electrolytic plating of copper (Cu) of about 5 μm, for example. That is, the wiring layer 63 is formed by performing electrolytic plating of copper (Cu). The wiring layer 63 is formed to extend from the via hole 57 to the back surface of the semiconductor substrate 51, and is electrically connected to the pad electrode 53 via the seed layer 62 and the barrier layer 61.

  In FIG. 6, the seed layer 62 and the wiring layer 63 are not formed so as to be embedded in the groove 58, but actually, the seed layer 62 and the wiring layer 63 are embedded in the groove 58. Formed.

  In FIG. 6, the wiring layer 63 is formed by electrolytic plating of copper (Cu). However, the present invention is not limited to this. After tin (Sn) is formed by plating, copper (Cu) is further formed by plating. It may be formed by performing.

  Further, the wiring layer 63 may be formed by a method other than plating. For example, the wiring layer 63 may be formed by depositing copper (Cu) in the via hole 57 and the groove 58 by the CVD method or the MOCVD method. The wiring layer 63 may be formed by a sputtering method using a metal such as aluminum (Al).

  In FIGS. 5 and 6, after the third photoresist layer 56c is formed in a partial region on the back side of the semiconductor substrate 51, the barrier layer 61 and the seed layer 62 are formed using this as a mask, and wiring is further performed. Although the layer 63 is formed, this invention is not limited to this, For example, you may form those layers as follows. That is, although not shown, after a metal layer for a barrier layer, a seed layer, and a wiring layer is formed on the entire back surface of the semiconductor substrate 51 including the via hole 57 and the groove 58 via the insulating film 59, the metal A wiring layer may be formed by forming a photoresist layer on the layer and patterning by etching or the like using the photoresist layer as a mask. A desired number of wiring layers 63 can be formed in a desired region on the back surface of the semiconductor substrate 51.

  Next, as shown in FIG. 7, a protective layer 64 is formed on the back surface of the semiconductor substrate 51 so as to cover the wiring layer 63 and the insulating film 59. Then, a part of the protective layer 64 corresponding to the formation position of the wiring layer 63 and the dicing line DL is selectively removed by, for example, etching. Thus, an opening for exposing the insulating film 59 (or the semiconductor substrate 51) in the vicinity of the dicing line DL is provided, and an opening 65 for exposing the wiring layer 63 is provided.

  On the wiring layer 63 exposed at the opening 65, solder is printed by using a screen printing method, and the solder is reflowed by heat treatment to form the conductive terminal 68. Here, an electrode layer such as a Ni (nickel) layer 66 and an Au (gold) layer 67 may be formed on the wiring layer 63 exposed in the opening 65, and the conductive terminal 68 may be formed thereon.

  The conductive terminal 68 is not limited to solder, and may be formed using a lead-free low melting point metal material. Further, the conductive terminal 68 can be formed by freely selecting the number and the formation region by appropriately selecting the number of the openings 65 and the formation region. Instead of forming the conductive terminal 68 by solder, the conductive terminal may be formed by plating.

  Then, as shown in FIG. 8, a dicing process is performed along the dicing line DL to divide the semiconductor substrate 51 into a plurality of semiconductor chips 51A. In this dicing process, cutting is performed using a dicing blade. Thus, the semiconductor device according to this embodiment is completed.

  As described above, in this embodiment, the groove 58 formed on the back surface of the semiconductor chip 51A serves as an anchor, that is, a locking portion for the insulating film 59, the barrier layer 61, the seed layer 62, and the wiring layer 63. This improves the adherence of the insulating film 59 and the like to the back surface of the semiconductor chip 51A. Accordingly, the insulating film 59 and the like are prevented from being peeled off from the back surface of the semiconductor chip 51A as much as possible due to stress or impact generated when the semiconductor device is mounted on the printed board.

  In particular, when the groove 58 is formed at a position corresponding to the end portion of the wiring layer 63, the wiring layer 63 and the like (insulating film 59, barrier layer 61) with respect to the back surface of the semiconductor chip 51A in the vicinity of the end portion of the wiring layer 63. , Including the seed layer 62) is improved. Therefore, even when stress, impact, and the like generated when the semiconductor device is mounted on the printed circuit board are concentrated near the end of the wiring layer 63, the wiring layer 63 is prevented from being peeled off from the back surface of the semiconductor chip 51A as much as possible. Is done.

  When the trench 58 is formed in a region other than the region where the wiring layer 63 is formed (for example, in the vicinity of the dicing line DL), the trench 58 is formed so that the insulating film 59 and the protective layer 64 are embedded. In this case, the adherence of the insulating film 59 and the protective layer 64 to the back surface of the semiconductor chip 51A is improved. Therefore, the protective layer 64 is prevented from being peeled off from the back surface of the semiconductor chip 51A as much as possible due to stress or impact generated when the semiconductor device is mounted on the printed circuit board. Alternatively, in the dicing process, it is possible to suppress peeling of the protective layer 64 and the like in the vicinity of the dicing line DL as much as possible.

  As a result, it is possible to suppress damage to the wiring layer formed on the back surface of the semiconductor chip 51A through the insulating film 59 as much as possible, and a highly reliable chip size package type semiconductor device can be obtained.

  In the embodiment described above, the via hole 57 and the groove 58 are formed in the same process, but the present invention is not limited to this. That is, the via hole 57 and the groove 58 described above may be formed in different processes.

  Although the above-described present invention is applied to the BGA type semiconductor device in which the conductive terminal 68 is formed and the manufacturing method thereof, the present invention is not limited to this. That is, the present invention is also applicable to a semiconductor device in which a conductive terminal is not formed on the back surface of a semiconductor chip and a method for manufacturing the same as long as it has a wiring layer formed in a via hole penetrating the semiconductor chip. For example, the present invention is also applied to an LGA (Land Grid Array) type semiconductor device and a manufacturing method thereof.

It is sectional drawing explaining the manufacturing method of the semiconductor device which concerns on embodiment of this invention. It is sectional drawing explaining the manufacturing method of the semiconductor device which concerns on embodiment of this invention. It is sectional drawing explaining the manufacturing method of the semiconductor device which concerns on embodiment of this invention. It is sectional drawing explaining the manufacturing method of the semiconductor device which concerns on embodiment of this invention. It is sectional drawing explaining the manufacturing method of the semiconductor device which concerns on embodiment of this invention. It is sectional drawing explaining the manufacturing method of the semiconductor device which concerns on embodiment of this invention. It is sectional drawing explaining the manufacturing method of the semiconductor device which concerns on embodiment of this invention. It is sectional drawing explaining the manufacturing method of the semiconductor device which concerns on embodiment of this invention. It is a figure explaining the conventional semiconductor device. It is a figure explaining the conventional semiconductor device.

Claims (10)

A pad electrode formed on the first main surface of the semiconductor chip;
A support bonded to the first main surface of the semiconductor chip;
A via hole reaching the pad electrode from the second main surface of the semiconductor chip;
A groove having an opening diameter smaller than that of the via hole and formed in the second main surface of the semiconductor chip;
An insulating film formed on a second main surface of the semiconductor chip including the side wall of the via hole and the inside of the groove;
Formed on the second main surface of the semiconductor chip so as to be electrically connected to the pad electrode exposed at the bottom of the via hole and to include the inside of the trench from the via hole via the insulating film And a wiring layer. A pad electrode formed on the first main surface of the semiconductor chip;
A via hole reaching the pad electrode from the second main surface of the semiconductor chip;
A groove having an opening diameter smaller than that of the via hole and formed in the second main surface of the semiconductor chip;
An insulating film formed on a second main surface of the semiconductor chip including the side wall of the via hole and the inside of the groove;
Formed on the second main surface of the semiconductor chip so as to be electrically connected to the pad electrode exposed at the bottom of the via hole and to include the inside of the trench from the via hole via the insulating film And a wiring layer.   3. The semiconductor device according to claim 1, wherein the groove is formed at a position corresponding to an end of the wiring layer in the second main surface of the semiconductor chip. A protective layer that covers the wiring layer and has an opening that exposes a portion of the wiring layer;
The semiconductor device according to claim 1, further comprising: a conductive terminal formed on the wiring layer exposed at the opening. Preparing a semiconductor substrate on which a pad electrode is formed, and bonding a support to the first main surface of the semiconductor substrate;
Forming a via hole reaching the pad electrode from the second main surface of the semiconductor substrate and forming a groove having an opening diameter smaller than the via hole on the second main surface of the semiconductor substrate; When,
Forming an insulating film on the second main surface of the semiconductor chip including the side wall of the via hole and the inside of the groove;
A wiring layer electrically connected to the pad electrode exposed at the bottom of the via hole and extending from the via hole to the second main surface of the semiconductor chip so as to include the inside of the trench through the insulating film is formed. And a process for manufacturing the semiconductor device. Preparing a semiconductor substrate having a pad electrode formed on the first main surface;
Forming a via hole reaching the pad electrode from the second main surface of the semiconductor substrate and forming a groove having an opening diameter smaller than the via hole on the second main surface of the semiconductor substrate; When,
Forming an insulating film on the second main surface of the semiconductor chip including the side wall of the via hole and the inside of the groove;
A wiring layer electrically connected to the pad electrode exposed at the bottom of the via hole and extending from the via hole to the second main surface of the semiconductor chip so as to include the inside of the trench through the insulating film is formed. And a process for manufacturing the semiconductor device. The step of forming the via hole and the groove includes
Forming a resist layer provided with a first opening and a second opening having an opening diameter smaller than the first opening on the second main surface;
The method for manufacturing a semiconductor device according to claim 5, further comprising: etching the second main surface of the semiconductor substrate using the resist layer as a mask.   The semiconductor device according to claim 5, wherein the groove is formed at a position corresponding to an end portion of the wiring layer in the second main surface of the semiconductor substrate. Manufacturing method.   6. The second opening provided in the resist layer is formed at a position corresponding to an end of the wiring layer in the second main surface of the semiconductor substrate. A method for manufacturing a semiconductor device according to claim 8. After the step of forming the wiring layer,
Forming a protective layer covering the wiring layer;
Forming an opening exposing a part of the wiring layer in a part of the protective layer, and forming a conductive terminal on the wiring layer exposed in the opening;
The method for manufacturing a semiconductor device according to claim 5, further comprising a step of dividing the semiconductor substrate into a plurality of semiconductor chips.

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