JP2003347471A - Semiconductor device and method for manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method for manufacturing a semiconductor device capable of reducing the bending of a wafer posterior to cure or hard-bake at the time of forming a resin layer. <P>SOLUTION: This semiconductor device 20A including a semiconductor wafer 21 and a resin layer 22 covering at least a part of the semiconductor wafer is configured by forming a bending reducing groove 23 crossing a part or whole part of the thickness direction of the resin layer, or reaching from the resin layer to a part of the thickness direction of the semiconductor wafer. <P>COPYRIGHT: (C)2004,JPO

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device including a semiconductor wafer and a resin layer covering at least a part of the semiconductor wafer, and more particularly, a part or all of the resin layer in a thickness direction, or The present invention relates to a semiconductor device capable of preventing a warp of a wafer by curing or hard baking by forming a warp suppressing groove extending from a resin layer to a part in a thickness direction of the semiconductor wafer, and a method of manufacturing the same.

[0002]

2. Description of the Related Art Conventionally, as a semiconductor package structure, for example, a package in which a semiconductor chip is sealed with a resin (so-called Dual Inline package or Quad Flat package).
In this case, a peripheral terminal arrangement type in which metal lead electrodes are arranged on a side surface around a resin package was mainly used. On the other hand, as a semiconductor package structure that has spread rapidly in recent years, for example, a so-called ball grid array (BGA) technology called a CSP (chip scale package), in which electrodes are arranged on a flat surface of a package on a plane. By adopting a semiconductor chip with the same projection area with the same number of electrode terminals,
There is a package structure that allows high-density mounting on an electronic circuit board with a smaller area than before. A chip scale package (hereinafter, referred to as CSP) structure in which the area of the package is substantially equal to the area of the semiconductor chip, and the above-mentioned BGA
The development of the electrode arrangement structure has greatly contributed to the reduction in size and weight of electronic devices. In the CSP, a silicon wafer on which a circuit is formed is cut, and individual semiconductor chips are individually subjected to a packaging process to complete a package.

[0003] In these semiconductor package technologies,
A manufacturing method generally called a “wafer level CSP” is known. In this wafer level CSP, an insulating layer, a rewiring layer, a sealing layer, etc. are formed on a silicon wafer,
Form solder bumps. FIG. 1 is a cross-sectional view showing a configuration example of a conventional CSP. FIG. 1 shows a state of being mounted on a printed circuit board, and in the following description, the vertical relationship is reversed from that of FIG. In this CSP, a plurality of electrodes, for example, Al pads 2 are formed on the front surface of a wafer 1. Further, a passivation film covering the Al pad 2, for example, a SiN layer 3 and a polyimide layer 4 are formed on the entire surface of the wafer 1. Via holes are formed in the SiN layer 3 and the polyimide layer 4 to reach the Al pad 2 from the surface. The conductor layer 5 is buried in the via hole. Further, a redistribution layer 6 connected to the conductor layer 5 is formed on the polyimide layer 4. The rewiring layer 6 is made of, for example, Cu. Further, a sealing resin layer 7 covering the rewiring layer 6 is provided on the entire surface of the polyimide layer 4. Inside the sealing resin layer 7, a Cu post 8 is formed as a metal post extending from the surface to the redistribution layer 6. A barrier metal layer 9 is formed on the Cu post 8, and a solder bump 10 is formed on the barrier metal layer 9.

[0004] In the final step, a semiconductor chip having a package structure can be obtained by cutting the wafer into a predetermined chip size. Since these circuits are laminated on the entire surface of the wafer and the wafer is diced in the final process, the size of the cut chip itself becomes a packaged semiconductor chip and has a minimum projected area with respect to the mounting substrate. Can be obtained. A feature of the method of manufacturing a wafer-level CSP is that all the members constituting the package are processed in the shape of a wafer. That is, the insulating layer, the rewiring layer, the sealing resin layer, the solder bumps, and the like are all formed by handling the wafer. For example, formation of a resin layer for electrical insulation and sealing for protecting a chip and its components can be obtained by forming a resin on the entire surface of a silicon wafer on which a large number of semiconductor circuits are formed. Such a resin layer is generally formed using, for example, a photosensitive or non-photosensitive liquid resin, a polyimide resin or an epoxy resin formed into a dry film.

[0005]

When a photosensitive or non-photosensitive liquid resin or dry film is formed on a wafer and cured or hard-baked, the resin 12
2 tends to warp the entire wafer 11 as shown in FIG. This phenomenon is caused by curing or hard baking a liquid resin or a dry film formed on the wafer 11, thereby causing the resin 12 to contract in volume while being in close contact with the substrate. The warpage of the wafer strongly depends on the characteristics of the resin used and the thickness of the formed resin, but in some cases, the warp A of the wafer reaches 2 mm,
Since vacuum suction cannot be performed, handling cannot be performed, and alignment cannot be performed in the next process.
There is a drawback in that problems such as cracking of the resin and breakage of the wafer occur.

The present invention has been made in view of the above circumstances. In a semiconductor device including a semiconductor wafer and a resin layer covering at least a part of the semiconductor wafer, the present invention relates to a method of curing a resin layer and forming a wafer after hard baking. The purpose is to provide a method capable of reducing warpage.

[0007]

In order to achieve the above object, the present invention provides a semiconductor device including a semiconductor wafer and a resin layer covering at least a part of the semiconductor wafer, in a thickness direction of the resin layer. Provided is a semiconductor device, wherein a warp suppressing groove is provided that partially or entirely, or extends from a resin layer to a part in a thickness direction of a semiconductor wafer.

The present invention also relates to a method of manufacturing a semiconductor device including a semiconductor wafer and a resin layer covering at least a part of the semiconductor wafer, wherein a liquid resin layer or a dry film layer for forming the resin layer is formed on the semiconductor wafer. Formed into a laminate, and then reach a part or all of the thickness of the liquid resin layer or the dry film layer of the laminate, or reach from the liquid resin layer or the dry film layer to a part of the thickness of the semiconductor wafer. A method for manufacturing a semiconductor device, comprising: forming a warp suppressing groove; and curing or hard-baking the laminate to form a resin layer.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS In the present invention, a "semiconductor device"
Means various semiconductor devices having a structure in which a resin layer is bonded to at least a part of the surface of a semiconductor wafer, for example, various semiconductor packages such as a CSP manufactured by a wafer level CSP, an electronic circuit element including the semiconductor package, and an electronic device. Including equipment.

A semiconductor device according to the present invention has a structure in which a resin layer is bonded to at least a part of the surface of a semiconductor wafer. A feature is provided in which a warp suppressing groove reaching a part in the thickness direction is provided. Further, a method of manufacturing a semiconductor device according to the present invention is a method of manufacturing a semiconductor device including a semiconductor wafer and a resin layer covering at least a part of the semiconductor wafer, wherein a liquid resin layer or a dry film layer is formed on the semiconductor wafer. A laminate, and then a part or all of the liquid resin layer or dry film layer of the laminate in the thickness direction, or a warp suppressing groove extending from the liquid resin layer or dry film layer to a part of the thickness direction of the semiconductor wafer And then curing or hard-baking the laminate to form a resin layer.

In the present invention, the resin layer to be bonded to the semiconductor wafer is, for example, a photosensitive or non-photosensitive liquid resin (UV curable resin, visible light curable resin, infrared light curable resin, heat curable resin). Mold resin), a polyimide resin or an epoxy resin formed into a dry film. The liquid resin can be formed into a uniform thickness on a semiconductor wafer by, for example, a spin coating method.

FIG. 3 is a view showing a first embodiment of a semiconductor device according to the present invention.
The insulating resin layer 22 is formed on the surface
2, the warp suppressing groove 23 is formed by cutting out a part of the insulating resin layer 22 in the thickness direction. An electrode 24 is provided on the wafer 21 so as to be in contact with a circuit in the wafer 21.
Has been removed.

The warp suppressing groove 23 may be formed by any of the following. (1) A groove is formed only in the scribe line. (2) A groove is formed only in a chip. (3) Grooves are formed in scribe lines and chips. The pattern for forming the warp suppressing groove 23 is not particularly limited, as long as the wafer does not warp due to cure (hardening) or hard baking for forming the resin layer or an effect of significantly reducing the warp can be obtained. FIG. 4 (a)
4D illustrate line patterns of the warp suppressing grooves 23 formed in the chip, and FIG. 4A illustrates a case where lines are formed at substantially equal intervals along the length and width of the chip. (B) shows a case including a line along a diagonal line of the chip and a line orthogonal to the diagonal line. (C) shows a case where a plurality of concentric lines are formed from the center of the chip. (D) shows a case where a plurality of circular lines are formed in a chip.

Semiconductor device 2 having warpage suppressing groove 23
In order to manufacture OA, for example, the following steps 1 to 3 can be sequentially performed. 1. A positive photosensitive liquid resin or dry film is applied and formed on the wafer 21 to a thickness of 5 to 200 μm. Examples of the resin used include a polyimide resin, an epoxy resin, and an acrylic resin. 2. The pattern of the warp suppressing groove 23 is exposed and developed in addition to the pattern of the resin layer. 3. Cure or hard bake is performed using a heating device such as an oven.

The semiconductor device 20A includes an insulating resin layer 22
A warp suppressing groove 23 is provided to prevent warpage of the wafer 21 due to cure or hard bake processing when the resin layer 22 is formed. Defects such as poor properties, inability to perform alignment in the next step, and damage to the wafer can be avoided. Furthermore, stress applied to the solder bumps after mounting on the board can be reduced, and dimensional stability can be improved to obtain a high quality product.

FIG. 5 is a view showing a second embodiment of the semiconductor device according to the present invention.
It is configured to include the same components as those of the embodiment.
Insulating resin layer 22 of semiconductor device 20B according to the present embodiment
Is formed using an exposure mask on which both the formation pattern of the insulating resin layer 22 itself and the formation pattern of the warp suppressing groove 23 are drawn. The present embodiment is characterized in that the dimension of the pattern width of the warp suppressing groove 23 is made smaller than the resolution of the photolithography and a part of the insulating resin layer 22 is left, and the liquid resin is applied irrespective of a positive type or a negative type. it can. As in the first embodiment, the semiconductor device 20B according to the present embodiment has poor warpability because vacuum suction cannot be performed by providing the warp suppressing groove 23 in the insulating resin layer 22, and alignment cannot be performed in the next step.
Defects such as breakage of the wafer can be avoided.
Furthermore, stress applied to the solder bumps after mounting on the board can be reduced, and dimensional stability can be improved to obtain a high quality product.

FIG. 6 is a view showing a third embodiment of the semiconductor device of the present invention. The semiconductor device 20C of the present embodiment includes:
An insulating resin layer 22 is provided on the wafer 21, and a sealing resin layer 25 is provided on the insulating resin layer 22. In addition, the electrode 24 provided on the wafer 21 is disposed between the insulating resin layer 22 and the sealing resin layer 25 in contact with the electrode 24,
A conductive layer 2 partially exposed through the sealing resin layer 25;
6 enables electrical connection. In the present embodiment, the warp suppressing groove 23 is formed in the sealing resin layer 25.

In this embodiment, the warp suppressing groove 23 is
The semiconductor device 2 of the present embodiment is formed by using a photosensitive or non-photosensitive resin by laser exposure and dicing.
0C is manufactured by the following steps 1 to 4, for example. 1. A liquid resin or a dry film of a photosensitive or non-photosensitive resin is applied to the wafer 21 to form a film. Examples of the type of the resin include a polyimide resin, an epoxy resin, and an acrylic resin. 2. If necessary, the resin layer is patterned. 3. Perform a cure or hard bake. 4. A groove is formed by laser or dicing. Steps 3 and 4 may be interchanged.

In the semiconductor device 20C of this embodiment, a warp suppressing groove 23 is provided in the sealing resin layer 25, and the wafer 2 is formed by curing or hard baking when forming the resin layers 22, 25.
1, the warpage is reduced.
Defects at the time of warpage, that is, poor handling because vacuum suction is not possible, alignment cannot be performed in the next process,
Defects such as breakage of the wafer can be avoided.
Furthermore, stress applied to the solder bumps after mounting on the board can be reduced, and dimensional stability can be improved to obtain a high quality product.

FIG. 7 is a view showing a fourth embodiment of the semiconductor device of the present invention. The semiconductor device 20D of the present embodiment includes:
The third embodiment has the same components as those of the third embodiment. The semiconductor device 20D of the present embodiment is characterized in that a warp suppressing groove 23 that penetrates a resin layer (the insulating resin layer 22 and the sealing resin layer 25) and reaches the upper portion of the wafer 21 is formed. The formation of the warp suppressing groove 23 can be performed by manufacturing each component other than the groove of the semiconductor device 20D and then forming the warp suppressing groove 23 reaching the upper portion of the wafer 21 by, for example, dicing. The semiconductor device 20D of the present embodiment can obtain the same effects as those of the semiconductor devices according to the above-described embodiments.

FIG. 8 is a view showing a fifth embodiment of the semiconductor device of the present invention. The semiconductor device 20E of the present embodiment includes:
An insulating resin layer 22 is provided on both sides of the wafer 21, and a rewiring 28 connected to the electrode 24 is provided.
1 and a through electrode 27 disposed in a hole penetrating the insulating resin layer 22 on both sides, and a rewiring 28
Are connected, and a solder bump 30 is formed at the end on the back surface side of the through electrode 27 via a barrier metal layer 29. Then, the wafer 2 is formed on the back surface of the semiconductor device 20E by penetrating the insulating resin layer 22 on the back surface.
1 is provided.

In the present embodiment, in the semiconductor device 20E having the structure in which the solder bumps 30 are present on the back surface of the wafer 21 using the through electrodes 27, the back surface insulating resin layer 22 and the back surface of the wafer 21 are warped using laser processing or dicing processing. By providing the suppression groove 23, the warp of the wafer 21 can be reduced, and the stress applied to the solder bump 30 during mounting on the substrate can be reduced.

[0023]

EXAMPLE 1 A semiconductor device 20A having the structure shown in FIG. 3 was manufactured by sequentially performing the following steps 1 to 4. In this manufacturing method, a resin layer pattern and an exposure mask for the groove pattern are separately prepared and separately exposed,
The warp suppressing groove 23 is formed by giving a difference in the exposure amount.
Applicable to positive photosensitive resin. 1. 30μ thick photosensitive polyimide on φ6 inch wafer
m is formed. 2. The pattern of the insulating resin layer was exposed at a dose of 500 mJ / cm ^2.
Exposure. 3. The pattern of the warp suppressing groove is exposed at a dose of 100 mJ / cm ^2.
Exposure. 4. After the development, curing is performed at 300 ° C. for 1 hour using an oven.

By performing the above steps 1-4, FIG.
As shown in (1), the warp suppressing groove 23 could be provided in the insulating resin layer 22. FIG. 9 shows the result of measuring the warpage of the semiconductor device 20A in which the warp suppressing groove 23 is formed and the semiconductor device in which the warp suppressing groove 23 is not formed. The edge of the wafer of the semiconductor device in which the groove was not formed is about 1.2 mm higher than the center of the wafer (see the broken line labeled "no groove" in FIG. 9). On the other hand, the edge of the wafer 21 of the semiconductor device 20A provided with the warp suppressing groove 23 is 0.1 mm thicker than the center of the wafer 21.
The height was only slightly higher (see the solid line labeled “with groove” in FIG. 9), and it was demonstrated that the warpage of the wafer 21 can be reduced by applying the present invention.

(Example 2) By sequentially performing the following steps 1 to 3, a semiconductor device 20B having a structure shown in FIG. 5 was manufactured. In this manufacturing method, an exposure mask on which both a resin layer pattern and a warp suppressing groove pattern are drawn is used. The feature is that the width of the warp suppressing groove pattern width is made smaller than the resolution of photolithography and a part of the insulating resin layer 22 is left, and it can be applied to both positive and negative types. 1. 80mm thick photosensitive epoxy resin on φ8 inch wafer
The film is formed to have a thickness of μm. 2. Exposure is performed at a dose of 2000 mJ / cm ² using a mask on which a pattern of the insulating resin layer and a pattern of the groove are drawn. The mask size of the groove is 10 μm, and when the photosensitive epoxy used in this experiment is formed in a thickness of 50 μm or more, the resin cannot be separated so that a U-shaped groove can be formed. 3. After the development, hard baking is performed at 180 ° C. for 30 minutes using a hot air circulation path.

By performing the above-mentioned steps 1-3, FIG.
As shown in (1), the warp suppressing groove 23 could be provided in the insulating resin layer 22. Semiconductor device 2 having warpage suppressing groove 23 formed therein
As a result of measuring the warpage of the wafer 21 of 0B and the wafer that was not formed, the edge of the wafer where the groove was not formed was about 3.9 mm higher than the center of the wafer. On the other hand, the wafer 21 of the semiconductor device 20B provided with the warp suppressing groove 23 is only about 0.8 mm higher, and the warp of the wafer can be reduced by applying the present invention.

Example 3 In forming a sealing resin layer,
By sequentially performing the following steps 1 to 4, a semiconductor device 20C having the structure shown in FIG. 6 was manufactured. 1. A dry film of a non-photosensitive acrylic resin having a thickness of 100 μm is laminated on a φ6 inch wafer. 2. Hard bake at 150 ° C. for 90 minutes in an oven. 3. The conductive layer connected to the solder bump is exposed by plasma etching. 4. Groove processing is performed using a YAG laser.

By performing the above steps 1-4, FIG.
As shown in (1), the warp suppressing groove 23 could be provided in the sealing resin layer 25. Semiconductor device 2 having warpage suppressing groove 23 formed therein
As a result of measuring the warpage of the wafer 21 at 0C and the wafer that was not formed, the edge of the wafer where the groove was not formed was about 0.9 mm higher than the center of the wafer. In contrast,
Wafer 21 of semiconductor device 20C provided with warpage suppressing groove 23
Is only about 0.1 mm higher, and by applying the present invention, it has become possible to reduce the warpage of the wafer.

Example 4 In the formation of the sealing resin layer,
By sequentially performing the following steps 1 to 4, a semiconductor device 20D having a structure shown in FIG. 7 was manufactured. A liquid photosensitive epoxy resin is formed on a φ6 inch wafer having a thickness of 1.625 μm so as to have a thickness of 50 μm. 2. Patterning is performed by photolithography. 3. Hard baking is performed at 200 ° C. for 45 minutes using a clean oven. 4. Dicing on the scribe line. At this time, the wafer is also cut at a depth of 200 μm.

By performing the above steps 1-4, FIG.
As shown in (1), grooves can be provided after resin sealing, and the warpage of the wafer can be reduced. As a result of measuring the warpage of the wafer on which the groove was formed and the wafer on which the groove was not formed, the edge of the wafer on which no groove was formed was approximately 2.2 mm higher than the center of the wafer. On the other hand, the wafer provided with the groove has a diameter of 0.1 mm.
The height was only about 05 mm, and it was possible to reduce the warpage of the wafer by applying the present invention.

[0031]

According to the present invention, a warp suppressing groove is provided in a resin layer of a semiconductor device to suppress warpage due to curing or hard baking during the formation of the resin layer.
Warpage is reduced, and defects at the time of warpage, that is, drawbacks such as poor handling due to vacuum suction, inability to align in the next step, and damage to the wafer can be avoided. Furthermore, stress applied to the solder bumps after mounting on the board can be reduced, and dimensional stability can be improved to obtain a high quality product.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view illustrating a conventional CSP.

FIG. 2 is a cross-sectional view illustrating a semiconductor device in which warpage has occurred after curing or hard baking.

FIG. 3 is a sectional view showing a first embodiment of the semiconductor device of the present invention.

FIG. 4 is a plan view illustrating an arrangement pattern of a warp suppressing groove.

FIG. 5 is a sectional view showing a second embodiment of the semiconductor device of the present invention.

FIG. 6 is a sectional view showing a third embodiment of the semiconductor device of the present invention.

FIG. 7 is a sectional view showing a fourth embodiment of the semiconductor device of the present invention.

FIG. 8 is a sectional view showing a fifth embodiment of the semiconductor device of the present invention.

FIG. 9 is a graph showing the results of the example according to the present invention and comparing the degree of warpage depending on the presence or absence of a warp suppressing groove.

[Explanation of symbols]

20A to E: Semiconductor device, 21: Wafer (semiconductor wafer), 22: Insulating resin layer (resin layer), 23: Warpage suppressing groove, 24: Electrode, 25: Sealing resin layer (resin layer), 26:
Conductive layer, 27: through electrode, 28: rewiring layer, 29: barrier metal layer, 30: solder bump.

Claims (2)

[Claims] In a semiconductor device including a semiconductor wafer and a resin layer covering at least a part of the semiconductor wafer, a part or all in a thickness direction of the resin layer, or a part of the resin layer in a thickness direction of the semiconductor wafer. A semiconductor device having a warp suppressing groove that reaches a part thereof. 2. A method of manufacturing a semiconductor device including a semiconductor wafer and a resin layer covering at least a part of the semiconductor wafer, wherein a liquid resin layer or a dry film layer is formed on the semiconductor wafer to form a laminate, and then the laminate is formed. Forming a warp suppressing groove extending partially or entirely in the thickness direction of the liquid resin layer or the dry film layer of the body, or from the liquid resin layer or the dry film layer to a part in the thickness direction of the semiconductor wafer; A method for manufacturing a semiconductor device, comprising forming a resin layer by curing or hard baking a body.