JP2011054653A - Manufacturing method of semiconductor device - Google Patents

Manufacturing method of semiconductor device Download PDF

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Publication number
JP2011054653A
JP2011054653A JP2009200381A JP2009200381A JP2011054653A JP 2011054653 A JP2011054653 A JP 2011054653A JP 2009200381 A JP2009200381 A JP 2009200381A JP 2009200381 A JP2009200381 A JP 2009200381A JP 2011054653 A JP2011054653 A JP 2011054653A
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Prior art keywords
sealing resin
manufacturing
semiconductor device
wiring
wiring mother
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Japanese (ja)
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Takashi Oba
高志 大馬
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Micron Memory Japan Ltd
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Elpida Memory Inc
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Priority to JP2009200381A priority Critical patent/JP2011054653A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3511—Warping

Abstract

<P>PROBLEM TO BE SOLVED: To provide a manufacturing method of a semiconductor device whose warpage amount is small and in which a wiring mother substrate can be enlarged, even if the difference in the thermal expansion coefficients between sealing resin and a wiring mother substrate is large, and which has inexpensive manufacturing cost and has less individual differences of warpages, in a manufacturing method of the semiconductor device for manufacturing the sealing resin in the wiring mother substrate by a mold manufacturing method. <P>SOLUTION: The manufacturing method includes a process for forming the sealing resin 21 on the wiring mother substrate 1 by the mold manufacturing method, a process for cutting the sealing resin along a dicing line arranged on the wiring mother substrate and a process for thermally-curing the sealing resin, after the resin is cut. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

本発明は、半導体装置の製造方法に関する。   The present invention relates to a method for manufacturing a semiconductor device.

近年、デジタル機器の小型化、高速化、高機能化に伴い、ＢＧＡ（ボールグリッドアレイ）型半導体装置を例とする半導体装置の高密度実装化の要望が強まり、１つのパッケージに複数の半導体チップを積層するＭＣＰ（マルチチップパッケージ）化や、複数の薄型パッケージを積層するＰｏＰ（パッケージオンパッケージ）化が進んでいる。   In recent years, with the miniaturization, high speed, and high functionality of digital devices, there is an increasing demand for high density mounting of semiconductor devices such as BGA (ball grid array) type semiconductor devices, and a plurality of semiconductor chips in one package. The MCP (multi-chip package) for stacking layers and the PoP (package on package) for stacking a plurality of thin packages are progressing.

このＢＧＡ型またはＬＧＡ（ランドグリッドアレイ）型半導体装置は、複数の製品形成部を整列して配置している配線母基板を利用し、製品形成部ごとに半導体チップを搭載、ボンディングし、配線母基板全体を一括して封止樹脂でモールドした後に、製品単位ごとに切断して個別分離して製造されてきた。   This BGA type or LGA (land grid array) type semiconductor device uses a wiring mother board in which a plurality of product forming portions are arranged and arranged, a semiconductor chip is mounted and bonded to each product forming portion, and a wiring mother is provided. After the entire substrate is molded with a sealing resin all at once, it has been manufactured by cutting into individual product units and separating them individually.

なお、特許文献１及び特許文献２には、半導体ウェハの反りを対策する技術が開示されている。また、特許文献３には、封止体に溝を形成する技術が、特許文献４には、封止体にスリットを形成する技術が開示されている。また、特許文献５には、パッケージ形状別に金型を準備し、金型に凸部を設け、モールド部に溝を形成する技術が開示されている。   Patent Documents 1 and 2 disclose a technique for taking measures against warping of a semiconductor wafer. Patent Document 3 discloses a technique for forming a groove in the sealing body, and Patent Document 4 discloses a technique for forming a slit in the sealing body. Patent Document 5 discloses a technique for preparing a mold for each package shape, providing a protrusion on the mold, and forming a groove in the mold part.

特開２００３−２１８１４４号公報JP 2003-218144 A 特開２００３−２１８２７５号公報JP 2003-218275 A 特開２００５−３３３０４４号公報JP 2005-333044 A 特開２００８−１７７４４０号公報JP 2008-177440 A 特開２００２−１１０７１８号公報JP 2002-110718 A

ところで、パッケージの薄型化に伴い、従来は問題にならなかった半導体装置の反りの影響を無視することができなくなった。特に、本願発明者らは、以下に説明する問題点があることを明らかにした。   By the way, with the thinning of the package, the influence of the warp of the semiconductor device, which has not been a problem in the past, can no longer be ignored. In particular, the inventors of the present application have revealed that there are problems described below.

すなわち、配線母基板の上側に位置する封止樹脂が、例えば熱膨張係数ａ１のエポキシ素材からなり、配線母基板１が、例えば熱膨張係数ａ２のポリイミド素材から形成されているとする。この場合、ａ１がａ２より大きいと、封止樹脂を加熱硬化して常温に冷却する際に、上側の封止樹脂が下側の配線母基板よりも大きく縮むことになる。 That is, the sealing resin on the upper side of the wiring mother board, for example, from an epoxy material thermal expansion coefficient of a 1, a wiring mother substrate 1 is, for example, formed from a polyimide material thermal expansion coefficient a 2. In this case, the a 1 is greater than a 2, upon cooling to room temperature by heating and curing the sealing resin, the upper sealing resin so that shrinks larger than the wiring substrate of the lower.

その結果、半導体装置単体としては、中央部が下側に凹み、周縁部が上側に反るマイナス反りとなる。そして、このマイナス反りが大きいと、半導体装置を外部基板に実装したり、他の半導体装置と積層してＰｏＰ化したりする場合に、周縁部において実装はがれ不良が生じるという不都合があった。   As a result, the semiconductor device itself becomes a negative warp in which the central portion is recessed downward and the peripheral portion warps upward. If this negative warpage is large, there is a disadvantage that a mounting device peels off at the peripheral portion when the semiconductor device is mounted on an external substrate or is stacked with another semiconductor device to form PoP.

特に、配線母基板１全体で考えると、図１０（ａ）ないし（ｃ）に示すように、配線母基板１の周縁領域５ではセンターライン６側からの硬化収縮力が累積されるため、封止樹脂２の硬化収縮力α１と配線母基板１の硬化収縮力β１の差が大きくなり、反り発生量が大きくなる。また、配線母基板１のセンターライン６周辺の中央領域４では、封止樹脂２の硬化収縮力α２と配線母基板１の硬化収縮力β２の差は小さいが、逆にプラス反りになるという不都合もあった。 In particular, considering the entire wiring mother board 1, as shown in FIGS. 10 (a) to 10 (c), the hardening shrinkage force from the center line 6 side is accumulated in the peripheral region 5 of the wiring mother board 1, so that sealing is performed. difference cure shrinkage force beta 1 of cure shrinkage force alpha 1 and the wiring substrate 1 of the sealing resin 2 is increased, warpage amount increases. Further, in the central region 4 of the center line 6 near the wiring mother substrate 1, but the difference in cure shrinkage force beta 2 of hardening shrinkage force alpha 2 and the wiring mother substrate 1 of the sealing resin 2 is small, a plus warp in the opposite There was also an inconvenience.

以上より、配線母基板１を大型化すると、周縁領域５で形成される半導体装置３ｂの反りが大きくなるという不都合があった。その結果、例えばＰｏＰ製品などのように反りの製造許容範囲が厳しい製品を製造する際には、大型化した配線母基板１を用いることができず、原価を低減することができないという問題があった。
なお、引用文献１ないし引用文献５に開示された技術は、いずれも上記課題を解決するものではない。 From the above, when the wiring mother board 1 is enlarged, there is a disadvantage that warpage of the semiconductor device 3b formed in the peripheral region 5 increases. As a result, for example, when manufacturing a product having a severe manufacturing tolerance of warp such as a PoP product, the large-sized wiring mother board 1 cannot be used, and the cost cannot be reduced. It was.
Note that none of the techniques disclosed in the cited documents 1 to 5 solves the above-described problem.

そこで、本発明は以下の構成を採用した。
本発明の半導体装置の製造方法は、配線基板に封止樹脂をモールド工法によって形成する工程と、前記配線基板に設けられたダイシングラインに沿って前記封止樹脂を切断する工程と、切断した後に前記封止樹脂を加熱硬化させることで封止体を形成する工程と、を含むことを特徴とする。 Therefore, the present invention employs the following configuration.
The method for manufacturing a semiconductor device of the present invention includes a step of forming a sealing resin on a wiring substrate by a molding method, a step of cutting the sealing resin along a dicing line provided on the wiring substrate, and after cutting Forming a sealing body by heat-curing the sealing resin.

本発明では、封止樹脂をモールド工法によって形成した後に、封止樹脂をダイシングラインに沿って切断してから加熱硬化させている。これにより、封止樹脂を加熱硬化して常温に冷却させる際に、硬化収縮力が蓄積されることがなくなり、封止樹脂と配線基板の熱膨張係数の差が大きくても、配線基板の周縁領域の反り量が小さくなる。その結果、配線基板を大型化させることが可能となり、製造原価が低く、かつ、反りの個体差が少ない半導体装置を製造することができる。   In the present invention, after the sealing resin is formed by the molding method, the sealing resin is cut along the dicing line and then cured by heating. As a result, when the sealing resin is heat-cured and cooled to room temperature, the curing shrinkage force is not accumulated, and even if the difference in thermal expansion coefficient between the sealing resin and the wiring board is large, the peripheral edge of the wiring board The amount of warpage of the region is reduced. As a result, it is possible to increase the size of the wiring board, and it is possible to manufacture a semiconductor device with a low manufacturing cost and a small individual difference in warpage.

図１は、本発明の第１の実施形態の半導体装置の製造方法を示す断面工程図である。FIG. 1 is a cross-sectional process diagram illustrating a method for manufacturing a semiconductor device according to a first embodiment of the present invention. 図２は、本発明の第１の実施形態に用いられる配線母基板を示す平面図である。FIG. 2 is a plan view showing a wiring mother board used in the first embodiment of the present invention. 図３は、本発明の第１の実施形態に用いられる配線母基板を示す平面図である。FIG. 3 is a plan view showing a wiring mother board used in the first embodiment of the present invention. 図４は、本発明の第１の実施形態の半導体装置の製造方法の一部を示す断面工程図である。FIG. 4 is a cross-sectional process diagram illustrating a part of the semiconductor device manufacturing method according to the first embodiment of the present invention. 図５は、本発明の第１の実施形態の半導体装置の製造フローを示す図である。FIG. 5 is a diagram showing a manufacturing flow of the semiconductor device according to the first embodiment of the present invention. 図６は、本発明の第１の実施形態の半導体装置の製造方法によって製造される半導体装置を示す断面図である。FIG. 6 is a cross-sectional view showing a semiconductor device manufactured by the method for manufacturing a semiconductor device according to the first embodiment of the present invention. 図７（ａ）は、本発明の第２の実施形態の半導体装置の製造方法に用いられる配線母基板を示す平面図であり、図７（ｂ）は、本発明の第２の実施形態の半導体装置の製造方法の一部を示す断面工程図である。FIG. 7A is a plan view showing a wiring mother board used in the method for manufacturing a semiconductor device of the second embodiment of the present invention, and FIG. 7B is a diagram of the second embodiment of the present invention. It is sectional process drawing which shows a part of manufacturing method of a semiconductor device. 図８は、本発明の第３の実施形態の半導体装置の製造方法を示す断面工程図である。FIG. 8 is a cross-sectional process diagram illustrating a method for manufacturing a semiconductor device according to a third embodiment of the present invention. 図９は、本発明の第３の実施形態の半導体装置の製造フローを示す図である。FIG. 9 is a diagram showing a manufacturing flow of the semiconductor device according to the third embodiment of the present invention. 図１０は、従来の半導体装置の製造方法の一部を示す断面工程図である。FIG. 10 is a sectional process diagram showing a part of a conventional method for manufacturing a semiconductor device.

［第１の実施形態］
以下、本発明の第１の実施形態である半導体装置の製造方法について、図面を参照して説明する。なお、以下の説明において、封止樹脂とは加熱硬化する前のものをさし、封止体とは加熱硬化した後のものをさす。 [First Embodiment]
A method for manufacturing a semiconductor device according to a first embodiment of the present invention will be described below with reference to the drawings. In the following description, the sealing resin refers to the one before heat curing, and the sealing body refers to the one after heat curing.

まず、本実施形態の半導体装置の製造方法によって製造される半導体装置の一例について説明する。
図６に示すように、半導体装置１１は、ＢＧＡ（Ｂａｌｌ Ｇｒｉｄ Ａｒｒａｙ）型半導体装置であり、一面１２ａに複数の接続パッド１３を有し、他面１２ｂに接続パッド１３と電気的に接続された複数のランド１４を有する配線基板１２と、配線基板１２の一面１２ａに搭載された半導体チップ１５と、配線基板１２に設けられた接続パッド１３と半導体チップ１５に設けられた電極パッド１６を接続するワイヤ１７と、少なくとも半導体チップ１５とワイヤ１７とを覆う絶縁性樹脂からなる封止体１８と、ランド１４上に設けられた半田ボール等の外部端子１９と、を有した構成となっている。 First, an example of a semiconductor device manufactured by the semiconductor device manufacturing method of the present embodiment will be described.
As shown in FIG. 6, the semiconductor device 11 is a BGA (Ball Grid Array) type semiconductor device, which has a plurality of connection pads 13 on one surface 12a and is electrically connected to the connection pads 13 on the other surface 12b. A wiring board 12 having a plurality of lands 14, a semiconductor chip 15 mounted on one surface 12 a of the wiring board 12, a connection pad 13 provided on the wiring board 12, and an electrode pad 16 provided on the semiconductor chip 15 are connected. The structure includes a wire 17, a sealing body 18 made of an insulating resin that covers at least the semiconductor chip 15 and the wire 17, and an external terminal 19 such as a solder ball provided on the land 14.

なお、本実施形態で製造される半導体装置１１は、配線母基板１を利用して製造されるものであればよく、上記構造のものに限らない。例えば半導体チップを複数搭載するマルチチップ構造、ワイヤボンディングの代わりにバンプにより接続する構造、外部接続用半田ボールがないＬＧＡ型構造であっても構わない。   The semiconductor device 11 manufactured in the present embodiment is not limited to the above structure as long as it is manufactured using the wiring motherboard 1. For example, a multi-chip structure in which a plurality of semiconductor chips are mounted, a structure in which connection is made by bumps instead of wire bonding, or an LGA type structure having no external connection solder balls may be used.

次に、本実施形態の半導体装置の製造方法について説明する。
まず、図２に示すような配線母基板１を準備する。配線母基板１は、ＭＡＰ（Ｍｏｌｄ Ａｒｒａｙ Ｐｒｏｃｅｓｓ）方式で処理されるものであり、平面視略矩形状の板状で、複数の製品形成部２０がマトリクス状に配置されている。
製品形成部２０は、各製品形成部２０間に設けられたダイシングライン２２に沿って切断分離した後に、配線基板１２となる部位である。 Next, a method for manufacturing the semiconductor device of this embodiment will be described.
First, a wiring mother board 1 as shown in FIG. 2 is prepared. The wiring mother board 1 is processed by a MAP (Mold Array Process) method, and has a substantially rectangular plate shape in plan view, and a plurality of product forming portions 20 are arranged in a matrix.
The product forming portion 20 is a portion that becomes the wiring substrate 12 after being cut and separated along the dicing line 22 provided between the product forming portions 20.

また、配線母基板１は、例えば厚さ０．２５ｍｍのガラスエポキシ基板からなっており、配線母基板１の両面には、所定の配線が設けられ、その配線の外側の一部に図示略の絶縁膜、例えばソルダーレジストが積層された構成となっている。   The wiring mother board 1 is made of, for example, a glass epoxy board having a thickness of 0.25 mm. Predetermined wiring is provided on both surfaces of the wiring mother board 1, and an unillustrated portion is provided on a part of the outer side of the wiring. An insulating film such as a solder resist is laminated.

配線母基板１の製品形成部２０の一面の配線のソルダーレジストから露出された部位には、それぞれ複数の接続パッド１３（図６参照）が配置されている。
また、製品形成部２０の他面の配線のソルダーレジストから露出された部位には、それぞれ複数のランド１４（図６参照）が格子状に配置されている。
そして、接続パッド１３とこれに対応するランド１４は、内部配線８（図６参照）によりそれぞれ電気的に接続されている。 A plurality of connection pads 13 (see FIG. 6) are arranged in the portions exposed from the solder resist of the wiring on one surface of the product forming portion 20 of the wiring motherboard 1.
In addition, a plurality of lands 14 (see FIG. 6) are arranged in a grid pattern at portions exposed from the solder resist of the wiring on the other surface of the product forming unit 20.
And the connection pad 13 and the land 14 corresponding to this are electrically connected by the internal wiring 8 (refer FIG. 6), respectively.

また、マトリクス状に配置された製品形成部２０の周囲の領域には、枠部２３が設けられている。枠部２３には所定の間隔で位置決め孔２４が設けられ、搬送・位置決めが可能に構成されている。   Further, a frame portion 23 is provided in a region around the product forming portion 20 arranged in a matrix. Positioning holes 24 are provided in the frame portion 23 at a predetermined interval so that conveyance and positioning can be performed.

次に、配線母基板１のそれぞれの製品形成部２０の一面の略中央位置に、それぞれ半導体チップ１５（図６参照）を、例えば絶縁性の接着材あるいはＤＡＦ（Ｄｉｅ Ａｔｔａｃｈｅｄ Ｆｉｌｍ）等の固定部材９（図６参照）を介して接着固定する。   Next, a semiconductor chip 15 (see FIG. 6) is placed at a substantially central position on one surface of each product forming part 20 of the wiring mother board 1, for example, an insulating adhesive or a fixing member such as DAF (Die Attached Film). 9 (see FIG. 6).

半導体チップ１５を製品形成部２０に接着固定した後は、半導体チップ１５の一面１５ａに形成された電極パッド１６（図６参照）と、配線母基板１の接続パッド１３とを導電性のワイヤ１７（図６参照）により結線する。   After the semiconductor chip 15 is bonded and fixed to the product forming portion 20, the electrode pads 16 (see FIG. 6) formed on the one surface 15 a of the semiconductor chip 15 and the connection pads 13 of the wiring mother board 1 are connected to the conductive wires 17. (See FIG. 6).

次に、配線母基板１上に封止樹脂２１をモールド工法によって形成する。モールド工法としては、従来知られているものであれば、いずれの方法でも構わない。例えば、配線母基板１を圧縮モールド装置の上型に吸着保持させ、圧縮モールド装置の下型に液状の封止樹脂を供給し、上型を下降させることで、配線母基板を下型に形成された液状の封止樹脂に浸漬し、上型と下型により加熱圧縮することで形成する方法を用いても構わない。
以上のようにして、図１（ａ）及び図３に示すように、モールド工法によって封止樹脂２１が形成された配線母基板１が得られる。なお、図１，図４（ａ），図７（ｂ）及び図８は、図３のＡ−Ａ’間断面図である。 Next, a sealing resin 21 is formed on the wiring mother board 1 by a molding method. As a mold method, any method known in the art may be used. For example, the wiring mother board 1 is sucked and held on the upper mold of the compression molding apparatus, liquid sealing resin is supplied to the lower mold of the compression molding apparatus, and the upper mold is lowered to form the wiring mother board on the lower mold. A method of forming by immersing in the liquid sealing resin thus formed and heating and compressing with an upper mold and a lower mold may be used.
As described above, as shown in FIGS. 1A and 3, the wiring mother board 1 on which the sealing resin 21 is formed by the molding method is obtained. 1, FIG. 4 (a), FIG. 7 (b) and FIG. 8 are cross-sectional views taken along the line AA 'in FIG.

次に、封止樹脂２１を加熱硬化させない状態で、配線母基板１に設けられた全てのダイシングライン２２に沿って、封止樹脂２１を切断する。この際、図１（ｂ），図４（ａ）及び（ｂ）に示すように、封止樹脂２１には、切断溝２５が形成される。
切断溝２５の深さは、封止樹脂２１の厚さｌと同一の深さとすることが最も好ましいが、切断溝２５に伴う強度低下や破断の影響を考慮して、反り軽減効果が見込まれる範囲で切断溝２５の深さを、封止樹脂２１の厚さｌよりも浅く設定しても構わない。例えば、図４（ｂ）に示すように、封止樹脂２１の厚さｌの５０％程度の深さｍとして設計しても構わない。
なお、この工程においては、配線母基板１を個別分離しないので、配線母基板１を切断しないようにする。 Next, the sealing resin 21 is cut along all the dicing lines 22 provided on the wiring mother board 1 in a state where the sealing resin 21 is not heated and cured. At this time, as shown in FIGS. 1B, 4 </ b> A, and 4 </ b> B, a cutting groove 25 is formed in the sealing resin 21.
The depth of the cutting groove 25 is most preferably set to the same depth as the thickness l of the sealing resin 21, but a warp reduction effect is expected in consideration of the strength reduction and breakage caused by the cutting groove 25. The depth of the cutting groove 25 may be set to be shallower than the thickness l of the sealing resin 21 in the range. For example, as illustrated in FIG. 4B, the depth m may be designed to be about 50% of the thickness l of the sealing resin 21.
In this step, since the wiring mother board 1 is not individually separated, the wiring mother board 1 is not cut.

また、切断する設備は、後の配線母基板１のダイシング工程で利用するダイシング装置及びダイシングブレード２６を利用することが好ましい。
これにより、追加の設備費用を抑制することができる。また、同一のダイシングブレード２６によって切断するので、配線母基板１のダイシング工程を経た際に、封止樹脂２１と配線母基板１の切断面（側面）に段差が発生するのを抑制することができる。 Moreover, it is preferable to use the dicing apparatus and dicing blade 26 which are utilized in the dicing process of the wiring mother board 1 later as equipment for cutting.
Thereby, an additional installation expense can be suppressed. Further, since the cutting is performed by the same dicing blade 26, it is possible to suppress the occurrence of a step on the cutting surface (side surface) of the sealing resin 21 and the wiring mother board 1 when the wiring mother board 1 is subjected to the dicing process. it can.

次に、図１（ｃ）に示すように、封止樹脂２１を切断した後に、封止樹脂２１を加熱硬化させることで、封止体２７を形成する。具体的には、配線母基板１を、例えば１７５℃で５時間加熱保持し、封止樹脂２１を完全に硬化させてから、加熱を解除して常温に冷却する（キュアベーク）。   Next, as illustrated in FIG. 1C, after the sealing resin 21 is cut, the sealing body 27 is formed by heating and curing the sealing resin 21. Specifically, the wiring mother board 1 is heated and held at, for example, 175 ° C. for 5 hours to completely cure the sealing resin 21, and then the heating is released to cool to room temperature (cure baking).

配線母基板１に封止体２７を形成した後は、図１（ｄ）に示すように、ボールマウント工程（半田ボール付け）に移行する。すなわち、配線母基板１の製品形成部２０の他面に格子状に配置された複数のランド１４上に、導電性の半田ボールを搭載し、外部端子１９となるバンプ電極を形成する。   After the sealing body 27 is formed on the wiring mother board 1, as shown in FIG. 1D, the process proceeds to a ball mounting process (solder ball attachment). That is, conductive solder balls are mounted on the plurality of lands 14 arranged in a grid pattern on the other surface of the product forming portion 20 of the wiring mother board 1, and bump electrodes serving as the external terminals 19 are formed.

具体的には、配線母基板１上のランド１４の配置に合わせて複数の吸着孔が形成されたボールマウントツール２８を用いて、半田ボールを吸着孔に吸着保持し、保持された半田ボールにフラックスを転写形成し、配線母基板１のランド１４上に一括搭載する。そして、全ての製品形成部２０への半田ボール搭載後、配線母基板１をリフローすることで、半田ボールを固着させ、外部端子１９となるバンプ電極を形成する。   Specifically, using the ball mount tool 28 in which a plurality of suction holes are formed in accordance with the arrangement of the lands 14 on the wiring mother board 1, the solder balls are sucked and held in the suction holes, and the held solder balls are The flux is transferred and mounted on the land 14 of the wiring motherboard 1 at a time. Then, after mounting the solder balls on all the product forming portions 20, the wiring mother board 1 is reflowed to fix the solder balls and form the bump electrodes to be the external terminals 19.

その後、図１（ｅ）及び（ｆ）に示すように、半田ボールの搭載された配線母基板１は、ダイシング工程（個片切断）に移行され、配線母基板１をダイシングライン２２で切断し、製品形成部２０毎に分離する。
具体的には、配線母基板１の封止体２７側をダイシングテープ２９に接着し、ダイシングテープ２９によって配線母基板１を支持する。その後、配線母基板１を図示略のダイシング装置のダイシングブレード２６により、縦横にダイシングライン２２に沿って切断し、製品形成部２０毎に切断分離する。切断分離後、ダイシングテープ２９からピックアップすることで、半導体装置１１が得られる。 Thereafter, as shown in FIGS. 1E and 1F, the wiring mother board 1 on which the solder balls are mounted is transferred to a dicing process (individual piece cutting), and the wiring mother board 1 is cut by a dicing line 22. The product forming unit 20 is separated.
Specifically, the sealing body 27 side of the wiring mother board 1 is bonded to a dicing tape 29, and the wiring mother board 1 is supported by the dicing tape 29. Thereafter, the wiring mother board 1 is cut along the dicing lines 22 vertically and horizontally by a dicing blade 26 of a dicing apparatus (not shown), and is cut and separated for each product forming portion 20. After cutting and separating, the semiconductor device 11 is obtained by picking up from the dicing tape 29.

本実施形態の半導体装置の製造方法は、封止樹脂２１をモールド工法によって配線母基板１上に形成した後に、封止樹脂２１をダイシングライン２２に沿って切断してから加熱硬化させて封止体２７を形成している。
すなわち、図５に示すように、従来封止樹脂２１をモールド工法によって形成した直後に、封止樹脂２１を加熱硬化して常温に冷却し（キュアベーク）、その後にボールマウント工程（半田ボール付け）及びダイシング工程（個片切断）を行っていた。これに対し、本実施形態では、封止樹脂２１をモールド工法によって形成した後、硬化していない状態の封止樹脂２１をダイシングライン２２に沿って切断し、その後に封止樹脂２１を加熱硬化して常温に冷却し、ボールマウント工程及びダイシング工程を行っている。 In the manufacturing method of the semiconductor device according to the present embodiment, after the sealing resin 21 is formed on the wiring mother board 1 by the molding method, the sealing resin 21 is cut along the dicing line 22 and then cured by heat curing. A body 27 is formed.
That is, as shown in FIG. 5, immediately after the conventional sealing resin 21 is formed by a molding method, the sealing resin 21 is heated and cured and cooled to room temperature (curing bake), and then a ball mounting step (solder ball attachment). And a dicing process (cutting pieces). On the other hand, in this embodiment, after the sealing resin 21 is formed by the molding method, the uncured sealing resin 21 is cut along the dicing line 22, and then the sealing resin 21 is heated and cured. Then, it is cooled to room temperature, and a ball mounting process and a dicing process are performed.

これにより、加熱硬化して常温に冷却させる際には、封止樹脂２１は個別化されており、図４（ａ）に示すように、封止樹脂２１の硬化収縮力αが配線母基板１の周縁領域に蓄積されることがなくなる。その結果、封止樹脂２１と配線母基板１の熱膨張係数の差が大きくても、配線母基板１の周縁領域の反り量が小さくなる。これにより、配線母基板１を大型化させることが可能となり、製造原価が低く、かつ、反りの固体差が少ない半導体装置１１を製造することができる。
なお、封止樹脂２１を加熱硬化して常温に冷却する際には、封止樹脂２１は個別化されているので、配線母基板１の中央領域でプラス反りになることも防ぐことができる。 As a result, when the resin is heat-cured and cooled to room temperature, the sealing resin 21 is individualized, and as shown in FIG. Is not accumulated in the peripheral area. As a result, even if the difference in thermal expansion coefficient between the sealing resin 21 and the wiring mother board 1 is large, the amount of warpage of the peripheral region of the wiring mother board 1 is reduced. As a result, the wiring mother board 1 can be enlarged, and the semiconductor device 11 can be manufactured with a low manufacturing cost and a small solid difference in warpage.
When the sealing resin 21 is cured by heating and cooled to room temperature, since the sealing resin 21 is individualized, it is possible to prevent the central region of the wiring mother board 1 from being positively warped.

また、本実施形態の半導体装置の製造方法は、新たな素材や製造治具を用いず、標準的な部材と製造装置によって製造することができるので、製造コストを低減することができる。   Moreover, since the manufacturing method of the semiconductor device of this embodiment can be manufactured with a standard member and a manufacturing apparatus without using a new raw material and a manufacturing jig, manufacturing cost can be reduced.

［第２の実施形態］
次に、本発明の第２の実施形態である半導体装置の製造方法について説明する。本実施形態の半導体装置の製造方法は、第１の実施形態の変形例であり、同様な部分については適宜説明を省略する。 [Second Embodiment]
Next, a method for manufacturing a semiconductor device according to the second embodiment of the present invention will be described. The manufacturing method of the semiconductor device according to the present embodiment is a modification of the first embodiment, and description of similar parts will be omitted as appropriate.

まず、本実施形態でも第１の実施形態と同様に配線母基板１を準備し、製品形成部２０に半導体チップ１５を搭載し、半導体チップ１５に形成された電極パッド１６と配線母基板１の接続パッド１３を導電性のワイヤ１７によって結線する。その後、配線母基板１に封止樹脂３１（図７参照）をモールド工法によって形成する。   First, also in the present embodiment, the wiring mother board 1 is prepared as in the first embodiment, the semiconductor chip 15 is mounted on the product forming unit 20, and the electrode pads 16 formed on the semiconductor chip 15 and the wiring mother board 1 are formed. The connection pad 13 is connected by a conductive wire 17. Thereafter, a sealing resin 31 (see FIG. 7) is formed on the wiring mother board 1 by a molding method.

次に、封止樹脂３１を加熱硬化させない状態で、配線母基板１に設けられたダイシングライン２２に沿って、封止樹脂３１を切断する。この際、第１の実施形態では、配線母基板１に設けられた全てのダイシングライン２２の全てに沿って切断したが、本実施形態では、ダイシングライン２２の一部に沿って切断する。
例えば、図７（ａ）に示すように、ダイシングライン２２の１ラインまたは２ライン間隔に間引いて切断する。すなわち、ダイシングライン２２には、封止樹脂３１を加熱硬化させない状態で切断する切断ライン３３と、加熱硬化させた後に切断する切断ライン３４とがあることになる。なお、切断するダイシングライン２２を間引く間隔は、用いる封止樹脂３１や配線母基板１の熱膨張係数等の関係から、適宜設定すればよい。 Next, the sealing resin 31 is cut along the dicing line 22 provided on the wiring motherboard 1 in a state where the sealing resin 31 is not cured by heating. At this time, in the first embodiment, cutting is performed along all of the dicing lines 22 provided on the wiring motherboard 1, but in this embodiment, cutting is performed along a part of the dicing lines 22.
For example, as shown in FIG. 7A, the dicing line 22 is cut by being thinned at intervals of one line or two lines. That is, the dicing line 22 includes a cutting line 33 that cuts the sealing resin 31 without being heated and cured, and a cutting line 34 that is cut after being heated and cured. In addition, what is necessary is just to set suitably the space | interval which thins out the dicing line 22 to cut | disconnect from the relationship of the thermal expansion coefficient of the sealing resin 31 to be used, the wiring motherboard 1, etc.

その後は、第１の実施形態と同様に、封止樹脂３１を切断した後に、封止樹脂３１を加熱硬化させることで、封止体３２を形成し、ボールマウント工程及びダイシング工程を行うことで、半導体装置１１が得られる。   Thereafter, as in the first embodiment, after cutting the sealing resin 31, the sealing resin 31 is heated and cured to form the sealing body 32, and the ball mounting process and the dicing process are performed. Thus, the semiconductor device 11 is obtained.

本実施形態の半導体装置の製造方法も、第１の実施形態と同様に、封止樹脂３１を加熱硬化して常温に冷却する際には、封止樹脂３１は個別化されており、硬化収縮力が蓄積されることがなくなる。その結果、封止樹脂３１と配線母基板１の熱膨張係数の差が大きくても、配線母基板１の周縁領域の反り量が小さくなる。これにより、配線母基板１を大型化させることが可能となり、製造原価が低く、かつ、反りの固体差が少ない半導体装置１１を製造することができる。
また、新たな素材や製造治具を用いることなく、標準的な部材と製造装置によって、製造することができるので、製造コストを低減することができる。 As in the first embodiment, the method for manufacturing the semiconductor device according to the present embodiment is such that when the sealing resin 31 is heated and cured and cooled to room temperature, the sealing resin 31 is individualized and cured and contracted. Power is no longer accumulated. As a result, even if the difference in thermal expansion coefficient between the sealing resin 31 and the wiring mother board 1 is large, the amount of warpage of the peripheral region of the wiring mother board 1 is reduced. As a result, the wiring mother board 1 can be enlarged, and the semiconductor device 11 can be manufactured with a low manufacturing cost and a small solid difference in warpage.
Moreover, since it can manufacture with a standard member and a manufacturing apparatus, without using a new raw material and a manufacturing jig, manufacturing cost can be reduced.

また、第１の実施形態と比較すると、加熱硬化されていない封止樹脂３１を切断する際の作業時間を低減することができる。加えて、第１の実施形態と比較すると、ダイシングブレード２６の使用時間も低減するので、ダイシングブレード２６のメンテナンス間隔を長くすることができる。   Moreover, compared with 1st Embodiment, the working time at the time of cut | disconnecting the sealing resin 31 which is not heat-hardened can be reduced. In addition, since the use time of the dicing blade 26 is reduced as compared with the first embodiment, the maintenance interval of the dicing blade 26 can be lengthened.

［第３の実施形態］
次に、本発明の第３の実施形態である半導体装置の製造方法について説明する。本実施形態の半導体装置の製造方法は、ダイシング工程を経てから封止樹脂を加熱硬化させている点で第１の実施形態と異なっており、第１の実施形態と同様な部分については、適宜説明を省略する。 [Third Embodiment]
Next, a method for manufacturing a semiconductor device according to the third embodiment of the present invention will be described. The manufacturing method of the semiconductor device of this embodiment is different from that of the first embodiment in that the sealing resin is heat-cured after passing through the dicing process, and the same parts as those of the first embodiment are appropriately selected. Description is omitted.

まず、本実施形態でも第１の実施形態と同様に配線母基板１を準備し、製品形成部２０に半導体チップ１５を搭載し、半導体チップ１５に形成された電極パッド１６と配線母基板１の接続パッド１３を導電性のワイヤ１７によって結線する。
次に、図８（ａ）に示すように、配線母基板１に封止樹脂４１をモールド工法によって形成する。 First, also in the present embodiment, the wiring mother board 1 is prepared as in the first embodiment, the semiconductor chip 15 is mounted on the product forming unit 20, and the electrode pads 16 formed on the semiconductor chip 15 and the wiring mother board 1 are formed. The connection pad 13 is connected by a conductive wire 17.
Next, as shown in FIG. 8A, a sealing resin 41 is formed on the wiring motherboard 1 by a molding method.

その後、図８（ｂ）に示すように、封止樹脂４１を加熱硬化させない状態で、ボールマウント工程に移行する。すなわち、配線母基板１の製品形成部２０の他面に配置された複数のランド１４上に、導電性の半田ボールを搭載し、外部端子１９となるバンプ電極を形成する。   Thereafter, as shown in FIG. 8B, the process proceeds to the ball mounting step in a state where the sealing resin 41 is not cured by heating. That is, conductive solder balls are mounted on the plurality of lands 14 arranged on the other surface of the product forming portion 20 of the wiring mother board 1, and bump electrodes serving as the external terminals 19 are formed.

配線母基板１に半田ボールを搭載した後は、図８（ｃ）及び（ｄ）に示すように、ダイシング工程に移行し、配線母基板１をダイシングライン２２で切断することで、製品形成部２０ごとに分離する。
具体的には、配線母基板１の封止樹脂４１側をダイシングテープ２９に接着し、ダイシングテープ２９によって配線母基板１を支持する。その後、配線母基板１を図示略のダイシング装置のダイシングブレード２６により、縦横にダイシングライン２２に沿って切断し、製品形成部２０ごとに切断分離する。切断分離後、ダイシングテープ２８からピックアップする。 After mounting the solder balls on the wiring mother board 1, as shown in FIGS. 8C and 8D, the process proceeds to a dicing process, and the wiring mother board 1 is cut by the dicing line 22, thereby forming the product forming portion. Separate every 20th.
Specifically, the sealing resin 41 side of the wiring mother board 1 is bonded to the dicing tape 29, and the wiring mother board 1 is supported by the dicing tape 29. Thereafter, the wiring mother board 1 is cut along the dicing lines 22 vertically and horizontally by a dicing blade 26 of a dicing device (not shown), and is cut and separated for each product forming portion 20. After cutting and separating, the pickup is picked up from the dicing tape 28.

その後、図８（ｅ）に示すように、ダイシング工程を経て個別分離した後に、封止樹脂４１を加熱硬化して常温に冷却する。具体的には、個別化された封止樹脂４１が加熱硬化される前の半導体装置１１を図示略の搭載治具に搭載する。その後、例えば１７５℃で５時間の加熱保持を実施し、加熱を解除して常温に冷却する。これにより、封止樹脂４１は完全に硬化収縮され、封止体４２が形成される。
以上のようにして、半導体装置１１が得られる。 Thereafter, as shown in FIG. 8E, after the individual separation through the dicing process, the sealing resin 41 is heat-cured and cooled to room temperature. Specifically, the semiconductor device 11 before the individualized sealing resin 41 is heat-cured is mounted on a mounting jig (not shown). After that, for example, heating and holding at 175 ° C. for 5 hours is performed, heating is released, and cooling is performed to room temperature. Thereby, the sealing resin 41 is completely cured and shrunk, and the sealing body 42 is formed.
The semiconductor device 11 is obtained as described above.

本実施形態の半導体装置の製造方法は、封止樹脂４１をモールド工法によって配線母基板１上に形成した後に、加熱硬化させない状態で、配線母基板１を製品形成部２０ごとに切断分離し、その後に封止樹脂４１を加熱硬化して常温に冷却することで、封止体４２を形成している。
すなわち、図９に示すように、従来封止樹脂４１をモールド工法によって形成した直後に、封止樹脂４１を加熱硬化して常温に冷却し、その後にボールマウント工程及びダイシング工程を行っていた。これに対し、本実施形態では、封止樹脂４１をモールド工法によって形成した後、封止樹脂４１を加熱硬化させない状態でボールマウント工程及びダイシング工程を行い、その後に封止樹脂４１を加熱硬化して常温に冷却することで、封止体４２を形成している。 The manufacturing method of the semiconductor device according to the present embodiment cuts and separates the wiring mother board 1 for each product forming unit 20 in a state where the sealing resin 41 is not cured by heating after the sealing resin 41 is formed on the wiring mother board 1 by a molding method. Then, the sealing body 41 is formed by heating and curing the sealing resin 41 and cooling to room temperature.
That is, as shown in FIG. 9, immediately after forming the conventional sealing resin 41 by a molding method, the sealing resin 41 is heated and cured and cooled to room temperature, and then a ball mounting process and a dicing process are performed. On the other hand, in this embodiment, after the sealing resin 41 is formed by the molding method, the ball mounting process and the dicing process are performed in a state where the sealing resin 41 is not heated and cured, and then the sealing resin 41 is heated and cured. Then, the sealing body 42 is formed by cooling to room temperature.

これにより、加熱硬化して冷却する際には、封止樹脂４１は個別化されており、硬化収縮力が蓄積されることがなくなる。その結果、封止樹脂４１と配線母基板１の熱膨張係数の差が大きくても、配線母基板１の周縁領域の反り量が小さくなる。これにより、配線母基板１を大型化させることが可能となり、製造原価が低く、かつ、反りの固体差が少ない半導体装置１１を製造することができる。   As a result, when the resin is heat-cured and cooled, the sealing resin 41 is individualized so that the curing shrinkage force is not accumulated. As a result, even if the difference in thermal expansion coefficient between the sealing resin 41 and the wiring mother board 1 is large, the amount of warpage of the peripheral region of the wiring mother board 1 is small. As a result, the wiring mother board 1 can be enlarged, and the semiconductor device 11 can be manufactured with a low manufacturing cost and a small solid difference in warpage.

また、本実施形態の半導体装置の製造方法は、第１の実施形態と異なり、封止樹脂４１に切断溝を形成する作業がなく、標準的な半導体装置１１の製造工程を入れ替えただけなので、総製造時間の増加を防止することができる。また、切断作業は１回のみなので、半導体装置１１の切断面（側面）に段差は発生しない。   In addition, unlike the first embodiment, the method for manufacturing a semiconductor device according to the present embodiment has no work of forming a cutting groove in the sealing resin 41, and only the manufacturing process of the standard semiconductor device 11 is replaced. An increase in total manufacturing time can be prevented. Further, since the cutting operation is performed only once, no step is generated on the cut surface (side surface) of the semiconductor device 11.

また、新たな素材や製造治具を用いることなく、標準的な部材と製造装置によって、製造することができるので、製造コストを低減することができる。   Moreover, since it can manufacture with a standard member and a manufacturing apparatus, without using a new raw material and a manufacturing jig, manufacturing cost can be reduced.

なお、本実施形態では、封止樹脂４１を加熱硬化させない状態で、複数の工程にわたって作業を行うため、柔軟案状態の封止樹脂４１の損傷や異物付着などの外形不良が増加しないように監視・対応する必要がある。   In the present embodiment, since the work is performed over a plurality of steps in a state where the sealing resin 41 is not heat-cured, monitoring is performed so as not to increase external defects such as damage to the flexible sealing resin 41 and adhesion of foreign substances.・ It is necessary to respond.

以上、本発明を実施形態に基づき説明したが、本発明は、上記実施形態に限定されるものではなく、その要旨を逸脱しない範囲で種々変更可能であることは言うまでもない。   As mentioned above, although this invention was demonstrated based on embodiment, it cannot be overemphasized that this invention can be variously changed in the range which is not limited to the said embodiment and does not deviate from the summary.

本発明は、半導体装置の製造に関するものなので、半導体装置を製造する製造業において幅広く利用することができる。   Since the present invention relates to the manufacture of semiconductor devices, it can be widely used in the manufacturing industry for manufacturing semiconductor devices.

１・・・配線母基板、１２・・・配線基板、１２ａ・・・配線基板の一面、１２ｂ・・・配線基板の他面、１３・・・接続パッド、１４・・・ランド、１５・・・半導体チップ、２１，３１，４１・・・封止樹脂、２２・・・ダイシングライン、 DESCRIPTION OF SYMBOLS 1 ... Wiring mother board, 12 ... Wiring board, 12a ... One side of a wiring board, 12b ... Other side of a wiring board, 13 ... Connection pad, 14 ... Land, 15 ... Semiconductor chip, 21, 31, 41 ... sealing resin, 22 ... dicing line,

Claims (5)

配線基板に封止樹脂をモールド工法によって形成する工程と、
前記配線基板に設けられたダイシングラインに沿って前記封止樹脂を切断する工程と、
切断した後に前記封止樹脂を加熱硬化する工程と、を含むことを特徴とする半導体装置の製造方法。 Forming a sealing resin on the wiring board by a molding method;
Cutting the sealing resin along a dicing line provided on the wiring board;
And a step of heat-curing the sealing resin after cutting. 一面に接続パッドを有し、他面に前記接続パッドと電気的に接続された複数のランドを有した配線基板を準備する工程と、
前記配線基板の一面上に、半導体チップを搭載する工程と、
前記接続パッドと、前記半導体チップに設けられた電極パッドとを、電気的に接続する工程と、
前記配線基板に封止樹脂をモールド工法によって形成する工程と、
前記配線基板に設けられたダイシングラインに沿って前記封止樹脂を切断する工程と、
切断した後に前記封止樹脂を加熱硬化する工程と、を含むことを特徴とする半導体装置の製造方法。 Preparing a wiring board having a connection pad on one side and a plurality of lands electrically connected to the connection pad on the other side;
Mounting a semiconductor chip on one surface of the wiring board;
Electrically connecting the connection pads and electrode pads provided on the semiconductor chip;
Forming a sealing resin on the wiring board by a molding method;
Cutting the sealing resin along a dicing line provided on the wiring board;
And a step of heat-curing the sealing resin after cutting. 前記配線基板に設けられたダイシングラインに沿って前記封止樹脂を切断する際に、前記封止樹脂をその厚さ方向の一部のみを切断することを特徴とする請求項１または請求項２に記載の半導体装置の製造方法。   3. When cutting the sealing resin along a dicing line provided on the wiring board, only a part of the sealing resin in the thickness direction is cut. The manufacturing method of the semiconductor device as described in any one of Claims 1-3. 前記配線基板に設けられたダイシングラインに沿って前記封止樹脂を切断する際に、前記ダイシングラインの一部のみに沿って前記封止樹脂を切断することを特徴とする請求項１ないし請求項３のいずれか１項に記載の半導体装置の製造方法。   2. The sealing resin is cut along only a part of the dicing line when the sealing resin is cut along a dicing line provided on the wiring board. 4. A method for manufacturing a semiconductor device according to any one of 3 above. 配線基板に封止樹脂をモールド工法によって形成する工程と、
前記配線基板に設けられたダイシングラインに沿って前記配線基板及び前記封止樹脂を切断分離する工程と、
分離した後に前記封止樹脂を加熱硬化する工程と、を含むことを特徴とする半導体装置の製造方法。 Forming a sealing resin on the wiring board by a molding method;
Cutting and separating the wiring board and the sealing resin along a dicing line provided on the wiring board;
And a step of heat-curing the sealing resin after being separated.
JP2009200381A 2009-08-31 2009-08-31 Manufacturing method of semiconductor device Pending JP2011054653A (en)

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JP2015115553A (en) * 2013-12-13 2015-06-22 株式会社東芝 Semiconductor device manufacturing method
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