JP2003124431A - Wafer-form sheet, a chip-form electronic part, and their manufacturing method - Google Patents
Wafer-form sheet, a chip-form electronic part, and their manufacturing methodInfo
- Publication number
- JP2003124431A JP2003124431A JP2001319542A JP2001319542A JP2003124431A JP 2003124431 A JP2003124431 A JP 2003124431A JP 2001319542 A JP2001319542 A JP 2001319542A JP 2001319542 A JP2001319542 A JP 2001319542A JP 2003124431 A JP2003124431 A JP 2003124431A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor chip
- wafer
- chip
- sheet
- electrode surface
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 27
- 239000004065 semiconductor Substances 0.000 claims abstract description 194
- 238000000034 method Methods 0.000 claims abstract description 19
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 41
- 229910052710 silicon Inorganic materials 0.000 claims description 41
- 239000010703 silicon Substances 0.000 claims description 41
- 230000001070 adhesive effect Effects 0.000 claims description 38
- 239000000853 adhesive Substances 0.000 claims description 37
- 239000010410 layer Substances 0.000 claims description 34
- 229920003002 synthetic resin Polymers 0.000 claims description 22
- 239000000057 synthetic resin Substances 0.000 claims description 22
- 239000011229 interlayer Substances 0.000 claims description 20
- 239000000463 material Substances 0.000 claims description 3
- 239000004820 Pressure-sensitive adhesive Substances 0.000 claims 8
- 239000003822 epoxy resin Substances 0.000 abstract description 19
- 229920000647 polyepoxide Polymers 0.000 abstract description 19
- 229920001296 polysiloxane Polymers 0.000 abstract 1
- 239000000758 substrate Substances 0.000 description 8
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 7
- 239000010453 quartz Substances 0.000 description 5
- 238000010438 heat treatment Methods 0.000 description 4
- 238000002161 passivation Methods 0.000 description 4
- 238000012360 testing method Methods 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 229920005989 resin Polymers 0.000 description 3
- 239000011347 resin Substances 0.000 description 3
- 238000001816 cooling Methods 0.000 description 2
- 230000002950 deficient Effects 0.000 description 2
- 230000009977 dual effect Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 229920001721 polyimide Polymers 0.000 description 2
- 230000035939 shock Effects 0.000 description 2
- 239000004642 Polyimide Substances 0.000 description 1
- 230000005856 abnormality Effects 0.000 description 1
- 150000001408 amides Chemical class 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000008602 contraction Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000012634 fragment Substances 0.000 description 1
- 239000004850 liquid epoxy resins (LERs) Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000010355 oscillation Effects 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 239000009719 polyimide resin Substances 0.000 description 1
- 229920000642 polymer Polymers 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 230000000630 rising effect Effects 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- 229920001169 thermoplastic Polymers 0.000 description 1
- 229920001187 thermosetting polymer Polymers 0.000 description 1
- 239000004416 thermosoftening plastic Substances 0.000 description 1
- 238000009849 vacuum degassing Methods 0.000 description 1
- 239000013585 weight reducing agent Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/568—Temporary substrate used as encapsulation process aid
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
- H01L2224/241—Disposition
- H01L2224/24135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/24137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/102—Material of the semiconductor or solid state bodies
- H01L2924/1025—Semiconducting materials
- H01L2924/10251—Elemental semiconductors, i.e. Group IV
- H01L2924/10253—Silicon [Si]
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Dicing (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明はウェーハ状シ−ト、
チップ状電子部品、およびそれらの製造方法に関するも
のであり、更に詳しくは、所定のピッチに配置された複
数個の半導体チップと、半導体チップの電極面以外の底
面および側面を覆い連結する連続相の合成樹脂層と、電
極面側に層間絶縁膜を介して形成された配線層を有する
ウェーハ状シ−ト、そのウェーハ状シートを単数または
複数の半導体チップが含まれるようにダイシングして得
られるチップ状電子部品、およびそれらの製造方法に関
するものである。TECHNICAL FIELD The present invention relates to a wafer-like sheet,
The present invention relates to a chip-shaped electronic component and a manufacturing method thereof, and more specifically, a plurality of semiconductor chips arranged at a predetermined pitch and a continuous phase that covers and connects the bottom surface and side surfaces other than the electrode surface of the semiconductor chip. Wafer-shaped sheet having a synthetic resin layer and a wiring layer formed on the electrode surface side via an interlayer insulating film, and a chip obtained by dicing the wafer-shaped sheet to include a single or a plurality of semiconductor chips The present invention relates to an electronic component and a manufacturing method thereof.
【０００２】[0002]
【従来の技術】従来、半導体チップは例えばＱＦＰ（ク
オッド・フラット・パッケージ）のように周囲に多数本
のリード端子を有する形状の封止体として使用されてき
たが、近年の携帯電話、ノートパソコン等に代表される
可搬性電子機器において小型化、薄型化、軽量化の要請
が大であり、これに応ずるものとして半導体チップをＣ
ＳＰ（チップ・サイズ・パッケージ）化したものが採用
されるようになっている。すなわち、半導体チップをダ
イペーストによってインターポーザ基板の一面にフェイ
スアップに固定し、半導体チップの電極とインターポー
ザ基板の電極を金線でワイヤボンディングして、インタ
ーポーザ基板の他面の電極を例えば半田ボールによって
回路基板（マザーボード）の電極に接続するか、または
インターポーザ基板の電極に対してフェイスダウンとし
た半導体チップの電極に設けたバンプをフリップチップ
的に接続して、インターポーザ基板の他面の電極を回路
基板の電極に接続するものである。2. Description of the Related Art Conventionally, a semiconductor chip has been used as an encapsulating body having a large number of lead terminals in its periphery such as a QFP (quad flat package). There is a great demand for downsizing, thinning, and weight reduction in portable electronic equipment such as a semiconductor chip.
An SP (chip size package) version has been adopted. That is, the semiconductor chip is fixed face-up on one surface of the interposer substrate by die paste, the electrodes of the semiconductor chip and the electrodes of the interposer substrate are wire-bonded with a gold wire, and the electrodes on the other surface of the interposer substrate are circuited by, for example, solder balls. The electrodes on the other surface of the interposer board are connected to the electrodes of the board (motherboard) or the bumps provided on the electrodes of the semiconductor chip that face down with respect to the electrodes of the interposer board are connected in a flip-chip manner. It is connected to the electrode of.
【０００３】上記のＣＳＰは個々の半導体チップを可及
的に小さくパッケージして回路基板に高密度に実装する
ものであるが、これを更に進めて、複数個、複数種の半
導体チップを１個にパッケージしてモジュール化したＭ
ＣＭ（マルチ・チップ・モジュール）の実用化が図られ
ている。例えば、デジタル携帯電話におけるＳＲＡＭ
（スタティックラム）、フラッシュメモリ、マイクロコ
ンピュータ等の半導体チップを１個にパッケージしたＭ
ＣＭのチップ状電子部品である。ＭＣＭに使用されるチ
ップ状電子部品には上記以外にもあり、例えば発振用の
チップ状ＬＣＲはその一例である。The above-mentioned CSP packages individual semiconductor chips as small as possible and mounts them on a circuit board with a high density. M packaged in and modularized
Commercialization of CM (multi-chip module) has been attempted. For example, SRAM in a digital mobile phone
(Static RAM), Flash memory, Microcomputer, etc.
It is a chip-shaped electronic component of CM. There are other chip-shaped electronic components used in the MCM than the above, and for example, a chip-shaped LCR for oscillation is one example.
【０００４】そして、ＭＣＭ化の技術の中に、半導体チ
ップを個別にＭＣＭ化するものがある。図８はその中の
一つの方式を示し、図８のＡは斜視図、図８のＢは側面
図であるが、半導体チップ６０Ａ、６０Ｂをダイペース
トによって回路基板７０の一面にフェイスアップに固定
し、半導体チップ６０Ａ、６０Ｂの電極パッド６１と回
路基板７０の電極パッド７１を金線６２でワイヤボンデ
ィングするものである。回路基板７０の他面には接続用
の電極７２が設けられている。また同様な図９は、フェ
イスダウンとした半導体チップ６０Ａ、６０Ｂのバンプ
６３を回路基板７０の電極７１に対してフリップチップ
的に接続するものであり、半導体チップ６０Ａ、６０Ｂ
と回路基板との間はアンダーフィル６４が充填されてい
る。しかし、半導体チップを個別にＭＣＭ化する方法は
製造コストの増大を伴い易い。Among the MCM techniques, there is a technique in which semiconductor chips are individually made into MCMs. FIG. 8 shows one of the methods, and FIG. 8A is a perspective view and FIG. 8B is a side view. The semiconductor chips 60A and 60B are fixed face-up on one surface of the circuit board 70 by die paste. Then, the electrode pad 61 of the semiconductor chips 60A and 60B and the electrode pad 71 of the circuit board 70 are wire-bonded with the gold wire 62. An electrode 72 for connection is provided on the other surface of the circuit board 70. Further, FIG. 9 similarly shows that the bumps 63 of the face-down semiconductor chips 60A and 60B are flip-chip connected to the electrodes 71 of the circuit board 70.
An underfill 64 is filled between the circuit board and the circuit board. However, the method of individually converting the semiconductor chips into MCMs is likely to involve an increase in manufacturing cost.
【０００５】これに対し、本出願人が先に出願した特願
２０００−１２２１１２号には、チップ状電子部品、そ
れを製造するための疑似ウェーハ、およびそれらの製造
方法が開示されている。 図５、図６はその方法による
疑似ウェーハの一例であるウェーハ状シート２０の製造
方法をステップ的に示す断面図である。すなわち、図５
のＡに示すように、石英基板３上に粘着面を上向きにし
て固定した粘着性シート４に対し、図５のＢに示すよう
に、二種の半導体チップ１３Ａ、１３Ｂを所定のピッチ
でフェイスダウンに粘着させる。なお図７は、半導体チ
ップ１３Ａ、１３Ｂを粘着させた粘着性シート４の全体
を示す斜視図であり、図５のＢに対応する図である。続
いて図５のＣに示すように、その全面に液状のエポキシ
樹脂１２を塗布し、要すれば真空脱泡してボイドが残ら
ないようにした後に加熱して硬化させる。その後、図５
のＤに示すように、石英基板３側から紫外線を照射し粘
着剤を紫外線硬化させて（または加熱し粘着剤を熱硬化
させて）粘着性を失わせ、半導体チップ１３Ａ、１３Ｂ
とエポキシ樹脂１２とからなるウェーハ状シート２０を
粘着性シート４から剥離する。なお本文において、ウェ
ーハ状シート２０は、上記の半導体チップ１３Ａ、１３
Ｂとエポキシ樹脂１２とからなるもののほか、その半導
体チップ１３Ａ、１３Ｂの側の面に層間絶縁膜、配線
層、オーバーコート膜を形成させたそれぞれの段階のも
のも含む。On the other hand, Japanese Patent Application No. 2000-122112 previously filed by the present applicant discloses a chip-shaped electronic component, a pseudo wafer for manufacturing the same, and a manufacturing method thereof. 5 and 6 are cross-sectional views showing stepwise a method for manufacturing a wafer-shaped sheet 20 which is an example of a pseudo wafer by the method. That is, FIG.
As shown in A of FIG. 5, with respect to the adhesive sheet 4 fixed on the quartz substrate 3 with its adhesive surface facing upward, as shown in B of FIG. Stick it down. Note that FIG. 7 is a perspective view showing the entire adhesive sheet 4 to which the semiconductor chips 13A and 13B are adhered, and is a view corresponding to B in FIG. Subsequently, as shown in FIG. 5C, a liquid epoxy resin 12 is applied to the entire surface, and if necessary, vacuum degassing is performed to eliminate voids, and then the resin is heated and cured. After that, FIG.
As shown in D of FIG. 3, the semiconductor chips 13A and 13B are irradiated with ultraviolet rays from the quartz substrate 3 side to cure the adhesive with ultraviolet rays (or heat the adhesive to thermally cure the adhesive) to lose the adhesiveness.
The wafer-shaped sheet 20 including the epoxy resin 12 and the epoxy resin 12 is peeled from the adhesive sheet 4. In the text, the wafer-shaped sheet 20 is the semiconductor chips 13A, 13 described above.
In addition to those composed of B and the epoxy resin 12, those of each stage in which an interlayer insulating film, a wiring layer, and an overcoat film are formed on the surface of the semiconductor chips 13A and 13B are also included.
【０００６】図６のＡは剥離された図５のＤのウェーハ
状シート２０を裏返しにして上下を反転させた状態を示
し、半導体チップ１３Ａと半導体チップ１３Ｂが電極面
２２ａ、２２ｂ以外の底面と側面を連続相のエポキシ樹
脂１２によって覆われて連結されたものである。そし
て、半導体チップ１３Ａの電極面２２ａは電極１４
ａ1、１４ａ2 、パッシベーション膜１５ａからなり、
半導体チップ１３Ｂの電極面２２ｂは電極１４ｂ1 、１
４ｂ2 、 パッシベーション膜１５ｂからなっている。
続く図６のＢは、ウェーハ状シート２０の全面に厚さ１
０〜１５μｍ程度の層間絶縁膜１６を形成して、半導体
チップ１３Ａの電極１４ａ1 、１４ａ2 、および半導体
チップ１３Ｂの電極１４ｂ1 、１４ｂ2 に対応する部分
にビアホール１７ａ1 、１７ａ2 およびビアホール１７
ｂ1 、１７ｂ2 を開孔した状態を示す。更に図６のＣ
は、全面に成膜した厚さ１〜２μｍの配線層をパターニ
ングして、半導体チップ１３Ａの電極１４ａ2 と半導体
チップ１３Ｂの電極１４ｂ1 を接続する配線１８ａｂ、
半導体チップ１３Ａを外部と接続する配線１８ａ、半導
体チップ１３Ｂを外部と接続する配線１８ｂを、例えば
Ｌ／Ｓ（ラインアンドスペース）３０μｍで形成させた
状態を示す。更に続く図６のＤは、配線１８ａｂ、１８
ａ、１８ｂを含む全面にオーバーコート膜１９を形成し
た後、オーバーコート膜１９を開孔して配線１８ａ、１
８ｂの電極パッド２１ａ、２１ｂを露出させた状態を示
す。なお、図６のＤにおけるウェーハ状シート２０は、
半導体チップ１３Ａの左側と半導体チップ１３Ｂの右側
において示す二点鎖線Ｄに沿ってダイシングされて、半
導体チップ１３Ａと半導体チップ１３Ｂとが１個にパッ
ケージされたＭＣＭのチップ状電子部品２が得られる。FIG. 6A shows a state in which the peeled wafer-like sheet 20 of FIG. 5D is turned upside down and turned upside down. The semiconductor chip 13A and the semiconductor chip 13B have bottom surfaces other than the electrode surfaces 22a and 22b. The side surface is covered with the continuous phase epoxy resin 12 and connected. The electrode surface 22a of the semiconductor chip 13A is connected to the electrode 14
a 1 , 14a 2 , a passivation film 15a,
The electrode surface 22b of the semiconductor chip 13B has electrodes 14b 1 , 1
4b 2 and a passivation film 15b.
Continuing with FIG. 6B, the thickness of 1
The interlayer insulating film 16 having a thickness of 0 to 15 μm is formed, and the via holes 17a 1 and 17a 2 and the via hole 17 are formed in the portions corresponding to the electrodes 14a 1 and 14a 2 of the semiconductor chip 13A and the electrodes 14b 1 and 14b 2 of the semiconductor chip 13B.
The state where b 1 and 17 b 2 are opened is shown. Further, C in FIG.
Is a wiring 18ab for connecting the electrode 14a 2 of the semiconductor chip 13A and the electrode 14b 1 of the semiconductor chip 13B by patterning a wiring layer having a thickness of 1 to 2 μm formed on the entire surface.
A wiring 18a for connecting the semiconductor chip 13A to the outside and a wiring 18b for connecting the semiconductor chip 13B to the outside are formed with an L / S (line and space) of 30 μm, for example. Further, FIG. 6D shows the wirings 18ab, 18
After the overcoat film 19 is formed on the entire surface including a and 18b, the overcoat film 19 is opened to form the wirings 18a and 1a.
8B shows a state in which the electrode pads 21a and 21b of 8b are exposed. The wafer-shaped sheet 20 in D of FIG.
By dicing along a two-dot chain line D shown on the left side of the semiconductor chip 13A and the right side of the semiconductor chip 13B, the chip-shaped electronic component 2 of the MCM in which the semiconductor chip 13A and the semiconductor chip 13B are packaged into one is obtained.
【０００７】そして、上記のようなウェーハ状シート２
０によるＭＣＭの技術は次に示すような利点を有してい
る。
開発の最先端にある半導体チップはシリコンウェー
ハ当りの良品の収量が低く、シリコンウェーハ状態で半
導体チップを処理すると、製品にならない半導体チップ
も処理されることになり無駄が多いが、ウェーハ状シー
トによる方法では良品の半導体チップのみを選別して並
べ得るので処理に無駄を生じない。
良品のみの半導体チップを並べてウェーハ状シート
を作製するので、例えば接続用のバンプの形成を一括し
て行うことができ、半導体チップの個々についてバンプ
を形成する場合に比して大幅な合理化が可能である。
自社、他社を問わず製造元が異なる半導体チップを
入手し、同一のウェーハ状シート面に並べて組み合わせ
ることができる。Then, the wafer-like sheet 2 as described above
The 0-based MCM technology has the following advantages. Semiconductor chips, which are at the forefront of development, have a low yield of non-defective products per silicon wafer, and when semiconductor chips are processed in the silicon wafer state, semiconductor chips that are not products are also processed, which is wasteful. According to the method, only non-defective semiconductor chips can be selected and arranged, so that the processing is not wasted. Wafer-shaped sheets are produced by arranging only good semiconductor chips, so that, for example, bumps for connection can be formed in a batch, which can be significantly rationalized when bumps are formed for each semiconductor chip. Is. It is possible to obtain semiconductor chips from different manufacturers regardless of whether they are in-house or other companies, and arrange and combine them on the same wafer-shaped sheet surface.
【０００８】[0008]
【発明が解決しようとする課題】しかるに、図６のＡか
らＤまでに示すウェーハ状シート２０は、熱膨張係数が
一桁近く異なる有機のエポキシ樹脂２と、無機シリコン
の半導体チップ１３Ａ、１３Ｂとからなるので、図５の
Ｃのエポキシ樹脂１２が固化されて寸法が定まる硬化時
の温度においては、エポキシ樹脂１２と半導体チップ１
３Ａ、１３Ｂとの界面に収縮応力は存在せず、ウェーハ
状シート２０は反らないが、この硬化温度から冷却され
ると、半導体チップ１３Ａ、１３Ｂに比して熱膨張係数
の大きいエポキシ樹脂１２は収縮量が大であるから、エ
ポキシ樹脂１２を内側にして反るようになる。そして、
その収縮は、半導体チプチップ１３Ａ、１３Ｂの電極面
２２ａ、２２ｂの稜線２４部分において曲率半径の小さ
い折り曲げを生じるので、その折り曲げの近傍に存在す
る配線１８ａ、１８ｂ、１８ａｂにクラックが発生し易
く、発生したクラックは断線に至る怖れが大である。勿
論、温度上昇すれは反りは復元されが、一度発生したク
ラックや断線はそのまま残る。However, the wafer-like sheet 20 shown in FIGS. 6A to 6D includes an organic epoxy resin 2 having a coefficient of thermal expansion different by almost one digit and inorganic semiconductor chips 13A and 13B. Therefore, the epoxy resin 12 and the semiconductor chip 1 at the curing temperature at which the epoxy resin 12 of FIG.
Although there is no shrinkage stress at the interfaces with 3A and 13B and the wafer-shaped sheet 20 does not warp, when cooled from this curing temperature, the epoxy resin 12 having a larger coefficient of thermal expansion than the semiconductor chips 13A and 13B. Has a large shrinkage amount, so that the epoxy resin 12 warps with the epoxy resin 12 inside. And
The contraction causes a bend with a small radius of curvature at the ridgeline 24 portion of the electrode surfaces 22a, 22b of the semiconductor chip chips 13A, 13B, so that cracks easily occur in the wirings 18a, 18b, 18ab existing in the vicinity of the bend. There is a great fear that the cracks will break. Of course, as the temperature rises, the warp is restored, but cracks and disconnections that have occurred once remain as they are.
【０００９】このようなウェーハ状シート２０の反りと
復元は、上述した配線１８ａ、１８ｂ、１８ａｂやオー
バーコート膜１９の形成時における加熱と、それらの間
における冷却とによっても繰り返される。更には、この
ような反りと復元は、ウェーハ状シート２０から切り出
したチップ状電子部品２を搭載する可搬性電子機器にお
いても、使用される雰囲気温度の上昇と下降によってチ
ップ状電子部品２に反りと復元が同様に発生する。そし
て、そのチップ状電子部品２の実用上の寿命を推定する
ための加速試験である熱衝撃試験（例えばチップ状電子
部品２を−２５℃で９分間、常温で１分間、＋１２５℃
で９分間、常温で１分間の保持を行う温度サイクルを１
サイクルとして、この温度サイクルを繰り返す試験）に
よってもチップ状電子部品２に反りと復元が同様に繰り
返される。Such warpage and restoration of the wafer-shaped sheet 20 are repeated by heating at the time of forming the wirings 18a, 18b, 18ab and the overcoat film 19 and cooling between them. Further, such warpage and restoration causes warpage of the chip-shaped electronic component 2 due to rise and fall of the ambient temperature used even in a portable electronic device in which the chip-shaped electronic component 2 cut out from the wafer-shaped sheet 20 is mounted. And restore occurs as well. Then, a thermal shock test which is an accelerated test for estimating the practical life of the chip-shaped electronic component 2 (for example, the chip-shaped electronic component 2 is -25 ° C. for 9 minutes, room temperature for 1 minute, and + 125 ° C.
1 cycle for 9 minutes at room temperature and 1 minute at room temperature
As a cycle, a warp and restoration are similarly repeated in the chip-shaped electronic component 2 by a test in which this temperature cycle is repeated.
【００１０】本発明は上述の問題に鑑みてなされ、加
熱、冷却によって配線にクラックないしは断線を生じな
いウェーハ状シート、チップ状電子部品、およびそれら
の製造方法を提供することを課題とする。The present invention has been made in view of the above problems, and an object of the present invention is to provide a wafer-shaped sheet, a chip-shaped electronic component, and a manufacturing method thereof, which do not cause cracks or disconnections in wiring due to heating and cooling.
【００１１】[0011]
【課題を解決するための手段】上記の課題は請求項１、
請求項３、請求項５、または請求項６の構成によって解
決されるが、その解決手段を説明すれば、次の如くであ
る。[Means for Solving the Problem]
The problem can be solved by the configuration of claim 3, claim 5, or claim 6, and the solution means will be described below.
【００１２】請求項１のウェーハ状シートは、所定のピ
ッチに配置された複数個の半導体チップと、半導体チッ
プの電極面以外の底面および側面を覆い連結する連続相
の合成樹脂層と、電極面側に層間絶縁膜を介して形成さ
れた配線層とを有するウェーハ状シートにおいて、半導
体チップの電極面と側面との間の稜線が面取りされてい
るものである。このようなウェーハ状シートは、温度の
上昇、下降によって反りと復元が繰り返されても、半導
体チップの電極面と側面との間の稜線（以降、電極面の
稜線と略称することがある）が面取りされているので、
稜線部分で小さい曲率半径に折り曲げられることはな
く、近傍の配線にクラックや断線を招かない。A wafer-like sheet according to a first aspect of the present invention is a plurality of semiconductor chips arranged at a predetermined pitch, a synthetic resin layer of a continuous phase which covers and connects bottom surfaces and side surfaces other than electrode surfaces of the semiconductor chips, and electrode surfaces. In a wafer-shaped sheet having a wiring layer formed on its side with an interlayer insulating film interposed therebetween, a ridgeline between an electrode surface and a side surface of a semiconductor chip is chamfered. Such a wafer-shaped sheet has a ridge line (hereinafter, may be abbreviated as a ridge line of the electrode surface) between the electrode surface and the side surface of the semiconductor chip even if warping and restoration are repeated due to temperature rise and fall. Because it is chamfered,
It is not bent to a small radius of curvature at the ridge portion, and does not cause cracks or breaks in the wiring in the vicinity.
【００１３】請求項１に従属する請求項２のウェーハ状
シートは、半導体チップの電極面の稜線の面取りが、半
導体チップをシリコンウェーハから切り出すダイシング
時に、先端断面がＶ字形状の厚刃ブレードを用いて半導
体チップの電極面側からシリコンウェーハをハーフカッ
トし、続いて細刃ブレードによってハーフカットの中央
底部から反対面までをフルカットして施されたものであ
る。このようなウェーハ状シートは、シリコンウェーハ
からのダイシングによって自ら面取りされる半導体チッ
プを使用するので、面取りによるコスト上昇を伴わな
い。A wafer-like sheet according to claim 2 which depends on claim 1 is a thick blade blade having a V-shaped cross section when the semiconductor chip electrode surface is chamfered on the ridge line during dicing to cut the semiconductor chip from a silicon wafer. The silicon wafer is half-cut from the electrode surface side of the semiconductor chip by using it, and then a full cut is performed from the center bottom of the half-cut to the opposite surface by a fine blade. Since such a wafer-like sheet uses semiconductor chips that are chamfered by dicing from a silicon wafer, the chamfering does not increase the cost.
【００１４】請求項３のチップ状電子部品は、所定のピ
ッチに配置された複数個の半導体チップと、半導体チッ
プの電極面以外の底面および側面を覆い連結する連続相
の合成樹脂層と、電極面側に層間絶縁膜を介して形成さ
れた配線層とを有するウェーハ状シートを、単数または
複数の半導体チップが含まれるように、ダイシングして
得られるチップ状電子部品において、半導体チップの電
極面と側面との間の稜線が面取りされているものであ
る。このようなチップ状電子部品は、温度の上昇、下降
によって反りと復元が繰り返されても、半導体チップの
電極面の稜線が面取りされているので、稜線部分で小さ
い曲率半径に折り曲げられることはなく、近傍の配線に
クラックや断線を招かない。According to a third aspect of the present invention, in a chip-shaped electronic component, a plurality of semiconductor chips arranged at a predetermined pitch, a continuous-phase synthetic resin layer that covers and connects bottom surfaces and side surfaces other than electrode surfaces of the semiconductor chips, and electrodes. In a chip-shaped electronic component obtained by dicing a wafer-shaped sheet having a wiring layer formed on the surface side via an interlayer insulating film so as to include one or more semiconductor chips, the electrode surface of the semiconductor chip The ridge between the side and the side is chamfered. In such a chip-shaped electronic component, even if warping and restoration are repeated due to temperature rise and fall, the ridge line of the electrode surface of the semiconductor chip is chamfered, so that the ridge portion does not bend to a small radius of curvature. , Does not cause cracks or breaks in nearby wiring.
【００１５】請求項３に従属する請求項４のチップ状電
子部品は、半導体チップの電極面の稜線の面取りが、半
導体チップをシリコンウェーハから切り出すダイシング
時に、先端断面がＶ字形状の厚刃ブレードを用いて半導
体チップの電極面側からシリコンウェーハをハーフカッ
トし、続いて細刃ブレードによってハーフカットの中央
底部から反対面までをフルカットして施されたものであ
る。このようなチップ状電子部品は、シリコンウェーハ
からのダイシングによって自ら面取りされる半導体チッ
プを使用するので、面取りによるコスト上昇を伴わな
い。According to a fourth aspect of the present invention, in the chip-shaped electronic component, the ridge line of the electrode surface of the semiconductor chip is chamfered at the time of dicing to cut the semiconductor chip from the silicon wafer. Is used to half-cut a silicon wafer from the electrode surface side of a semiconductor chip, and then a half blade is fully cut from the center bottom to the opposite surface of the half-cut with a fine blade. Since such a chip-shaped electronic component uses a semiconductor chip which is chamfered by itself by dicing from a silicon wafer, the chamfering does not increase the cost.
【００１６】請求項５のウェーハ状シートの製造方法
は、粘着力を低下させることが可能な粘着性シートを平
板上に粘着面を上向きに固定する工程と、粘着性シート
上に複数の半導体チップを所定のピッチで電極面を下向
きに粘着させる工程と、半導体チップを含む粘着性シー
トの全面に合成樹脂層を形成する工程と、粘着性シート
の粘着力を低下させて半導体チップと共に合成樹脂層を
粘着性シートから剥離する工程と、電極面側に層間絶縁
膜を介して配線層を形成する工程とを有するウェーハ状
シートの製造方法において、半導体チップとして、半導
体チップをシリコンウェーハから切り出すダイシング時
に、先端断面がＶ字形状の厚刃ブレードを用いて半導体
チップの電極面側からシリコンウェーハをハーフカット
し、続いて細刃ブレードによってハーフカットの中央底
部から反対面までをフルカットしたものを使用する方法
である。このようなウェーハ状シートの製造方法は、シ
リコンウェーハからのダイシング時に自ら面取りされる
半導体チップを使用するので、半導体チップの面取りに
よるコスト上昇を伴わない。According to a fifth aspect of the present invention, in the method for manufacturing a wafer-shaped sheet, a step of fixing an adhesive sheet capable of reducing the adhesive force on a flat plate with the adhesive surface facing upward, and a plurality of semiconductor chips on the adhesive sheet. A step of adhering the electrode surface downward at a predetermined pitch, a step of forming a synthetic resin layer on the entire surface of an adhesive sheet containing a semiconductor chip, and a step of reducing the adhesive force of the adhesive sheet to form a synthetic resin layer with the semiconductor chip. In the method for manufacturing a wafer-like sheet having a step of peeling the adhesive sheet from the adhesive sheet, and a step of forming a wiring layer on the electrode surface side via an interlayer insulating film, as a semiconductor chip, at the time of dicing to cut the semiconductor chip from a silicon wafer. , A silicon blade is half-cut from the electrode surface side of the semiconductor chip using a thick blade with a V-shaped cross section, It is to use a material obtained by full cut to the opposite side from the bottom middle of the half-cut by de. Since such a wafer-shaped sheet manufacturing method uses the semiconductor chip which is chamfered by itself when dicing from the silicon wafer, the chamfering of the semiconductor chip does not increase the cost.
【００１７】請求項６のチップ状電子部品の製造方法
は、粘着力を低下させることが可能な粘着性シートを平
板上に粘着面を上向きに固定する工程と、粘着性シート
上に複数の半導体チップを所定のピッチで電極面を下向
きに粘着させる工程と、半導体チップを含む粘着性シー
トの全面に合成樹脂層を形成する工程と、粘着性シート
の粘着力を低下させて半導体チップと共に合成樹脂層を
粘着性シートから剥離する工程と、電極面側に層間絶縁
膜を介して配線層を形成する工程とによって得られるウ
ェーハ状シートを、単数または複数の半導体チップが含
まれるようにダイシングするチップ状電子部品の製造方
法において、半導体チップとして、半導体チップをシリ
コンウェーハから切り出すダイシング時に、先端断面が
Ｖ字形状の厚刃ブレードを用いて半導体チップの電極面
側からシリコンウェーハをハーフカットし、続いて細刃
ブレードによってハーフカットの中央底部から反対面ま
でをフルカットしたものを使用する方法である。このよ
うなチップ状電子部品の製造方法は、シリコンウェーハ
からのダイシング時に自ら面取りされる半導体チップを
使用するので、半導体チップの面取りによるコスト上昇
を伴わない。According to a sixth aspect of the present invention, there is provided a method of manufacturing a chip-shaped electronic component, which comprises a step of fixing an adhesive sheet capable of reducing an adhesive force on a flat plate with the adhesive surface facing upward, and a plurality of semiconductors on the adhesive sheet. The step of adhering the chip with the electrode surface facing down at a predetermined pitch, the step of forming a synthetic resin layer on the entire surface of the adhesive sheet including the semiconductor chip, and the adhesive force of the adhesive sheet to reduce the synthetic resin together with the semiconductor chip. Chip for dicing a wafer-shaped sheet obtained by a step of peeling a layer from an adhesive sheet and a step of forming a wiring layer on an electrode surface side via an interlayer insulating film so as to include a single or a plurality of semiconductor chips In a method for manufacturing a linear electronic component, a thick blade with a V-shaped cross section is used as a semiconductor chip when dicing the semiconductor chip from a silicon wafer. The silicon wafer half cut from the electrode surface of the semiconductor chip using a draw, followed by Hosoha blade is to use a material obtained by full cut to the opposite side from the bottom middle of the half-cut. Since such a method for manufacturing a chip-shaped electronic component uses a semiconductor chip which is chamfered by itself when dicing from a silicon wafer, the chamfering of the semiconductor chip does not increase the cost.
【００１８】[0018]
【発明の実施の形態】本発明は、上述したように、複数
個の半導体チップが所定のピッチで配置され、それらの
電極面以外の底面および側面が連続相の合成樹脂層で覆
われて連結されており、かつ電極面側に層間絶縁膜を介
して形成された配線層を有するウェーハ状シート、およ
びそのウェーハ状シートを単数または複数の半導体チッ
プが含まれるようにダイシングして得られるチップ状電
子部品、およびそれらの製造方法に関するものである。BEST MODE FOR CARRYING OUT THE INVENTION As described above, according to the present invention, a plurality of semiconductor chips are arranged at a predetermined pitch, and bottom surfaces and side surfaces other than the electrode surfaces thereof are covered with a continuous phase synthetic resin layer and connected. And a wafer-shaped sheet having a wiring layer formed on the electrode surface side via an interlayer insulating film, and a chip-shaped sheet obtained by dicing the wafer-shaped sheet to include one or more semiconductor chips The present invention relates to electronic components and manufacturing methods thereof.
【００１９】複数個の半導体チップは単一種の半導体チ
ップの複数個であってもよく、また複数種の半導体チッ
プであってもよく、更には単一種の複数個の半導体チッ
プに他種の半導体チップが追加されたものであってもよ
い。そして使用する半導体チップは、その電極面と側面
との間の稜線が面取りされていることを必要とする。詳
しくは後述するが、半導体チップの電極面の稜線をあら
かじめ面取りしておくことにより、合成樹脂と半導体チ
ップとの熱膨張係数の違いによってウェーハ状シート
（またはチップ状電子部品）が反りを生じる場合におい
ても、半導体チップの電極面の稜線が面取りされている
のでウェーハ状シート（またはチップ状電子部品）が小
さい曲率半径で折り曲げられることはなく、従って近傍
の配線にクラックや断線を生じることはない。The plurality of semiconductor chips may be a plurality of semiconductor chips of a single type, or may be semiconductor chips of a plurality of types. Further, a plurality of semiconductor chips of a single type may be used together with a semiconductor of another type. A chip may be added. The semiconductor chip to be used requires that the ridgeline between the electrode surface and the side surface be chamfered. As will be described later in detail, when the ridgeline of the electrode surface of the semiconductor chip is chamfered in advance, the wafer-shaped sheet (or the chip-shaped electronic component) warps due to the difference in the thermal expansion coefficient between the synthetic resin and the semiconductor chip. Also, since the ridge line of the electrode surface of the semiconductor chip is chamfered, the wafer-shaped sheet (or chip-shaped electronic component) is not bent with a small radius of curvature, and therefore, cracks or disconnections do not occur in the nearby wiring. .
【００２０】合成樹脂は、紫外線硬化性または熱硬化性
であって、後の層間絶縁膜、配線層、オーバーコート膜
等の形成時の加熱温度に耐えるものであればよく、その
種類は特に限定されない。通常的には半導体チップの封
止に広く採用されているエポキシ樹脂が好適に使用され
る。そのほか、熱可塑性の合成樹脂であっても、耐熱温
度が高くエンジニアリング樹脂に分類されるものも、加
熱温度との兼ね合いで使用され得る。また、合成樹脂に
はフィーラーとして例えば粉末状シリカを容積比で３０
〜６０％添加し、合成樹脂の見掛け上の熱膨張係数を低
下させたものが使用され得る。Any synthetic resin may be used as long as it is ultraviolet curable or thermosetting and can withstand the heating temperature during the subsequent formation of an interlayer insulating film, a wiring layer, an overcoat film, etc., and the kind thereof is not particularly limited. Not done. Usually, an epoxy resin widely used for sealing semiconductor chips is preferably used. In addition, even thermoplastic synthetic resins having high heat resistance and classified as engineering resins can be used in consideration of the heating temperature. Further, as a feeler for the synthetic resin, for example, powdered silica is used in a volume ratio of 30.
It is possible to use the one in which -60% is added and the apparent thermal expansion coefficient of the synthetic resin is lowered.
【００２１】そして、本発明のウェーハ状シートは、所
定のピッチで配列された複数の半導体チップの底面と側
面を合成樹脂層で覆うように適用し連結して製造され
る。そして、このようなウェーハ状シートの電極面側に
層間絶縁膜、配線層、更に好ましくはオーバーコート層
を設けたものについて、単数または複数の半導体チップ
が含まれるように、半導体チップ間で合成樹脂層をダイ
シングしてチップ状電子部品とすることは従来例の場合
と全く同様である。The wafer-like sheet of the present invention is manufactured by applying and connecting the bottom and side surfaces of a plurality of semiconductor chips arranged at a predetermined pitch with a synthetic resin layer. Then, regarding such a wafer-shaped sheet provided with an interlayer insulating film, a wiring layer, and more preferably an overcoat layer on the electrode surface side, a synthetic resin is used between the semiconductor chips so as to include a single or a plurality of semiconductor chips. Dicing the layers into chip-shaped electronic components is exactly the same as in the conventional example.
【００２２】半導体チップの電極面の稜線は、どのよう
に面取りしてもよいが、半導体チップの電極面と側面と
に交差する傾斜平面を形成させるのが最も簡便である。
面取り角を４５度としたもの、すなわち、電極面と傾斜
平面との内角、および傾斜平面と側面との内角が何れも
１３５度となるように面取りしたものは、両内角の角度
を非対称に面取りしたものと比較して、配線のクラッ
ク、断線を一層効果的に抑制する。更には、如何なる稜
線も残らないように、稜線を凸曲面で面取りし、電極面
と側面との間を連続的な曲面で繋いだものは配線のクラ
ック、断線を最も効果的に抑制する。The ridgeline of the electrode surface of the semiconductor chip may be chamfered in any way, but it is most convenient to form an inclined flat surface that intersects the electrode surface and the side surface of the semiconductor chip.
The chamfering angle is 45 degrees, that is, the chamfering is such that the inside angle between the electrode surface and the inclined plane and the inside angle between the inclined plane and the side surface are both 135 degrees. As compared with the above, the cracks and breaks in the wiring can be suppressed more effectively. Further, a chamfered ridge line so that no ridge line remains and the electrode surface and the side surface are connected by a continuous curved surface most effectively suppresses cracks and breaks in the wiring.
【００２３】また本発明のウェーハ状シート、チップ状
電子部品に使用される半導体チップの電極面の稜線の面
取りはどのような方法で行ってもよいが、次のようにし
て簡易に行い得る。すなわち、シリコンウェーハから半
導体チップを切り出す時に、先端断面がＶ字形状の厚刃
ブレードを用いて半導体チップの電極面側からシリコン
ウェーハをハーフカットし、続いて細刃ブレードによっ
てハーフカットの中央底部から反対面までをフルカット
することによって得られる。上記のように二種のブレー
ドを使用して二段カットすることにより、半導体チップ
の電極面の稜線は自ら面取りされるのである。なお、二
段カットはシリコンウェーハをダイシングする時に半導
体チップにチッピング（細片割れ）を発生させないよう
に一般的に採用されている技術であり、デュアル・ダイ
サーとして市販されている二段カットのダイサーの一段
目のブレードを上記のような厚刃ブレードに交換し、二
段目のブレードは一般的な薄刃ブレードとすることによ
り、通常的なダイシングを行うだけで、電極面の稜線を
面取りされた半導体チップが容易に得られる。Further, the chamfering of the ridgeline of the electrode surface of the semiconductor chip used in the wafer-shaped sheet or chip-shaped electronic component of the present invention may be carried out by any method, but it can be easily carried out as follows. That is, when cutting a semiconductor chip from a silicon wafer, the silicon wafer is half-cut from the electrode surface side of the semiconductor chip using a thick blade having a V-shaped tip cross section, and then from the center bottom of the half cut with a thin blade. Obtained by full cutting up to the opposite side. As described above, the ridge lines on the electrode surface of the semiconductor chip are chamfered by themselves by cutting in two stages using two kinds of blades. The two-step cutting is a technology that is generally adopted to prevent chipping (fragment breaks) in semiconductor chips when dicing a silicon wafer. By replacing the blade of the first stage with a thick blade as described above, the blade of the second stage is a general thin blade, and only by performing a normal dicing, the semiconductor with a chamfered ridge line of the electrode surface Chips are easily obtained.
【００２４】[0024]
【実施例】次に、本発明のウェーハ状シート、チップ状
電子部品、およびそれらの製造方法を実施例によって図
面を参照し具体的に説明する。EXAMPLES Next, the wafer-shaped sheet, the chip-shaped electronic component, and the manufacturing method thereof according to the present invention will be specifically described by way of examples with reference to the drawings.
【００２５】（実施例１）図１は配線層が設けられた実
施例１のウェーハ状シート１０（中央の断面図で示した
チップ状電子部品１の部分と、その左右の一点鎖線で示
す部分を含むもの）から、半導体チップ１３Ｃの左側と
半導体チップ１３Ｄの右側の二点鎖線Ｄで示す位置でダ
イシングして得られたチップ状電子部品１の断面図であ
る。すなわち、チップ状電子部品１は、半導体チップ１
３Ｃと半導体チップ１３Ｄが電極面以外の底面と側面を
連続相のエポキシ樹脂１２によって覆われて連結されて
いるものである。半導体チップ１３Ｃの電極面は電極１
４ａ1 、１４ａ2 、パッシベーション膜１５ａからな
り、半導体チップ１３Ｂの電極面は電極１４ｂ1 、１４
ｂ2 、 パッシベーション膜１５ｂからなっている。そ
して、半導体チップ１３Ｃ、１３Ｄを含む全面に厚さ１
０〜１５μｍ程度の層間絶縁膜１６が形成されて、ビア
ホール１７ａ1 、１７ａ2 、１７ｂ1 、１７ｂ2 が開孔
され、続いて、厚さ１〜２μｍ程度に設けた配線層をパ
ターニングして、半導体チップ１３Ａの電極１４ａ2 と
半導体チップ１３Ｂの電極１４ｂ1 を接続する配線１８
ａｂ、半導体チップ１３Ｃを外部と接続する配線１８
ａ、半導体チップ１３Ｄを外部と接続する配線１８ｂを
形成し、更に、配線１８ａｂ、１８ａ、１８ｂを含む全
面にオーバーコート膜１９を形成し、次いで配線１８
ａ、１８ｂの電極パッド２１ａ、２１ｂを露出させるよ
うにオーバーコート膜１９を開孔したものである。すな
わちチップ状電子部品１は、基本的には、従来例の図６
のＤのウェーハ状シート２０をダイシングして得られる
チップ状電子部品２と同様に構成されている。(Embodiment 1) FIG. 1 shows a wafer-like sheet 10 of Embodiment 1 in which a wiring layer is provided (the portion of the chip-shaped electronic component 1 shown in the central sectional view, and the portion shown by the one-dot chain line on the left and right sides thereof Is a cross-sectional view of the chip-shaped electronic component 1 obtained by dicing at positions on the left side of the semiconductor chip 13C and the right side of the semiconductor chip 13D at positions indicated by two-dot chain line D from FIG. That is, the chip-shaped electronic component 1 is the semiconductor chip 1
3C and the semiconductor chip 13D are connected by being covered with the continuous phase epoxy resin 12 on the bottom surface and side surfaces other than the electrode surface. The electrode surface of the semiconductor chip 13C is electrode 1
4a 1 and 14a 2 and a passivation film 15a, and the electrode surface of the semiconductor chip 13B has electrodes 14b 1 and 14a 1 .
b 2 and a passivation film 15b. Then, a thickness of 1 is formed on the entire surface including the semiconductor chips 13C and 13D.
The interlayer insulating film 16 having a thickness of 0 to 15 μm is formed, the via holes 17a 1 , 17a 2 , 17b 1 and 17b 2 are opened, and then the wiring layer having a thickness of 1 to 2 μm is patterned. Wiring 18 for connecting the electrode 14a 2 of the semiconductor chip 13A and the electrode 14b 1 of the semiconductor chip 13B
ab, wiring 18 for connecting the semiconductor chip 13C to the outside
a, a wiring 18b for connecting the semiconductor chip 13D to the outside is formed, and further, an overcoat film 19 is formed on the entire surface including the wirings 18ab, 18a, 18b, and then the wiring 18 is formed.
The overcoat film 19 is opened to expose the electrode pads 21a and 21b of a and 18b. That is, the chip-shaped electronic component 1 is basically the same as that shown in FIG.
It is configured in the same manner as the chip-shaped electronic component 2 obtained by dicing the wafer-shaped sheet 20 of D.
【００２６】実施例１のウェーハ状シート１０ないしは
チップ状電子部品１が従来例のウェーハ状シート２０な
いしはチップ状電子部品２と異なるところは、従来例で
使用されている半導体チップ１３Ａ、１３Ｂがシリコン
ウェーハから切り出したままの直方体形状であるに対し
て、実施例１で使用されている半導体チップ１３Ｃ、１
３Ｄは電極面の稜線が面取りされたものであるというこ
とである。図２は従来例の半導体チップ１３Ａと実施例
１の半導体チップ１３Ｃを比較して示す図であり、図２
のＡは平面図、図２のＢは図２のＡにおける［Ｂ］−
［Ｂ］線方向の断面図である。なお、簡明化のために電
極等の表示は省略している。半導体チップ１３Ａと半導
体チップ１３Ｃを比較して明らかなように、実施例１の
半導体チップ１３Ｃは従来例の半導体チップ１３Ａの電
極面２２と側面２３との間の稜線２４が面取りされてお
り、半導体チップ１３Ｃにおいては電極面２２と側面２
３とに交差する傾斜平面２５が形成されている。The wafer-shaped sheet 10 or the chip-shaped electronic component 1 of the first embodiment is different from the wafer-shaped sheet 20 or the chip-shaped electronic component 2 of the conventional example in that the semiconductor chips 13A and 13B used in the conventional example are made of silicon. The semiconductor chip 13C used in the first embodiment has a rectangular parallelepiped shape as it is cut out from the wafer,
3D means that the ridge line of the electrode surface is chamfered. FIG. 2 is a diagram showing a comparison between the conventional semiconductor chip 13A and the semiconductor chip 13C of the first embodiment.
2A is a plan view, and FIG. 2B is [B] -in FIG. 2A.
It is a sectional view of the [B] line direction. The electrodes and the like are omitted for the sake of simplicity. As is clear from comparison between the semiconductor chip 13A and the semiconductor chip 13C, the semiconductor chip 13C of the first embodiment has a chamfered ridge line 24 between the electrode surface 22 and the side surface 23 of the semiconductor chip 13A of the conventional example. In the chip 13C, the electrode surface 22 and the side surface 2
An inclined plane 25 intersecting with 3 is formed.
【００２７】そして、上記のような実施例１のウェーハ
状シート１０またはチップ状電子部品１を熱衝撃試験に
かけた時、３００サイクルを経過しても、配線１８ａ
ｂ、１８ａ、１８ｂのクラックや断線等の異常は認めら
れない。実施例１のウェーハ状シート１０およびチップ
状電子部品１は半導体チップ１３Ｃ、１３Ｄと配線１８
ａ、１８ｂ、１８ａｂとの間に厚さ１０〜１５μｍの層
間絶縁層１６を介在させているので配線１８ａ、１８
ｂ、１８ａｂはクラックや断線を生じにくい環境にある
と言えるが、将来的に一層の薄型化が望まれ層間絶縁膜
１６の厚さを２〜３μｍ程度とするような場合には、電
極面２２の稜線を面取りした半導体チップ１３Ｃ、１３
Ｄを使用する本発明のウェーハ状シート１０またはチッ
プ状電子部品１は一層効果的なものになると思考され
る。Then, when the wafer-shaped sheet 10 or the chip-shaped electronic component 1 of Example 1 as described above is subjected to a thermal shock test, the wiring 18a remains even after 300 cycles have passed.
No abnormalities such as cracks, disconnections, etc. of b, 18a, 18b were observed. The wafer-shaped sheet 10 and the chip-shaped electronic component 1 according to the first embodiment are the semiconductor chips 13C and 13D and the wiring 18.
Since the interlayer insulating layer 16 having a thickness of 10 to 15 μm is interposed between the wirings 18a, 18b and 18ab.
It can be said that b and 18ab are in an environment where cracks and disconnections are unlikely to occur, but when further thinning is desired in the future and the thickness of the interlayer insulating film 16 is set to about 2 to 3 μm, the electrode surface 22 Semiconductor chips 13C, 13 with chamfered ridgelines
It is considered that the wafer-like sheet 10 or the chip-like electronic component 1 of the present invention using D becomes more effective.
【００２８】（実施例２）実施例１のウェーハ状シート
１０ないしはチップ状電子部品１で使用されている半導
体チップ１３Ｃ、１３Ｄは次に示すような方法で電極面
２２の稜線の面取りを施した。図３はその面取り加工の
ステップを示す図である。すなわち、図３のＡは例えば
半導体チップ１３Ｃを切り出す前のシリコンウェーハ１
１の断面図である。そして、図３のＢに示すように、こ
のシリコンウェーハ１１内に作り込まれている半導体チ
ップの電極側の面の所定の位置に、デュアル・ダイサー
の一段目のブレードとして取り付けた、先端断面が角度
９０度のＶ字形状で、幅１００〜１２０μｍ程度の厚刃
ブレード３６を当てがいハーフカットした状態を示す。
続いて、図３のＣは、厚刃ブレード６でカットされた溝
の中央底部から裏面側までを、幅３０〜４０μｍ程度の
通常の細刃ブレード３８によってフルカットした状態を
示す図であり、ダイシングされた半導体ウェーハ１３Ｃ
は電極面２２の稜線が面取り角度４５度に面取りされ
て、電極面２２と側面２３とに交差する傾斜平面２５が
形成された状態で得られる。すなわち、二段カットして
ダイシングする場合の一段目のカットに適切なブレード
を選択することにより、シリコンウェーハ５から半導体
チップ１３Ｃを通常的な二段カットでダイシングするだ
けで、電極面２２の稜線２４が面取りされた半導体チッ
プ１３Ｃが得られるので、面取り加工によるコストの上
昇は無いに等しい。(Embodiment 2) The semiconductor chips 13C and 13D used in the wafer-shaped sheet 10 or the chip-shaped electronic component 1 of Embodiment 1 are chamfered on the ridge line of the electrode surface 22 by the following method. . FIG. 3 is a diagram showing steps of the chamfering process. That is, FIG. 3A shows, for example, the silicon wafer 1 before cutting the semiconductor chip 13C.
2 is a sectional view of FIG. Then, as shown in FIG. 3B, the tip cross section attached as a first stage blade of the dual dicer is attached at a predetermined position on the electrode side surface of the semiconductor chip formed in the silicon wafer 11. It shows a state in which a thick blade 36 having a V-shape with an angle of 90 degrees and a width of about 100 to 120 μm is applied and half-cut.
Subsequently, FIG. 3C is a diagram showing a state in which the central bottom portion of the groove cut by the thick blade blade 6 to the back surface side is fully cut by a normal fine blade blade 38 having a width of about 30 to 40 μm, Dicing semiconductor wafer 13C
Is obtained in a state where the ridgeline of the electrode surface 22 is chamfered at a chamfering angle of 45 degrees, and an inclined flat surface 25 intersecting the electrode surface 22 and the side surface 23 is formed. That is, the ridge line of the electrode surface 22 can be obtained by simply dicing the semiconductor chip 13C from the silicon wafer 5 by a normal two-step cut by selecting an appropriate blade for the first-step cut in the two-step cut and dicing. Since the semiconductor chip 13C having the chamfered portion 24 is obtained, the chamfering process does not increase the cost.
【００２９】（実施例３）実施例２においては、図３の
Ｃに示したように、面取り角４５度の傾斜平面２５が形
成されるよう、半導体チップ１３Ｃの電極面２２の稜線
を面取りしたものであるが、電極面２２と傾斜平面２５
との間に内角１３５度の稜線２６、および傾斜平面２５
と側面２３の間に内角１３５度の稜線２７が新たに形成
されて残る。図４は、電極面２２の稜線の面取り後に如
何なる稜線も残らないように、稜線を凸曲面で面取り
し、電極面２２と側面２３との間を連続的な凸曲面２８
で繋いだ半導体チップ１３Ｃ’を製造するステップを示
す図である。(Embodiment 3) In Embodiment 2, as shown in FIG. 3C, the ridge line of the electrode surface 22 of the semiconductor chip 13C is chamfered so that the inclined flat surface 25 having the chamfering angle of 45 degrees is formed. However, the electrode surface 22 and the inclined flat surface 25
A ridge 26 having an internal angle of 135 degrees between the and
A ridge line 27 having an internal angle of 135 degrees is newly formed and remains between the side surface 23 and the side surface 23. In FIG. 4, the ridgeline is chamfered with a convex curved surface so that no ridgeline remains after chamfering the ridgeline of the electrode surface 22, and a continuous convex curved surface 28 is provided between the electrode surface 22 and the side surface 23.
It is a figure which shows the step which manufactures the semiconductor chip 13C 'connected by.
【００３０】すなわち、図４のＡは半導体チップ１３Ｃ
を切り出す前のシリコンウェーハ１１の断面図である。
そして、図４のＢに示すように、このシリコンウェーハ
１１内に作り込まれている半導体チップの電極側の面の
所定の位置に、デュアル・ダイサーの一段目のブレード
として取り付けた、先端のＶ字形状の両面が凹曲面とさ
れた厚刃ブレード３７を当てがいハーフカットした状態
を示す。続いて、図４のＣは、厚刃ブレード３７でカッ
トされた溝の中央底部から裏面側までを、通常の細刃ブ
レード３８によってフルカットした状態を示す図であ
り、ダイシングされた半導体ウェーハ１３Ｃ’は電極面
２２の稜線２４が滑らかな凸曲面２８で面取りされたも
のとなる。そしてこのような半導体ウェーハ１３Ｃ’を
使用して製造されるウェーハ状シートやチップ状電子部
品は雰囲気温度の上昇、下降に起因する配線１８ａｂ、
１８ａ、１８ｂのクラックないしは断線を最も効果的に
抑制する。That is, FIG. 4A shows the semiconductor chip 13C.
It is sectional drawing of the silicon wafer 11 before cutting out.
Then, as shown in FIG. 4B, the tip V which is attached as a first stage blade of the dual dicer to a predetermined position on the electrode side surface of the semiconductor chip formed in the silicon wafer 11 A state in which a thick blade blade 37 whose both sides are shaped like a concave curve is applied and half-cut is shown. Subsequently, FIG. 4C is a view showing a state in which the central bottom portion of the groove cut by the thick blade blade 37 to the back surface side is fully cut by the normal thin blade blade 38, and the dicing semiconductor wafer 13C is shown. ′ Means that the ridgeline 24 of the electrode surface 22 is chamfered with a smooth convex curved surface 28. Wafer-shaped sheets and chip-shaped electronic components manufactured using such a semiconductor wafer 13C ′ have wirings 18ab due to rise and fall of ambient temperature,
The cracks or disconnection of 18a and 18b are most effectively suppressed.
【００３１】以上、本発明のウェーハ状シート、チップ
状電子部品、およびそれらの製造方法を実施例によって
説明したが、勿論、本発明はこれらに限られることな
く、本発明の技術的思想に基づいて種々の変形が可能で
ある。Although the wafer-shaped sheet, the chip-shaped electronic component, and the manufacturing method thereof according to the present invention have been described above with reference to the embodiments, the present invention is not limited to these and is based on the technical idea of the present invention. And various modifications are possible.
【００３２】例えば本実施例においては、チップ状電子
部品として、二種の半導体チップを１個にパッケージし
たＭＣＭのチップ状電子部品を例示したが、単一品種で
複数個の半導体チップをパッケージしたチップ状電子部
品も含む。勿論、１個の半導体チップを含むものであっ
てもよい。また本実施例においては、シリコンが主体の
複数の半導体チップと比較して熱膨張係数の大きい連続
相の合成樹脂としてエポキシ樹脂が使用されたチップ状
電子部品とを例示したが、エポキシ樹脂に換えてポリイ
ミド樹脂、ポリイミドアミド樹脂等の耐熱性高分子が使
用され得る。また、ウェーハ状シートの製造において連
続相のエポキシ樹脂は塗布し硬化して適用されものとし
て説明したが、半導体チップと一体成形したエポキシ樹
脂であってもよい。For example, in this embodiment, as the chip-shaped electronic component, an MCM chip-shaped electronic component in which two kinds of semiconductor chips are packaged into one is exemplified, but a plurality of semiconductor chips are packaged in a single type. Including chip-shaped electronic components. Of course, it may include one semiconductor chip. Further, in the present embodiment, a chip-shaped electronic component in which an epoxy resin is used as a continuous phase synthetic resin having a large thermal expansion coefficient as compared with a plurality of semiconductor chips mainly composed of silicon is exemplified. For example, a heat resistant polymer such as a polyimide resin or a polyimide amide resin may be used. Further, in the production of the wafer-shaped sheet, the continuous phase epoxy resin is applied, cured and applied, but the epoxy resin integrally molded with the semiconductor chip may be used.
【００３３】また本実施例においては、半導体チップの
平面形状が正方形または長方形のものを例示したが、例
えば正六角形や円形の平面形状を有するものであっても
よく、半導体チップの平面形状は限定されない。勿論、
立体形状も限定されない。また本実施例においては、半
導体チップ上に単層の配線が設けられる場合に付いて説
明したが、多層配線が設けられるものであってもよい。In this embodiment, the semiconductor chip having a square or rectangular planar shape is exemplified, but the semiconductor chip may have a regular hexagonal or circular planar shape, and the planar shape of the semiconductor chip is limited. Not done. Of course,
The three-dimensional shape is also not limited. Further, in the present embodiment, the case where the single layer wiring is provided on the semiconductor chip has been described, but the multilayer wiring may be provided.
【００３４】[0034]
【発明の効果】本発明のウェーハ状シート、チップ状電
子部品、およびそれらの製造方法は以上に説明したよう
な形態で実施され、次に述べるような効果を奏する。The wafer-shaped sheet, the chip-shaped electronic component, and the manufacturing method thereof according to the present invention are carried out in the form as described above, and have the following effects.
【００３５】請求項１のウェーハ状シートによれば、使
用されている半導体チップは電極面と側面との間の稜線
が面取りされているので、温度の上昇、下降によって反
りと復元が繰り返されても、稜線部分で小さい曲率半径
に折り曲げられることはなく、近傍の配線にクラックや
断線を招かない。According to the wafer-shaped sheet of the first aspect, since the ridge line between the electrode surface and the side surface of the used semiconductor chip is chamfered, warping and restoration are repeated due to temperature rise and fall. However, the ridge portion is not bent to have a small radius of curvature, and the adjacent wiring is not cracked or broken.
【００３６】請求項２のウェーハ状シートによれば、半
導体チップをシリコンウェーハからダイシングする時
に、先端断面がＶ字形状の厚刃ブレードを用いて半導体
チップの電極面側からシリコンウェーハをハーフカット
し、続いて細刃ブレードによってハーフカットの中央底
部から反対面までをフルカットすることにより、電極面
の稜線が自ら面取りされた半導体チップを使用している
ので、面取りしたものを使用することによるコスト上昇
はない。According to the wafer-shaped sheet of claim 2, when dicing a semiconductor chip from a silicon wafer, the silicon wafer is half-cut from the electrode surface side of the semiconductor chip by using a thick blade having a V-shaped tip cross section. , Then, by fully cutting from the center bottom part of the half cut to the opposite surface with a thin blade, the ridge line of the electrode surface uses a chamfered semiconductor chip itself, so the cost of using a chamfered one There is no rise.
【００３７】請求項３のチップ状電子部品によれば、使
用されている半導体チップは電極面と側面との間の稜線
が面取りされているので、温度の上昇、下降によって反
りと復元が繰り返されても、稜線部分で小さい曲率半径
に折り曲げられることはなく、近傍の配線にクラックや
断線を招かない。According to the chip-shaped electronic component of claim 3, since the ridge line between the electrode surface and the side surface of the used semiconductor chip is chamfered, warping and restoration are repeated due to temperature rise and fall. However, the ridgeline portion is not bent to have a small radius of curvature, and the adjacent wiring is not cracked or broken.
【００３８】請求項４のチップ状電子部品によれば、半
導体チップをシリコンウェーハからダイシングする時
に、先端断面がＶ字形状の厚刃ブレードを用いて半導体
チップの電極面側からシリコンウェーハをハーフカット
し、続いて細刃ブレードによってハーフカットの中央底
部から反対面までをフルカットすることにより、電極面
の稜線が自ら面取りされた半導体チップを使用している
ので、面取りしたものを使用することによるコスト上昇
はない。According to the chip-shaped electronic component of claim 4, when the semiconductor chip is diced from the silicon wafer, the silicon wafer is half-cut from the electrode surface side of the semiconductor chip by using a thick blade having a V-shaped cross section. Then, by fully cutting from the center bottom part of the half cut to the opposite surface with a fine blade, the ridge line of the electrode surface uses the chamfered semiconductor chip itself, so by using the chamfered one There is no cost increase.
【００３９】請求項５のウェーハ状シート製造方法によ
れば、シリコンウェーハからのダイシング時に電極面の
稜線が自ら面取りされた半導体チップを使用するので、
製造されるウェーハ状シートは温度の上昇、下降によっ
て反りと復元が繰り返されても、稜線部分で小さい曲率
半径に折り曲げられることはなく、従って近傍の配線に
クラックや断線を招かず、また、面取りされた半導体チ
ップを使用することによるウェーハ状シートのコスト上
昇もない。According to the wafer-like sheet manufacturing method of the fifth aspect, since the semiconductor chip in which the ridgeline of the electrode surface is chamfered by itself is used during dicing from the silicon wafer,
Even if the manufactured wafer-shaped sheet is repeatedly warped and restored due to temperature rise and fall, it will not be bent to a small radius of curvature at the ridge portion, so it will not cause cracks or breaks in the wiring in the vicinity and chamfering. There is no increase in the cost of the wafer-like sheet due to the use of the semiconductor chip thus manufactured.
【００４０】請求項６のチップ状電子部品の製造方法に
よれば、シリコンウェーハからのダイシング時に、電極
面の稜線が自ら面取りされた半導体チップを使用するの
で、製造されるチップ状電子部品は温度の上昇、下降に
よって反りと復元が繰り返されても、稜線部分で小さい
曲率半径に折り曲げられることはなく、従って近傍の配
線にクラックや断線を招かず、また、面取りされた半導
体チップを使用することによるウェーハ状シートのコス
ト上昇もない。According to the method for manufacturing a chip-shaped electronic component of claim 6, since the semiconductor chip in which the ridgeline of the electrode surface is chamfered by itself is used during dicing from the silicon wafer, the manufactured chip-shaped electronic component is not Even if warping and restoration are repeated by rising and falling, the ridge does not bend to a small radius of curvature, so it does not cause cracks or disconnections in nearby wiring, and use chamfered semiconductor chips. There is no increase in the cost of the wafer-like sheet due to.
【図１】実施例のＭＣＭ化させたチップ状電子部品の断
面図である。FIG. 1 is a cross-sectional view of an MCM-type chip-shaped electronic component of an example.
【図２】電極面の稜線が面取りされない半導体チップと
面取りされた半導体チップの形状を並べて示す図であ
り、Ａは平面図、ＢはＡにおける［Ｂ］−［Ｂ］線方向
の断面図である。2A and 2B are views showing side by side the shapes of a semiconductor chip in which a ridgeline of an electrode surface is not chamfered and a chamfered semiconductor chip. is there.
【図３】シリコンウェーハの二段カットのダイシングに
よって半導体チップが面取りされる過程を示す断面図で
あり、Ａはシリコンウェーハ、Ｂは先端断面が直線的な
Ｖ字形状の厚刃ブレードによってハーフカットした状
態、続くＣはハーフカットした底部中央から反対面まで
を細刃ブレードによってフルカットすることにより、半
導体チップの稜線が自ら面取りされた状態を示す。FIG. 3 is a cross-sectional view showing a process in which a semiconductor chip is chamfered by dicing a two-step cut of a silicon wafer, where A is a silicon wafer and B is a half-cut by a V-shaped thick blade blade having a linear tip cross section. The state C is a state in which the edge line of the semiconductor chip is chamfered by itself by fully cutting from the center of the half-cut bottom portion to the opposite surface with a fine blade.
【図４】図３と同様な図であり、厚刃ブレードの先端断
面を内側へ凹曲面のＶ字形状とした場合のダイシングを
示す断面図である。FIG. 4 is a view similar to FIG. 3, and is a cross-sectional view showing dicing when the tip cross-section of the thick blade blade is inwardly curved into a V-shape.
【図５】図６と共にウェーハ状シートの製造工程をステ
ップ的に示す断面図であり、Ａは半導体チップを粘着さ
せるための粘着性シートが固定された石英基板を示し、
Ｂは粘着性シートに半導体チップをフェイスダウンに粘
着させた状態、Ｃは半導体チップを含む全面にエポキシ
樹脂を適用して硬化させた状態、Ｄは石英基板側から紫
外線照射して粘着剤を硬化させ粘着性を失わせて、半導
体チップとエポキシ樹脂からなるウェーハ状シートを剥
離した状態を示す。FIG. 5 is a cross-sectional view showing a step of manufacturing a wafer-shaped sheet together with FIG. 6, wherein A shows a quartz substrate to which an adhesive sheet for adhering a semiconductor chip is fixed,
B is a state where the semiconductor chip is face-down adhered to the adhesive sheet, C is a state where epoxy resin is applied to the entire surface including the semiconductor chip and cured, and D is ultraviolet irradiation from the quartz substrate side to cure the adhesive. Then, the adhesive property is lost and the wafer-like sheet made of the semiconductor chip and the epoxy resin is peeled off.
【図６】図５に続いて、Ａはウェーハ状シートの上下を
裏返しにした状態、Ｂは全面に層間絶縁膜を設けビアホ
ールを開孔した状態、Ｃは層間絶縁膜の上に配線を形成
した状態、Ｄはオーバーコート膜を設けて、配線の電極
パッドを露出させた状態を示す。FIG. 6 is a continuation of FIG. 5, in which A is a state in which the upper and lower sides of the wafer-like sheet are turned upside down, B is a state in which an interlayer insulating film is provided on the entire surface and a via hole is opened, and C is a wiring formed on the interlayer insulating film. In the state D, the overcoat film is provided to expose the electrode pads of the wiring.
【図７】図５のＢに対応する斜視図であり、粘着性シー
トに半導体チップを並べて配置した状態を示す。FIG. 7 is a perspective view corresponding to FIG. 5B, showing a state in which semiconductor chips are arranged side by side on an adhesive sheet.
【図８】従来例のＭＣＭ化された半導体チップの実装状
態を示す図であり、Ａは斜視図、Ｂは側面図である。8A and 8B are views showing a mounting state of a semiconductor chip that has been converted to an MCM in a conventional example, in which A is a perspective view and B is a side view.
【図９】他の従来例のＭＣＭ化された半導体チップの実
装状態を示す図であり、Ａは斜視図、Ｂは部分破断側面
図である。9A and 9B are views showing a mounting state of another conventional MCM semiconductor chip, in which A is a perspective view and B is a partially cutaway side view.
１……チップ状電子部品、３……石英基板、４……粘着
性シート、１０……ウェーハ状シート、１１……シリコ
ンウェーハ、１２……エポキシ樹脂、１３Ｃ、１３Ｄ…
…半導体チップ、１６……層間絶縁膜、１８ａ、１８
ｂ、１８ａｂ……配線、２１ａ、２１ｂ……電極パッ
ド、２２ａ、２２ｂ……電極面、２３……側面、３６、
３７……厚刃ブレード、３８……薄刃ブレード。1 ... Chip-shaped electronic parts, 3 ... Quartz substrate, 4 ... Adhesive sheet, 10 ... Wafer sheet, 11 ... Silicon wafer, 12 ... Epoxy resin, 13C, 13D ...
... Semiconductor chip, 16 ... Interlayer insulating film, 18a, 18
b, 18ab ... Wiring, 21a, 21b ... Electrode pad, 22a, 22b ... Electrode surface, 23 ... Side surface, 36,
37 ... thick blade, 38 ... thin blade.
Claims (6)
体チップと、前記半導体チップの電極面以外の底面およ
び側面を覆い連結する連続相の合成樹脂層と、前記電極
面側に層間絶縁膜を介して形成された配線層とを有する
ウェーハ状シートにおいて、 前記半導体チップの前記電極面と前記側面との間の稜線
が面取りされていることを特徴とするウェーハ状シー
ト。1. A plurality of semiconductor chips arranged at a predetermined pitch, a continuous-phase synthetic resin layer covering and connecting a bottom surface and side surfaces other than the electrode surface of the semiconductor chip, and an interlayer insulating film on the electrode surface side. A wafer-like sheet having a wiring layer formed through the above, wherein a ridgeline between the electrode surface and the side surface of the semiconductor chip is chamfered.
コンウェーハから切り出すダイシング時に、先端断面が
Ｖ字形状の厚刃ブレードを用いて前記半導体チップの電
極面側から前記シリコンウェーハをハーフカットし、続
いて細刃ブレードによってハーフカットの中央底部から
反対面までをフルカットして施されたものであることを
特徴とする請求項１に記載のウェーハ状シート。2. The chamfering, when dicing to cut the semiconductor chip from the silicon wafer, half-cuts the silicon wafer from the electrode surface side of the semiconductor chip using a thick blade blade having a V-shaped cross section, The wafer-like sheet according to claim 1, wherein the wafer-like sheet is formed by performing full cutting from a central bottom portion of the half cut to the opposite surface with a fine blade.
体チップと、前記半導体チップの電極面以外の底面およ
び側面を覆い連結する連続相の合成樹脂層と、前記電極
面側に層間絶縁膜を介して形成された配線層とを有する
ウェーハ状シートを、単数または複数の前記半導体チッ
プが含まれるように、ダイシングして得られるチップ状
電子部品において、 前記半導体チップの前記電極面と前記側面との間の稜線
が面取りされていることを特徴とするチップ状電子部
品。3. A plurality of semiconductor chips arranged at a predetermined pitch, a continuous phase synthetic resin layer that covers and connects bottom surfaces and side surfaces other than the electrode surface of the semiconductor chip, and an interlayer insulating film on the electrode surface side. In a chip-shaped electronic component obtained by dicing a wafer-shaped sheet having a wiring layer formed via, so as to include one or more of the semiconductor chips, the electrode surface and the side surface of the semiconductor chip. A chip-shaped electronic component, characterized in that a ridgeline between and is chamfered.
コンウェーハから切り出すダイシング時に、先端断面が
Ｖ字形状の厚刃ブレードを用いて前記半導体チップの電
極面側から前記シリコンウェーハをハーフカットし、続
いて細刃ブレードによってハーフカットの中央底部から
反対面までをフルカットして施されたものであることを
特徴とする請求項３に記載のチップ状電子部品。4. The chamfering, when dicing to cut out the semiconductor chip from the silicon wafer, half-cuts the silicon wafer from the electrode surface side of the semiconductor chip using a thick blade blade having a V-shaped cross section, The chip-shaped electronic component according to claim 3, wherein the chip-shaped electronic component is formed by fully cutting from a central bottom portion of the half cut to the opposite surface with a fine blade.
シートを平板上に粘着面を上向きに固定する工程と、前
記粘着性シート上に複数の半導体チップを所定のピッチ
で電極面を下向きに粘着させる工程と、前記半導体チッ
プを含む前記粘着性シートの全面に合成樹脂層を形成す
る工程と、前記粘着性シートの粘着力を低下させて前記
半導体チップと共に前記合成樹脂層を前記粘着性シート
から剥離する工程と、前記電極面側に層間絶縁膜を介し
て配線層を形成する工程とを有するウェーハ状シートの
製造方法において、 前記半導体チップとして、前記半導体チップをシリコン
ウェーハから切り出すダイシング時に、先端断面がＶ字
形状の厚刃ブレードを用いて前記半導体チップの電極面
側から前記シリコンウェーハをハーフカットし、続いて
細刃ブレードによってハーフカットの中央底部から反対
面までをフルカットしたものを使用することを特徴とす
るウェーハ状シートの製造方法。5. A step of fixing a pressure-sensitive adhesive sheet capable of reducing the pressure-sensitive adhesive force on a flat plate with the pressure-sensitive adhesive surface facing upward, and a plurality of semiconductor chips on the pressure-sensitive adhesive sheet facing downward with an electrode surface at a predetermined pitch. And a step of forming a synthetic resin layer on the entire surface of the adhesive sheet including the semiconductor chip, the adhesive force of the adhesive sheet is reduced to reduce the adhesive strength of the synthetic resin layer together with the semiconductor chip. In a method for manufacturing a wafer-shaped sheet having a step of peeling from a sheet, and a step of forming a wiring layer on the electrode surface side via an interlayer insulating film, as the semiconductor chip, at the time of dicing to cut the semiconductor chip from a silicon wafer , Using a thick blade having a V-shaped cross section, the silicon wafer is half-cut from the electrode surface side of the semiconductor chip, Wafer sheet manufacturing method, characterized by using a material obtained by full cut to the opposite side from the bottom middle of the half-cut by Hosoha blade.
シートを平板上に粘着面を上向きに固定する工程と、前
記粘着性シート上に複数の半導体チップを所定のピッチ
で電極面を下向きに粘着させる工程と、前記半導体チッ
プを含む前記粘着性シートの全面に合成樹脂層を形成す
る工程と、前記粘着性シートの粘着力を低下させて前記
半導体チップと共に前記合成樹脂層を前記粘着性シート
から剥離する工程と、前記電極面側に層間絶縁膜を介し
て配線層を形成する工程とによって得られるウェーハ状
シートを、単数または複数の前記半導体チップが含まれ
るようにダイシングするチップ状電子部品の製造方法に
おいて、 前記半導体チップとして、前記半導体チップをシリコン
ウェーハから切り出すダイシング時に、先端断面がＶ字
形状の厚刃ブレードを用いて前記半導体チップの電極面
側から前記シリコンウェーハをハーフカットし、続いて
細刃ブレードによってハーフカットの中央底部から反対
面までをフルカットしたものを使用することを特徴とす
るチップ状電子部品の製造方法。6. A step of fixing a pressure-sensitive adhesive sheet capable of reducing the pressure-sensitive adhesive force on a flat plate with the pressure-sensitive adhesive surface facing upward, and a plurality of semiconductor chips on the pressure-sensitive adhesive sheet facing downward with a predetermined pitch of the electrode surface. And a step of forming a synthetic resin layer on the entire surface of the adhesive sheet including the semiconductor chip, the adhesive force of the adhesive sheet is reduced to reduce the adhesive strength of the synthetic resin layer together with the semiconductor chip. Chip-shaped electronic for dicing a wafer-shaped sheet obtained by a step of peeling from a sheet and a step of forming a wiring layer on the electrode surface side via an interlayer insulating film so as to include one or a plurality of the semiconductor chips. In the method of manufacturing a component, as the semiconductor chip, a thickness of a V-shaped tip cross section is obtained when dicing the semiconductor chip from a silicon wafer. Half-cutting the silicon wafer from the electrode surface side of the semiconductor chip using a blade, then using a thin blade to fully cut from the center bottom of the half-cut to the opposite surface Electronic component manufacturing method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2001319542A JP2003124431A (en) | 2001-10-17 | 2001-10-17 | Wafer-form sheet, a chip-form electronic part, and their manufacturing method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2001319542A JP2003124431A (en) | 2001-10-17 | 2001-10-17 | Wafer-form sheet, a chip-form electronic part, and their manufacturing method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JP2003124431A true JP2003124431A (en) | 2003-04-25 |
Family
ID=19137074
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2001319542A Pending JP2003124431A (en) | 2001-10-17 | 2001-10-17 | Wafer-form sheet, a chip-form electronic part, and their manufacturing method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2003124431A (en) |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2008142763A1 (en) * | 2007-05-18 | 2008-11-27 | Kabushiki Kaisha Nihon Micronics | Stacked package and method of forming stacked package |
| JP2012531058A (en) * | 2009-06-25 | 2012-12-06 | アイメック | Biocompatible packaging |
| WO2013145555A1 (en) * | 2012-03-30 | 2013-10-03 | 国立大学法人東北大学 | Integrated device |
| JP2014168096A (en) * | 2009-06-24 | 2014-09-11 | Intel Corp | Multi-chip package, and method of providing die-to-die interconnects in multi-chip package |
| JP2020517089A (en) * | 2016-12-23 | 2020-06-11 | ボード・オブ・リージエンツ，ザ・ユニバーシテイ・オブ・テキサス・システム | Heterogeneous integration of components into compact devices using moire-based metrology and vacuum-based pick-and-place |
| JP2021150537A (en) * | 2020-03-19 | 2021-09-27 | 株式会社東芝 | Semiconductor device and manufacturing method for the same |
| US11824032B2 (en) * | 2021-03-18 | 2023-11-21 | Taiwan Semiconductor Manufacturing Company Limited | Die corner removal for underfill crack suppression in semiconductor die packaging |
-
2001
- 2001-10-17 JP JP2001319542A patent/JP2003124431A/en active Pending
Cited By (17)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2008142763A1 (en) * | 2007-05-18 | 2008-11-27 | Kabushiki Kaisha Nihon Micronics | Stacked package and method of forming stacked package |
| US11824008B2 (en) | 2009-06-24 | 2023-11-21 | Intel Corporation | Multi-chip package and method of providing die-to-die interconnects in same |
| JP2014168096A (en) * | 2009-06-24 | 2014-09-11 | Intel Corp | Multi-chip package, and method of providing die-to-die interconnects in multi-chip package |
| US9875969B2 (en) | 2009-06-24 | 2018-01-23 | Intel Corporation | Multi-chip package and method of providing die-to-die interconnects in same |
| US10510669B2 (en) | 2009-06-24 | 2019-12-17 | Intel Corporation | Multi-chip package and method of providing die-to-die interconnects in same |
| US10763216B2 (en) | 2009-06-24 | 2020-09-01 | Intel Corporation | Multi-chip package and method of providing die-to-die interconnects in same |
| US10923429B2 (en) | 2009-06-24 | 2021-02-16 | Intel Corporation | Multi-chip package and method of providing die-to-die interconnects in same |
| US11876053B2 (en) | 2009-06-24 | 2024-01-16 | Intel Corporation | Multi-chip package and method of providing die-to-die interconnects in same |
| JP2012531058A (en) * | 2009-06-25 | 2012-12-06 | アイメック | Biocompatible packaging |
| WO2013145555A1 (en) * | 2012-03-30 | 2013-10-03 | 国立大学法人東北大学 | Integrated device |
| JP2013211365A (en) * | 2012-03-30 | 2013-10-10 | Tohoku Univ | Integrated device |
| US9478503B2 (en) | 2012-03-30 | 2016-10-25 | Tohoku University | Integrated device |
| JP2020517089A (en) * | 2016-12-23 | 2020-06-11 | ボード・オブ・リージエンツ，ザ・ユニバーシテイ・オブ・テキサス・システム | Heterogeneous integration of components into compact devices using moire-based metrology and vacuum-based pick-and-place |
| JP7348062B2 (en) | 2016-12-23 | 2023-09-20 | ボード オブ リージェンツ，ザ ユニバーシティ オブ テキサス システム | Heterogeneous integration of components into compact devices using moiré-based metrology and vacuum-based pick-and-place |
| JP7282710B2 (en) | 2020-03-19 | 2023-05-29 | 株式会社東芝 | Semiconductor device manufacturing method |
| JP2021150537A (en) * | 2020-03-19 | 2021-09-27 | 株式会社東芝 | Semiconductor device and manufacturing method for the same |
| US11824032B2 (en) * | 2021-03-18 | 2023-11-21 | Taiwan Semiconductor Manufacturing Company Limited | Die corner removal for underfill crack suppression in semiconductor die packaging |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US7944049B2 (en) | Semiconductor device and manufacturing method thereof | |
| US6737300B2 (en) | Chip scale package and manufacturing method | |
| JP4659660B2 (en) | Manufacturing method of semiconductor device | |
| US7361972B2 (en) | Chip packaging structure for improving reliability | |
| US8253258B2 (en) | Semiconductor device with hollow and throughhole and method of manufacturing same | |
| US8802507B2 (en) | Fabrication method of semiconductor package device, and fabrication method of semiconductor package structure | |
| US10978408B2 (en) | Semiconductor package and manufacturing method thereof | |
| US7148081B2 (en) | Method of manufacturing a semiconductor device | |
| JP5543086B2 (en) | Semiconductor device and manufacturing method thereof | |
| US20110209908A1 (en) | Conductor package structure and method of the same | |
| JP5518789B2 (en) | Multi-chip module | |
| TW201511209A (en) | Semiconductor device and method of manufacturing the semiconductor device | |
| JP2009049410A (en) | Semiconductor chip package, manufacturing method thereof, and electronic element comprising the same | |
| US10811384B2 (en) | Semiconductor package and method of manufacturing the same | |
| TW201903992A (en) | Package structure and manufacturing method thereof | |
| KR20150060758A (en) | Semiconductor device and method for manufacturing same | |
| JP2012009655A (en) | Semiconductor package and method of manufacturing the semiconductor package | |
| JP2002299546A (en) | Chip-like electronic component, manufacturing method therefor, pseudo wafer used for manufacturing and manufacturing method therefor | |
| JP2003124431A (en) | Wafer-form sheet, a chip-form electronic part, and their manufacturing method | |
| JP3618330B2 (en) | Semiconductor device and manufacturing method thereof | |
| US20070114672A1 (en) | Semiconductor device and method of manufacturing the same | |
| JP2005142452A (en) | Semiconductor device and its manufacturing method | |
| JP4131256B2 (en) | Semiconductor device and manufacturing method thereof | |
| JP4214969B2 (en) | Manufacturing method of semiconductor device | |
| JP6988360B2 (en) | Manufacturing method of semiconductor device and semiconductor device |