JP4131256B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

This invention relates to a method of manufacturing a semiconductor device and its, more particularly, to a semiconductor device and its manufacturing method having a structure corresponding to a further increase of the external terminals.

  In recent years, further reduction in size and thickness of packaged semiconductor devices has been demanded. In order to meet this requirement, a package form called a wafer level chip size package (hereinafter also simply referred to as WCSP) in which the outer size of the package is substantially the same as the outer size of the semiconductor chip. Has been proposed.

  The WCSP includes a semiconductor chip. The semiconductor chip includes a circuit element having a predetermined function and a plurality of electrode pads electrically connected to the circuit element. An insulating film is formed on the first main surface so as to expose the plurality of electrode pads.

  On the surface of the insulating film, a plurality of wiring patterns connected to the exposed electrode pads are formed.

  Electrode posts are formed on these wiring patterns. A sealing portion is formed so as to cover the insulating film and the wiring pattern and to expose the top surface of the electrode post.

  Furthermore, on the top surface of the electrode post, for example, in the case of a BGA package, a plurality of external terminals provided as solder balls are provided.

  As described above, the WCSP has a fan-in structure in which a plurality of external terminals are provided, for example, in a lattice shape in a region corresponding to the circuit formation surface of the semiconductor chip.

In mounting a semiconductor chip having an external terminal of such a structure on a printed board, a semiconductor chip having an electrode pad for the purpose of preventing the occurrence of breakage at the connection portion between the printed board and the external terminal; A wiring formed at a predetermined position on the semiconductor chip and connected to the electrode pad, an external terminal formed at a predetermined position on the wiring and connected to the wiring, a printed board connected to the external terminal, and a semiconductor A structure having a substrate formed on a chip and having a resin layer on the substrate for matching the thermal expansion of the substrate and the printed board, particularly a structure in which external terminals are provided on the resin layer There is known a semiconductor device that takes the following (for example, see Patent Document 1).
JP 2000-208556 A (Claims and FIG. 5)

  As the functionality of semiconductor devices increases, the number of external terminals formed in one packaged semiconductor device tends to increase. Conventionally, such a demand for an increase in the number of external terminals is addressed by a configuration in which the interval between adjacent external terminals is narrowed. Regarding the arrangement interval and arrangement position of the external terminals, the degree of freedom of design is remarkably limited as described below.

  In the conventional WCSP described above, the minimum interval between adjacent external terminals is specifically about 0.5 mm. In the case of a 7 mm × 7 mm square WCSP, the number of external terminals provided is about 160.

  Due to the demand for further increase in external terminals of packaged semiconductor devices, it is desired to provide about 300 external terminals on a 7 mm × 7 mm square WCSP.

  In the WCSP described above, it is technically impossible to form a larger number of external electrodes on the surface of the WCSP by narrowing the interval between adjacent external terminals.

  However, it is quite difficult to form 300 external terminals on the surface area of a 7 mm × 7 mm square WCSP. Further, if the interval between the external terminals is reduced, an extremely advanced technique is required to mount the WCSP on the mounting substrate.

  For example, it may be required to form the intervals between the plurality of external terminals within a range of about 0.3 mm to 0.7 mm according to the mounting pitch of the mounting substrate.

  In such a case, in a conventional package configuration, a semiconductor chip is connected on a substrate by so-called flip chip connection, and the semiconductor chip is connected to an external terminal through the substrate or by wire bonding. The semiconductor chip is connected to the external terminal through the substrate. Since any of the connection methods uses a substrate, and an extra sealing material for the height of the wire loop is required, the package becomes thick. Furthermore, the cost of the substrate increases, and the package becomes expensive. In particular, in the case of flip chip connection, a more expensive build-up substrate is required, so that the package becomes more expensive.

  On the other hand, when the connection by wire bonding is performed, the inductance of the wire portion is increased.

  SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a semiconductor device having a configuration capable of increasing the degree of freedom in designing the arrangement intervals and arrangement positions of external terminals and making the package itself compact.

The semiconductor device of the present invention has the following structural features.
That is, the semiconductor device includes a first main surface provided with a plurality of electrode pads, a second main surface facing the first main surface, and between the first main surface and the second main surface. A semiconductor chip having a plurality of side surfaces, a first surface, and a second surface opposite to the first surface, surrounding the semiconductor chip in contact with the side surfaces of the semiconductor chip, The surface is the same as the level of the first main surface, or is formed so as to have a level difference enough to form a wiring pattern on the upper side of the first surface and the upper side of the first main surface. The extension portion, a portion of the plurality of electrode pads exposed, an insulating film formed on the first surface and the first main surface, and electrically connected to each of the electrode pads, A plurality of wiring patterns led out from the electrode pad to the upper side of the first surface of the extended portion, A plurality of wiring patterns that are wider or thicker than other parts in a part located on the boundary between the first surface of the part and the first main surface of the semiconductor chip; A sealing portion formed by exposing a part of the wiring pattern on the wiring pattern and the insulating film, and a plurality of external terminals provided on the wiring pattern in a region including the upper side of the extension portion are provided.
Further, main steps of a method for manufacturing a semiconductor device of the present invention is as follows.

  A plurality of semiconductor chip placement areas where a plurality of semiconductor chips are placed are set at predetermined intervals on the ground.

  A first main surface having a plurality of electrode pads on a semiconductor chip arrangement region, a second main surface opposite to the first main surface, and the first main surface and the second main surface A semiconductor chip having one or more side surfaces in between is provided to face the second main surface.

The first surface and a second surface opposite to the first surface are provided on the ground, and surrounds the semiconductor chip in contact with the side surface of the semiconductor chip, and the level of the first surface is the first level. An extension portion is formed which is the same as the level of the main surface or has a level difference enough to form a wiring pattern on the upper side of the first surface and the upper side of the first main surface. To do.

  An insulating film is formed on the first surface and the first main surface of the extended portion so as to expose a part of the electrode pad.

In forming a plurality of wiring patterns electrically connected to each of the electrode pads on the insulating film and led out from the upper side of the first main surface to the upper side of the first surface of the extension portion , A plurality of wiring patterns are formed so that the width of the portion located on the boundary between the first surface of the extension portion and the first main surface of the semiconductor chip is wider than the other portions, or the thickness is increased. Form .

  On the insulating film on which the wiring pattern is formed, a sealing portion is formed by exposing a part of the wiring pattern located above the first surface of the wiring pattern.

  A plurality of external terminals are connected and formed on the wiring pattern in the region including the upper side of the extended portion so as to be individually electrically connected to each of the derived portions of the wiring pattern.

  A plurality of semiconductor chips are cut, and a semiconductor device including the semiconductor chips is separated.

  According to the configuration of the semiconductor device of the present invention, an external terminal can be provided on the extended portion provided so as to surround the side surface of the semiconductor chip to be mounted, that is, in the region including the expanded region. Since the fan-out structure or the fan-in / fan-out structure is possible, it is possible to increase the degree of design freedom such as the arrangement interval and arrangement position of the external terminals.

  Further, the semiconductor device of the present invention can be configured to directly connect the semiconductor chip and the external electrode without using an interposer such as a substrate by utilizing a so-called WCSP manufacturing process. In addition to the effect, the operation can be further speeded up, enhanced in function, multifunctional and compact in comparison with wire bonding connection. Further, in comparison with flip-chip connection, equivalent electrical characteristics can be obtained at a lower cost.

  According to the method for manufacturing a semiconductor device of the present invention, it is possible to provide a highly functional, multi-functional and compact semiconductor device by a simpler process. In particular, the degree of freedom in designing the arrangement interval and arrangement position of the external electrodes can be greatly increased.

  According to the second manufacturing method, a single jig can be used repeatedly. Since it is not necessary to use a base, members necessary for the manufacturing process can be reduced. Therefore, a reduction in manufacturing cost is expected. In addition, when the extension part and the semiconductor chip are configured to be sucked and held by the intake / exhaust system through the through hole, the extension part and the semiconductor chip can be easily and quickly held and peeled from the jig. Therefore, improvement of the throughput of the semiconductor device is expected.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the drawings, only the shapes, sizes, and arrangement relationships of the respective constituent components are schematically shown to such an extent that the present invention can be understood, and the present invention is not particularly limited thereby. In the following description, specific materials, conditions, numerical conditions, and the like may be used. However, these are merely preferred examples, and are not limited to these. In addition, it should be understood that the same constituent components are denoted by the same reference numerals in the drawings used for the following description, and redundant description thereof may be omitted.

  The semiconductor device of the present invention will be described with reference to FIGS. FIG. 1A is a schematic plan view as viewed from the top for explaining the structure of the semiconductor device, and FIG. 1B is a diagram for explaining the connection relationship between the wiring pattern and the electrode posts. It is the rough principal part top view which expanded and showed the partial area | region enclosed with the continuous line 11 of (A). 2 (A) and 2 (B) are schematic cross-sectional views showing a cut surface taken along the II broken line in FIG. 1 (A). FIG. 2A shows a configuration example in which the semiconductor device 10 of the present invention includes a base 12 on the bottom surface side. FIG. 2B shows a configuration example in which the base 12 is not provided.

  The semiconductor device 10 of the present invention includes a semiconductor chip 30 on a base 12. The semiconductor chip 30 includes a first main surface 36, a second main surface 38 opposite to the first main surface 36, and a space between the first main surface 36 and the second main surface 38. It has two or more side surfaces 37. The semiconductor chip 30 includes a circuit element having a predetermined function and a plurality of electrode pads 34 electrically connected to the circuit element. A plurality of electrode pads 34 are provided on the first main surface 36. The plurality of electrode pads 34 are formed along the periphery of the first main surface 36.

  The semiconductor chip 30 is provided on the base 12 such that the first main surface 36 is the upper surface, that is, the second main surface 38 faces the semiconductor chip arrangement region 14.

  The semiconductor device 10 of the present invention includes an extended portion 20 on a base 12. The extended portion 20 is provided so as to be in contact with and surround the side surface 37 of the semiconductor chip 30 disposed in the semiconductor chip arrangement region 14 on the base 12, that is, the surface other than the first and second main surfaces. ing. The extended portion 20 is formed such that the level (height, hereinafter the same) of the first surface 20a is substantially the same as the level of the first main surface 36 of the semiconductor chip 30. ing.

  The extended portion 20 can be appropriately selected from organic materials such as an epoxy resin and a silicone resin. That is, a so-called liquid resin or mold resin can be applied.

  In order to prevent the warpage occurring in the semiconductor device 10 of the present invention in the manufacturing process, the extended portion 20 is preferably formed of a material having a molding shrinkage larger than that of a sealing portion to be formed later. It is good.

  Here, “molding shrinkage” means shrinkage of a single material that occurs in the molding process. That is, “molding shrinkage” corresponds to the sum of curing shrinkage at the molding temperature and heat shrinkage from the molding temperature to the normal temperature.

Specifically, the expanded portion 20 is a liquid resin having a linear expansion coefficient in a temperature range lower than the glass transition point of less than 1.5 × 10 ⁻⁵ / ° C. and an elastic modulus in the range of 7.8 to 22 GPa. It is good to form by. The case where mold resin is applied to the extended portion 20 will be described later.

  An insulating film 40 is formed on the first surface 20a and the first main surface 36 of the extended portion 20 so that the plurality of electrode pads 34 are exposed.

  A plurality of wiring patterns 42 are formed on the surface of the insulating film 40 so as to be electrically connected to the exposed electrode pads 34.

  Sealing portions 44 are provided on the surface regions of the semiconductor chip 30 and the extended portion 20 so as to cover the wiring pattern 42 and the insulating film 40. The insulating film 40 and the sealing portion 44 described above are also collectively referred to as an insulating layer 48. Electrode posts 46 that penetrate the sealing portions 44 from the respective wiring patterns 42 and reach the surface of the sealing portions 44 are respectively provided. Some of these electrode posts 46 are provided on the upper side (directly above) of the semiconductor chip 30, and the remaining electrode posts 46 are provided on the upper side (directly above) of the extended portion 20. Normally, these electrode posts 46 are arranged at regular intervals. Further, the top surface of each electrode post 46 is exposed on the surface of the sealing portion 44. The electrode post 46 is also called a post electrode, and an external terminal 47 is provided on the exposed top surface. As the external terminal 47, a solder ball 47a is usually provided. The external terminals 47 are arranged with an interval wider than the arrangement interval of the electrode pads 34.

  Here, the connection relationship between the electrode pad 34 and the wiring pattern 42 will be described with reference to FIG. In order to facilitate understanding of these connection relationships, a partial region (region surrounded by a solid line) 11 in FIG. In the wiring pattern 42, an electrode post (shown by 46 in FIG. 2) that is connected to the lower portion of the external terminal 47 and the corresponding electrode pad 34 are regularly and electrically connected. For example, a long wiring 42a, a middle wiring 42b, and a short wiring 42c are provided as wirings constituting the wiring pattern 42. These wirings 42a, 42b and 42c are connected to the corresponding electrode pads 34 in this order in a one-to-one connection relationship of one wiring and one electrode pad.

  The wiring pattern 42 is provided so as to straddle the boundary between the region above (directly above) the semiconductor chip 30 and the region above (directly above) the extended portion 20, that is, the region of the expanded region 21. That is, at least a part of the plurality of wiring patterns 42 is electrically connected to each of the electrode pads 34 individually, and the electrode pad 34, that is, the first portion of the extension portion 20 from the upper side of the first main surface. The upper surfaces of the first surface 20a are separated and insulated from each other.

  Therefore, in the wiring pattern 42, a partial region having a certain length on and near the boundary is preferably thicker, that is, wider or thicker.

  As described above, the reliability of the operation of the semiconductor device 10 is improved by forming the partial region of the pattern 42 where stress is likely to be concentrated due to the edge effect or thermal stress.

  The region on the upper side (directly above) of the extended portion 20 is referred to as an expanded region 21 in the sense that the external terminal forming region is expanded outside the surface region of the semiconductor element. In this configuration example, electrode posts 46 are also formed in the expanded region 21.

  A sealing portion 44 is formed so as to cover the wiring pattern 42 and the electrode post 46. The sealing portion 44 is formed so that a part of the electrode post 46 is exposed.

  External terminals 47 are formed through the electrode posts 46. A configuration in which a part of the wiring pattern 42 is exposed from the sealing portion 44 and an external terminal is directly connected to the wiring pattern 42 without using an electrode post may be employed.

  In this configuration example, the external terminal 47 is formed of, for example, a solder ball 47a. These solder balls 47 a are provided on the top surfaces of the exposed electrode posts 46, and are connected to the wiring pattern 42 through these electrode posts 46. The arrangement and spacing between adjacent electrode posts 46 can be set to a desired arrangement and spacing in consideration of mounting on a printed circuit board, for example.

  As already described, these electrode posts 46 are provided not only on the surface area corresponding to the upper side of the semiconductor chip 30 but also on the upper side of the extended portion 20, that is, on the expanded region 21. Therefore, the degree of freedom in designing the arrangement positions and arrangement intervals of the electrode posts 46 is increased. That is, the restriction on the arrangement interval of the external terminals 47 can be relaxed so that the mounting can be facilitated, and, for example, a wider interval and a desired number can be formed in accordance with the structural requirements on the mounting substrate side. . Specifically, a desired number of external terminals can be formed at a desired arrangement interval by appropriately adjusting the area of the formed extended portion 20.

  The base 12 is peeled off and removed in a manufacturing process to be described later, if desired, so that the semiconductor device 10 can be made thinner as shown in FIG.

  According to the configuration of the semiconductor device 10 of the present invention, the extended portion 20 provided so as to be in contact with and surround the side surface 37 of the semiconductor chip 30, that is, the surface other than the first main surface 36 and the second main surface 38. Since the external terminals 47 are provided on the upper side (directly above), that is, in the expanded region 21, the external terminals 47 are also formed on the semiconductor device 10 on the upper side of the so-called fan-out structure or the first main surface 36. It can be configured as a fan-in / fan-out structure. Therefore, it is possible to increase the degree of freedom in designing the arrangement intervals and arrangement positions of the external terminals 47.

  The semiconductor device 10 of the present invention can be configured to directly connect the semiconductor chip 30 and the external terminal 47 without using an interposer such as a substrate by utilizing a so-called WCSP manufacturing process. In addition to the above effects, for example, in comparison with wire bonding connection, it is possible to further increase the operation speed, increase the function, increase the number of functions, and reduce the size. For example, in comparison with flip-chip connection, equivalent electrical characteristics can be obtained at a lower cost.

  Next, with reference to FIGS. 3A to 10B, a first manufacturing method of the semiconductor device of the first embodiment will be described.

  As a general rule, in each figure, (A) is a schematic partial plan view seen from the upper surface for explaining the configuration of the semiconductor device of the present invention, and (B) is cut along a broken line II in FIG. It is schematic sectional drawing which shows the cut surface which carried out. As an exception, FIG. 6 (B) is a partially enlarged view showing a portion surrounded by a solid line 11 shown in FIG. 6 (A) in an enlarged manner for easy explanation. FIG. 7 is a schematic cross-sectional view taken along the line II of FIG.

  A semiconductor chip placement region 14 on which the semiconductor chip 30 is placed is set on the prepared base 12 in advance. The outline of the semiconductor arrangement region 14 substantially matches the outline of the semiconductor chip 30. The intervals between adjacent semiconductor chip arrangement regions 14 are set to be equal to each other. This interval is sufficient in consideration of the margin area necessary for individualizing semiconductor devices to be implemented later, the surface area of the extended portion formed according to the number of desired external terminals, etc. What is necessary is just to set it as a short interval.

  First, as shown in FIGS. 3A and 3B, alignment is performed on the set semiconductor chip arrangement region 14 and the semiconductor chip 30 is arranged on the base 12.

  The semiconductor chip 30 includes the first main surface 36 as described above. The first main surface 36 includes an electrode pad 34. A plurality of electrode pads 34 are provided along the periphery of the semiconductor chip 30. The semiconductor device 30 has a second main surface 38 that faces the first main surface 36, and one or more side surfaces 37 between the first main surface and the second main surface. .

  Here, the base 12 may be formed of a substrate or sheet made of an organic material such as glass epoxy or polyimide. Or it can select suitably from a ceramic substrate, a metal substrate, Si substrate, etc. as needed. Preferably, at least the region where the semiconductor chip 30 is arranged is formed on the surface by a member having an adhesive means such as an adhesive (not shown).

  The semiconductor chip 30 is preferably bonded and held on the semiconductor chip arrangement region 14 by this bonding means.

  In particular, when the semiconductor device of the present invention is configured not to have a base as shown in FIG. 2B, a base that can be easily removed is selected by a technique such as peeling in a later step. It is good. Specifically, for example, a heat release sheet “Riva Alpha (trade name)” manufactured by Nitto Denko Corporation, a heat-resistant type icros tape (trade name) or SP series (trade name) manufactured by Mitsui Chemicals, Inc. may be peeled later. It can be applied as a possible substrate. Furthermore, a glass substrate on which, for example, an ultraviolet curable adhesive or the like is applied as an adhesive means on the surface is also suitable.

  Next, as shown in FIGS. 4A and 4B, the side surface 37 of the semiconductor chip 30, that is, the surface other than the first and second main surfaces 36 and 38 is surrounded and surrounded by a plurality of semiconductors. The extended portion 20 is formed so as to fill the gap between the chips 30.

  As described above, so-called liquid resin or mold resin can be used as the material for the extended portion 20. For example, it can be formed by appropriately selecting from organic materials such as epoxy resin and silicone resin.

In order to prevent the warpage that may occur in the semiconductor device 10 during the manufacturing process, the extended portion 20 is preferably formed of a material having a molding shrinkage smaller than the molding shrinkage of a sealing portion that is formed later. Is good. Specifically, the expanded portion 20 has a material whose linear expansion coefficient at a temperature lower than the glass transition temperature is smaller than 1.5 × 10 ⁻⁵ / ° C. and whose elastic modulus is in the range of 7.8 to 22 GPa. It is good to form with liquid resin.

For example, the following method can be applied to form the extended portion 20. (1) and (2) are methods used when applying a liquid resin to the extended portion 20, and (3) is a method used when applying a mold resin to the extended portion 20.
(1) After supplying the liquid resin so as to fill the gaps between the plurality of semiconductor chips 30 by the dispensing method, the liquid resin is cured by an appropriate curing means.
(2) After supplying the liquid resin so as to fill the gaps between the plurality of semiconductor chips 30 by a precision printing method, the liquid resin is cured by an appropriate curing means.
(3) After setting the first main surface 36 of the semiconductor chip 30 on the mold in a protected state and supplying the mold resin so as to fill the gaps between the plurality of semiconductor chips 30 by the transfer molding method, It is cured by a suitable curing means.

  Here, it is preferable that the height of the first surface 20 a of the extended portion 20, that is, the thickness d <b> 2, and the height of the first main surface 36 of the semiconductor chip 30, that is, the thickness d <b> 1 are matched. However, a slight difference in level or undulation may be present as long as the wiring pattern to be formed later is within a range of height difference that can be formed without fear of causing disconnection.

  In particular, when a mold resin is applied to the extended portion 20, the dimensional accuracy in the thickness direction can be increased, so that the extended portion 20 can be formed with higher accuracy.

  Next, the insulating film 40 is formed on the surface of the extended portion 20 and the first main surface 36. The insulating film 40 is formed so that the electrode pad 34 of the semiconductor chip 30 is at least partially exposed.

  At this time, after the insulating film 40 is once formed so as to cover the electrode pad 34, the electrode pad 34 may be exposed using, for example, a photolithography method.

  As described above, there may be a step between the surface of the extended portion 20 and the surface of the semiconductor chip 30. In addition, undulations or depressions may be generated on the surface of the extended portion 20. In these cases, the insulating material for the insulating film 40 may reduce the level of the step so that a wiring pattern can be formed in a later process, or the insulating film 40 may be formed substantially flat. it can.

  The insulating film 40 is formed by a conventionally known method such as a spin coating method, a printing method, or a direct coating process using a suitable insulating material and a suitable method according to the material of the extended portion 20. Yes, you can.

  Thereafter, as shown in FIGS. 6 and 7, a plurality of wiring patterns 42 are formed on the surface of the insulating film 40. The wiring patterns 42 are formed on the surface of the insulating film 40 in consideration of the arrangement of external terminals to be formed after each wiring pattern 42 is set to be electrically connected to the corresponding electrode pad 34. And do it.

  Specifically, according to the applicable wiring process rule, the wiring width, the wiring interval, the optimum angle, etc. are determined, and the connection is made so as to have the shortest possible distance. For example, as shown in the figure, a set of long wirings 42a, middle wirings 42b, and short wirings 42c is set so as to be the shortest distance in principle with respect to the plurality of electrode pads 34 formed along the periphery of the semiconductor chip 30. A plurality of wiring pattern groups are formed, and one end portion is connected to the corresponding electrode pad 34. An electrode post mounting pad is formed at the other end, and the external terminal 47 (solder ball 47a) is connected via the electrode post. That is, the plurality of wiring patterns 42 are individually electrically connected to each of the electrode pads 34 on the insulating film 40, and the electrode pads 34, that is, the first main surface 36 from the upper side of the first main surface 36. It is formed so as to be led out to the upper side of the first surface 20a.

  5A and 6A, the number of electrode pads 34 is schematically shown as a smaller number than the actual number for ease of explanation.

  The wiring pattern 42 is formed in the surface region of the insulating film 40 in a desired region on the insulating film 40 including the expanded region 21 above the extended portion 20, such as sputtering and photolithography. This can be performed by a wiring pattern forming process in the manufacturing process of the WCSP. As a material for forming the wiring pattern 42, any suitable material can be selected. For example, the wiring pattern 42 is preferably formed of a material such as aluminum, copper, and a metal alloy. For example, an appropriate material such as copper can be selected and performed.

  Next, as shown in FIGS. 8A and 8B, electrode posts 46 electrically connected to these are formed on the surface of each wiring pattern 42, respectively. These electrode posts 46 are provided in the extended region 21 on the upper side (directly above) of the extended portion 20 and the region near the expanded region 21 on the upper side (directly above) of the semiconductor chip 30. These electrode posts 46 are formed so as to be arranged at predetermined intervals in a lattice shape. As described above, this interval may be an interval considering the mounting, that is, a constant or irregular interval.

  The electrode post 46 can be formed by selecting an appropriate material according to a process for forming the electrode post 46 in a conventionally known WCSP manufacturing process such as plating and photolithography.

  Further, a sealing portion 44 is formed so as to cover the surface of the insulating film 40 on which the wiring pattern 42 and the electrode post 46 are formed. The sealing portion 44 is formed so as to expose a part of the lead-out portion of the wiring pattern 42 (the wiring pattern 42 itself when the electrode post is not formed).

  This sealing step can be performed by a conventionally known method using a conventionally known sealing material, for example, an epoxy mold resin.

As the mold resin generally used here, for example, the linear expansion coefficient at a temperature lower than the glass transition temperature is in the range of 0.6 to 1.3 × 10 ⁻⁵ / ° C., and the glass transition temperature (Tg). Is a range of 125 to 220 ° C., and an elastic modulus of 9.8 to 24 GPa (1000 to 2450 kg / mm ² ). These are preferably applied to the manufacture of the semiconductor device 10 of the present invention.

  In order to prevent the warpage of the semiconductor device 10 in the manufacturing process, as described above, the material for forming the extended portion 20 with a so-called mold resin, like the sealing portion 44, forms the extended portion 20. The molding shrinkage of the mold resin to be performed is determined to be larger than that of the sealing portion 44. For example, the following combinations are mentioned about the physical property of the mold resin of the expansion part 20 and the sealing part 44.

(1) Expansion part / sealing part: The physical property of the mold resin in the expansion part is such that the linear expansion coefficient at a temperature lower than the glass transition temperature is in the range of 1.1 to 1.5 × 10 ⁻⁵ / ° C. In addition, the glass transition temperature (Tg) is larger than 170 ° C./The physical properties of the molding resin in the sealing portion are such that the linear expansion coefficient at a temperature lower than the glass transition temperature is smaller than 1.0 × 10 ⁻⁵ / ° C. The temperature (Tg) is in the range of 125 to 220 ° C., and the elastic modulus is in the range of 14.7 to 24 GPa (1500 to 2450 kg / mm ² ).

(2) Expansion part / sealing part: The physical property of the mold resin of the expansion part is such that the linear expansion coefficient at a temperature lower than the glass transition temperature is in the range of 1.1 to 1.7 × 10 ⁻⁵ / ° C., In addition, the glass transition temperature (Tg) is lower than 170 ° C., the elastic modulus is 9.8 to 19.6 GPa (1000 to 2000 kg / mm ² ) / the physical properties of the molding resin of the sealing portion are lower than the glass transition temperature. Has a linear expansion coefficient of less than 1.0 × 10 ⁻⁵ / ° C., a glass transition temperature (Tg) in the range of 125 to 220 ° C., and an elastic modulus of 14.7 to 24 GPa (1500 to 2450 kg / mm ² ). range.

(3) Expansion part / sealing part: The physical properties of the mold resin in the expansion part are such that the linear expansion coefficient at a temperature lower than the glass transition temperature is in the range of 1.1 to 1.7 × 10 ⁻⁵ / ° C., and lines modulus is 13.7GPa (1400kg / mm ^2), and the physical properties of glass transition temperature (Tg) of 125 ° C. to 170 ° C. in the range / sealing portion of the molding resin, at a temperature lower than the glass transition temperature The expansion coefficient is smaller than 1.0 × 10 ⁻⁵ / ° C., the glass transition temperature (Tg) is in the range of 125 to 220 ° C., and the elastic modulus is in the range of 14.7 to 24 GPa (1500 to 2450 kg / mm ² ). .

  Thereafter, as shown in FIGS. 9A and 9B, the sealing portion 44 is scraped off from the surface side, and the top surface (also referred to as the upper surface) of the electrode post 46 is scraped and exposed.

  This step can be performed by applying a conventionally known grinding or polishing step.

  A method such as film forming can also be applied to the formation of the sealing portion 44. In that case, the electrode post 46 is not substantially loaded. In this case, the top surface of the electrode post 46 is directly formed so as to be exposed on the surface of the sealing portion 44 without requiring the grinding step for the sealing portion 44 described above.

  At this time, any suitable treatment necessary for design may be performed on the exposed top surface of the electrode post 46. For example, when the material of the electrode post 46 is copper, a Ni (nickel) film or the like may be formed on the top surface of the electrode post 46 as a barrier metal layer.

  The plurality of external terminals 47 are formed on the wiring pattern 42 in the region including the upper side of the extended portion 20 so as to be individually electrically connected to the lead-out portion of the wiring pattern 42, that is, the exposed portion. The

  In this configuration example, for example, solder balls 47 a are formed as the external terminals 47 on the upper surfaces of the electrode posts 46 exposed from the surface of the sealing portion 44.

  Next, as shown in FIGS. 10A and 10B, the extension portion 20 and the sealing resin 20 between the plurality of semiconductor chips 30 are cut along the cutting line indicated by the dashed line a. As a result, the structure is separated into a single semiconductor device that exhibits a predetermined function.

  This singulation process is preferably performed by, for example, a blade rotating at a high speed.

  Next, the base 12 is peeled off and removed from the second surface 20b and the second main surface 38 of the expanded portion 20 of the separated structure as desired.

  When the manufacturing process is performed by providing the above-described peelable adhesive means on the base 12 or by providing the peelable adhesive means, a process according to this adhesive means, for example, by heating or hot water It is preferable to perform the peeling process of the base 12 by a process such as ultraviolet irradiation. Specifically, for example, when a heat release sheet is applied as the base 12, it can be peeled off by heating at a predetermined temperature. For example, when an ultraviolet irradiation type adhesive material is applied as the bonding means, the base 12 can be peeled by curing by ultraviolet irradiation.

  This peeling step can be performed at any timing after the electrode post 46 forming step, after the sealing step, or after the individualization step, but is preferably in consideration of the mechanical strength of the extended portion 20 and the like. It is preferable to carry out after the sealing step.

  Further, in explaining the method of manufacturing a semiconductor device of the present invention, in each drawing, a plurality of semiconductor chips are arranged in a lattice shape of 2 (vertical) × X (horizontal; X is a positive number of 2 or more) on a base or a jig. An example of arranging and manufacturing a plurality of semiconductor devices 10 at the same time is shown. However, the present invention is not limited to this, and a larger number of semiconductor chips can be arranged in a lattice pattern composed of a larger number and simultaneously manufactured.

  As described above, according to the first manufacturing method, the WCSP manufacturing process can be applied, and thus the semiconductor device 10 can be manufactured without using a special process for manufacturing the semiconductor device 10.

  Next, a second manufacturing method of the semiconductor device of the present invention will be described with reference to FIGS. In addition, in the manufacturing process mentioned later, since the applied material, the implementation conditions of a process, etc. are the same as that of a 1st method, the detailed description is abbreviate | omitted.

  This second manufacturing method is characterized in that each step is performed using a jig 50 instead of the base 12 described in the first manufacturing method.

  Here, a configuration of a jig suitable for application to the second manufacturing method will be described with reference to FIGS.

  FIG. 11A is a schematic partial plan view for explaining a configuration of a jig suitable for application to the second method for manufacturing a semiconductor device of the present invention, and FIG. It is a schematic sectional drawing which shows the cut surface cut | disconnected by the II broken line of A).

  FIG. 12 is a schematic cross-sectional view for explaining a configuration of a modified example of the jig of FIG. 11 suitable for application to the second manufacturing method of the present invention. In addition, in FIG. 12, since it is the same as that of FIG. 11 (A) about the top view seen from the upper surface, illustration and its detailed description are abbreviate | omitted.

  The jig 50 is a tool for holding or aligning components in the manufacturing process. In this configuration example, the jig 50 is a pedestal provided with a plurality of recesses 52 in a lattice pattern at the same interval. The interval between the adjacent recesses 52 is suitably determined in consideration of the area of the extended portion required for the semiconductor device 10 to be manufactured, that is, the arrangement position, arrangement interval, and arrangement number of the external electrodes.

  In this example, the recess 52 of the jig 50 is a rectangular parallelepiped depression. However, the shape is not limited to this, and the semiconductor chip 30 having various shapes is not particularly limited as long as the semiconductor chip 30 is stably held by the recess 52 and there is no hindrance to the subsequent process.

  The depth h of the concave portion 52 and the area of the bottom surface portion 52a are set to such an extent that the semiconductor chip 30 can be held and stably fixed on the jig 50 and sufficient to carry out the subsequent steps. Is good.

  For example, when the first and second main surfaces 36 and 38 of the semiconductor chip 30 have a rectangular parallelepiped shape having the same shape and the same size, the area of the bottom surface portion 52 a of the recess 52 is at least equal to that of the second main surface 38. It is preferable to set the same area so that the side wall portion 52b of the recess 52 is perpendicular to the bottom surface portion 52a.

  Further, as shown in FIG. 12, the area of the bottom surface 52 a of the recess 52 (including the surface area of the through hole 56 described later) is set to be smaller than the area of the second main surface 38. Further, the side wall 52b of the recess 52 may have a shape having an inclination in which the tip is gradually thinned into the recess 52.

  In this case, as indicated by a dotted line in FIG. 12, the semiconductor chip 30 is a region in the vicinity of the edge portion on the second main surface 38 side of the semiconductor chip 30 within the inclined side wall portion 52b region, that is, It is held by the jig 50 in contact with the periphery of the second main surface 38 and the vicinity thereof. With this configuration, the area of the semiconductor chip 30 that contacts the jig 50 is minimized, so that the process of peeling the semiconductor chip 30 from the jig 50 becomes extremely easy.

  In addition, since the semiconductor chip 30 only needs to be supported within the range where the inclination of the side wall portion 52b exists, it is possible to deal with a plurality of types of semiconductor chips 30 having different sizes with one type of jig.

  The jig 50 is made of a material such as a metal or ceramic that has low adhesion to the semiconductor chip 30, or is made of an appropriate material coated with Teflon (registered trademark) or the like that has low adhesion to these. Is good. In this way, it is possible to easily carry out the process of peeling off the structure under production including the semiconductor device from the jig 50.

  In this jig 50, a through hole 56 is preferably formed in the recess 52. The through hole 56 is preferably connected to an intake / exhaust system 58 for sucking and holding the semiconductor chip 30 in the recess 52.

  The intake / exhaust system 58 can be configured by a conventionally known vacuum exhaust system including, for example, a vacuum pump, piping, and the like.

  Next, a second manufacturing method of the semiconductor device of the present invention using this jig 50 will be described with reference to FIGS. 13 (A) to 14 (C).

  In FIGS. 13 and 14, the plan view viewed from the upper surface side is the same as the first manufacturing method, and therefore illustration and description thereof will be omitted, and description will be made with reference to a schematic cross-sectional view showing a cut surface.

  The jig 50 already described with reference to FIGS. 11 and 12 is prepared in advance.

  Then, as shown in FIG. 13A, the semiconductor chip 30 is provided in the recess 52 so that the second main surface 38 of the semiconductor chip 30 faces the bottom surface 52 a of the recess 52 of the jig 50. At this time, as shown in FIG. 12, the area of the bottom surface 52 a of the recess 52 is set to be smaller than the area of the second main surface 38, and the side wall constituting the circumference of the recess 52 When the portion 52b has a shape having an inclination toward the recess 52, the edge of the semiconductor chip 30 on the second main surface 38 side of the semiconductor chip 30 in the region where the inclination of the side wall portion 52b exists. It is provided on the jig 50 so as to be in contact with the vicinity region, that is, the circumference defining the second main surface 38 and the vicinity thereof.

  Here, as described above, when the bottom surface portion 52a of the concave portion 52 of the jig 50 is provided with the through hole 56 and the intake / exhaust system 58 connected thereto, the second chip of the semiconductor chip 30 is thereby formed. The semiconductor chip 30 is preferably sucked and held on the jig 50 by evacuating the contact surface (gap) between the main surface 38 and the bottom surface portion 52 a of the recess 52.

  The degree of vacuum for sucking and holding the semiconductor chip 30 on the jig 50 may be such that the semiconductor chip 30 can be held stably.

  Next, as shown in FIG. 13B, first, on the jig 50, the surface other than the first and second main surfaces 36 and 38 of the semiconductor chip 30, that is, the side surface 37 of the semiconductor chip 30 is contacted. An extension portion 20 is formed so as to surround it.

  The extended portion 20 is formed such that the level of the first surface 20 a is substantially the same as the level of the first main surface 36 of the semiconductor chip 30.

  The extension 20 is formed by selecting the method and material described above. At this time, when the side wall 52b of the jig 50 has an inclination as described above, there is a possibility that a slight gap (space) may be generated between the jig 50 and the lower portion of the side surface of the semiconductor chip 30. . For this gap, further processing is not particularly required as long as it does not hinder the subsequent process, particularly the formation of the wiring pattern. However, if desired, the extended portion 20 may be formed so as not to cause this gap. Good.

  Next, the insulating film 40 is exposed on the surface of the extended portion 20 formed on the jig 50 and the first main surface 36 of the semiconductor chip 30, and the electrode pad 34 provided with the semiconductor chip 30 is exposed. Form.

  Next, as shown in FIG. 13C, a plurality of wiring patterns 42 are formed on the surface of the insulating film 40 so as to be electrically connected to the top surfaces of the respective electrode pads 34. In this case, as in the first manufacturing method, one wiring pattern is connected to one electrode pad 34 in a one-to-one relationship.

  Thereafter, as shown in FIG. 14A, one electrode post 46 is connected to each wiring pattern 42 at a ratio. The electrode posts 46 are provided in the expanded region 21 on the upper side (directly above) of the extended portion 20 and the region on the upper side (directly above) of the semiconductor chip 30 adjacent to the expanded region 21.

  More specifically, a sealing portion 44 that covers the surface of the insulating film 40 on which the wiring pattern 42 and the electrode post 46 are formed is formed.

  Further, as shown in FIG. 14B, the sealing portion 44 is scraped off from the surface side to expose the top surface of the electrode post 46.

  Next, solder balls 47 a are formed as external terminals 47 on the exposed top surfaces of the electrode posts 46.

  Next, as shown in FIG. 14C, the jig 50 is released from the second surface 20b and the second main surface 38 of the extended portion 20, and the vacuum is released when the vacuum suction means is used. And then peel off.

  Thereafter, a plurality of adjacent semiconductor chips 30 are cut and separated into a single semiconductor device 10 including the semiconductor chip 30.

  By such steps, a semiconductor device having substantially the same configuration as that of the semiconductor device manufactured by the manufacturing method of the first embodiment is manufactured.

  Note that the semiconductor device manufactured by the second manufacturing method has a concave portion of the jig 50 in the relationship between the bottom surface side, that is, the second surface 20b of the extended portion 20 and the second main surface 38 of the semiconductor chip 30. A step due to 52 occurs, but no further processing steps are required unless specifically desired.

  According to the second manufacturing method, a single jig can be used repeatedly. Since it is not necessary to use a base as in the first manufacturing method, members necessary for the manufacturing process can be reduced. Therefore, a reduction in manufacturing cost is expected. In addition, when the semiconductor chip is sucked and held on the jig by the intake / exhaust system through the through hole, the semiconductor chip is further held on the jig and the semiconductor device is peeled off easily and quickly. Therefore, the throughput of the manufactured semiconductor device is expected to be improved.

  In all embodiments of the present invention, the electrode post 46 may be formed of a conductive material. Preferably it is good to form with copper. At this time, it is preferable to form a thin oxide layer on the surface of the electrode post 46. In this way, the adhesiveness between the electrode post 46 and the sealing portion 44 is improved, so that the moisture resistance is improved.

  In all the embodiments of the present invention, a so-called BGA (Ball Grid Array) type in which solder balls 47a are formed on the electrode posts 46 as the external terminals 47 will be described, but the present invention is not limited to this. For example, on the exposed electrode post 46, a so-called LGA (Land Grid Array) type can be formed as a land by applying and reflowing solder paste or Ni / Au treatment by electroless plating.

  Further, in all the embodiments of the present invention, the shape of the sealing portion is not limited to the so-called saw cut type, and may not match the outer shape of the base and / or the extended portion as long as the object of the present invention is not impaired. Good.

  For example, a plurality of the semiconductor devices 10 according to the first embodiment may be stacked. In this case, for example, a through hole may be formed in the extended portion by a conventionally known method to form a lamination terminal.

(A) is a plan view seen from a schematic top view for explaining the configuration of the semiconductor device of the present invention, and (B) is a diagram for explaining the connection relationship between a wiring pattern and electrode pads. It is the rough principal part top view which expanded and showed the one part area | region. (A) And (B) is a schematic sectional drawing which shows the cut surface cut | disconnected by the II broken line of FIG. 1 (A), (A) is a form which provides a foundation | substrate, (B) is a foundation | substrate. It is a figure for demonstrating the form which does not have. . (A) And (B) is the schematic plan view and sectional drawing seen from the upper surface for demonstrating the 1st manufacturing method of the semiconductor device of this invention. (A) And (B) is the schematic plan view and sectional drawing seen from the upper surface following FIG. 3 for demonstrating the 1st manufacturing method of the semiconductor device of this invention. (A) And (B) is the schematic plan view and sectional drawing seen from the upper surface following FIG. 4 for demonstrating the 1st manufacturing method of the semiconductor device of this invention. (A) is the schematic top view seen from the upper surface for demonstrating the 1st manufacturing method of the semiconductor device of this invention, (B) is the planar enlarged view of the partial area | region of (A). . It is sectional drawing corresponding to FIG. (A) And (B) is the schematic plan view and sectional drawing seen from the upper surface following FIG.6 and FIG.7 for demonstrating the 1st manufacturing method of the semiconductor device of this invention. (A) And (B) is the schematic plan view and sectional drawing seen from the upper surface following FIG. 8 for demonstrating the 1st manufacturing method of the semiconductor device of this invention. (A) And (B) is the schematic plan view and sectional drawing seen from the upper surface following FIG. 9 for demonstrating the 1st manufacturing method of the semiconductor device of this invention. It is a schematic plan view and sectional view (1) of a jig suitable for use in the method for manufacturing a semiconductor device of the present invention. It is a schematic sectional drawing (2) of a jig | tool suitable for using for the manufacturing method of the semiconductor device of this invention. It is schematic sectional drawing (1) for demonstrating the 2nd manufacturing method of the semiconductor device of this invention. FIG. 14 is a schematic cross-sectional view (2) following FIG. 13 for illustrating the second method for manufacturing the semiconductor device of the present invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10: Semiconductor device 11: Partial area | region 12: Base | substrate 14: Semiconductor chip arrangement | positioning area | region 20: Expansion part 20a: 1st surface 20b: 2nd surface 21: Expanded area | region 22: Opening part 30: Semiconductor chip 34: Electrode Pad 36: First main surface 37: Side surface 38: Second main surface 40: Insulating film 42: Wiring pattern 42a: Long wiring 42b: Medium wiring 42c: Short wiring 44: Sealing portion 46: Electrode post 47: External Terminal 47a: Solder ball 50: Jig 52: Recessed portion 52a: Bottom portion 52b: Side wall portion 56: Through hole 58: Intake / exhaust system

Claims (7)

(1) a step of setting a plurality of semiconductor chip placement regions on which a plurality of semiconductor chips are placed at a predetermined interval;
(2) On the semiconductor chip arrangement region, a first main surface having a plurality of electrode pads, a second main surface facing the first main surface, the first main surface, and the Providing a semiconductor chip having a plurality of side surfaces between the second main surface and facing the second main surface;
(3) A first surface and a second surface opposite to the first surface are provided on the base, and the semiconductor chip is surrounded by the side surface of the semiconductor chip . The level of one surface is the same as the level of the first main surface, or a level having a level difference enough to form a wiring pattern between the upper side of the first surface and the upper side of the first main surface. Forming an extension formed to be, and
(4) forming an insulating film on the first surface of the extension portion and on the first main surface, exposing a part of the electrode pad;
(5) On the insulating film, a plurality of the wiring patterns that are electrically connected to each of the electrode pads and led out from the electrode pads to the upper side of the first surface of the extension portion are formed. A step of forming a width at a portion located on a boundary between the first surface of the extension portion and the first main surface of the semiconductor chip so as to be wider than other portions, or a thickness thereof. Forming a plurality of the wiring patterns so as to be thick,
(6) forming a sealing portion on the wiring pattern and the insulating film by exposing a part of the wiring pattern located on the upper side of the first surface;
(7) connecting and forming a plurality of external terminals on the wiring pattern in the region including the upper side of the extended portion;
(8) A method of manufacturing a semiconductor device, comprising: cutting a plurality of the semiconductor chips and separating the semiconductor devices including the semiconductor chips. (1) a step of setting a plurality of semiconductor chip placement regions on which a plurality of semiconductor chips are placed at a predetermined interval;
(2) On the semiconductor chip arrangement region, a first main surface having a plurality of electrode pads, a second main surface facing the first main surface, the first main surface, and the Providing a semiconductor chip having a plurality of side surfaces between the second main surface and facing the second main surface;
(3) A first surface and a second surface opposite to the first surface are provided on the base, and the semiconductor chip is surrounded by the side surface of the semiconductor chip . The level of one surface is the same as the level of the first main surface, or a level having a level difference enough to form a wiring pattern between the upper side of the first surface and the upper side of the first main surface. Forming an extension formed to be, and
(4) forming an insulating film on the first surface of the extension portion and on the first main surface, exposing a part of the electrode pad;
(5) On the insulating film, a plurality of the wiring patterns that are electrically connected to each of the electrode pads and led out from the electrode pads to the upper side of the first surface of the extension portion are formed. A step of forming a width at a portion located on a boundary between the first surface of the extension portion and the first main surface of the semiconductor chip so as to be wider than other portions, or a thickness thereof. Forming a plurality of the wiring patterns so as to be thick,
(6) forming a plurality of electrode posts on each of a part of the wiring pattern located above the extended portion;
(7) forming a sealing portion exposing the top surface of the electrode post on the wiring pattern and the insulating film;
(8) forming an external terminal on the exposed top surface of the electrode post;
(9) A method for manufacturing a semiconductor device, comprising: cutting a plurality of semiconductor chips to separate the semiconductor devices including the semiconductor chips. The step of forming a sealing portion exposing the top surface of the electrode post on the wiring pattern and the insulating film,
Forming a sealing portion on the wiring pattern and the insulating film so as to cover a top surface of the electrode post;
The method for manufacturing a semiconductor device according to claim 2, further comprising a step of exposing a top surface of the electrode post by grinding a surface of the sealing portion. A first main surface comprising a plurality of electrode pads; a second main surface opposite to the first main surface; and a plurality of between the first main surface and the second main surface A semiconductor chip having side surfaces;
A first surface and a second surface opposite to the first surface;
Surrounding the semiconductor chip in contact with a side surface, the first surface is the same as the level of the first main surface, or wiring is formed between the upper side of the first surface and the upper side of the first main surface An extension formed so as to have a level having a level that can form a pattern;
An insulating film formed on the first surface and the first main surface by exposing a part of the plurality of electrode pads;
A plurality of the wiring patterns that are electrically connected to each of the electrode pads and led out from the electrode pad to the upper side of the first surface of the extension portion, wherein the first of the extension portion; A plurality of the wiring patterns whose width is wider than other portions in the portion located on the boundary between the surface of the semiconductor chip and the first main surface of the semiconductor chip, or the thickness is increased,
A sealing portion formed on the wiring pattern and the insulating film by exposing a part of the wiring pattern;
A semiconductor device comprising: a plurality of external terminals provided on the wiring pattern in a region including the upper side of the extended portion. Comprising a plurality of electrode posts formed between the wiring pattern and the external terminals;
The semiconductor device according to claim 4, wherein the sealing portion is formed so as to expose a top surface of the electrode post. The semiconductor device according to claim 4, wherein the extension portion is formed of a material having a molding shrinkage larger than that of the sealing portion. The expansion portion has a linear expansion coefficient of 1.5 × 10 5 in a temperature range lower than the glass transition temperature. ^-Five The semiconductor device according to claim 4, wherein the semiconductor device is made of a liquid resin having a modulus of elasticity lower than / ° C. and a modulus of elasticity of 7.8 to 22 GPa.

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