JP2005011856A - Chip-like electronic part, its manufacturing method, and its mounting structure - Google Patents

Chip-like electronic part, its manufacturing method, and its mounting structure Download PDF

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JP2005011856A
JP2005011856A JP2003171443A JP2003171443A JP2005011856A JP 2005011856 A JP2005011856 A JP 2005011856A JP 2003171443 A JP2003171443 A JP 2003171443A JP 2003171443 A JP2003171443 A JP 2003171443A JP 2005011856 A JP2005011856 A JP 2005011856A
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Prior art keywords
chip
electronic component
pseudo wafer
shaped electronic
insulating material
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Japanese (ja)
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Kenichi Obinata
健一 小日向
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Sony Corp
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Sony Corp
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    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
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  • Engineering & Computer Science (AREA)
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  • Microelectronics & Electronic Packaging (AREA)
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  • Condensed Matter Physics & Semiconductors (AREA)
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Abstract

<P>PROBLEM TO BE SOLVED: To provide a chip-like electronic part which can be easily manufactured with high reliability at a low cost and highly functionalized, and to provide its manufacturing method and mounting structure. <P>SOLUTION: The method of manufacturing the chip-like electronic part comprises processes of fixing a plurality of semiconductor chips or a plurality of kinds of semiconductor chips on a board, depositing an insulating material on all the surface of the board including spaces among the semiconductor chips, separating a pseudo wafer where semiconductor chips are fixed from the board, boring a though-hole in the dicing area of the pseudo wafer of the insulating material penetrating through it in the direction of thickness, filling the through-hole with a conductive material, forming interconnect lines connected to conductive resins on both the surfaces of the pseudo wafer, and cutting the semiconductor chips to divide the board into separate chip-like electronic parts each having the conductive resin in the direction of thickness. The chip-like electronic part obtained by the manufacturing method is provided, and its manufacturing structure is also provided. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

【０００１】
【発明の属する技術分野】
本発明は、半導体装置の製造に好適なチップ状電子部品及びその製造方法、並びにその実装構造に関するものである。
【０００２】
【従来の技術】
近年、モジュールからなる半導体の部品セットの小型化に伴い、チップ状の部品である半導体チップやインターポーザ等の実装効率を向上することを目的として、これらの半導体パッケージのスタック（積層）構造に対する需要が増えている。
【０００３】
しかしながら、半導体チップをパッケージ化すると、その平面サイズはチップ面積よりも拡大してしまうため、スタック構造の効果を十二分に引き出すことができない。
【０００４】
この問題を解決するために、シリコンからなる半導体ウエーハに貫通孔を設けることにより、半導体ウエーハの裏面に外部回路との電気的接続用の外部端子を形成することを可能とするような方法の研究開発が、実用化に向けて進められている（例えば、後記の特許文献１参照。）。
【０００５】
以下、後記の特許文献１による上記したような方法の一例を、図１２、図１３及び図１４を参照して説明する。
【０００６】
まず、図１２（ａ）に示すように、シリコンからなる基体としての半導体ウエーハ５１を作製し、この半導体ウエーハ５１上に絶縁材料をスピンコート法や印刷法等で形成する。次に、絶縁材料をエッチング等で所定のパターンに加工して、開口部５３を有する絶縁層５２を形成し、更に、半導体ウエーハ５１及び絶縁層５２上に、これらを覆うようにして電極材料をスパッタリング等により形成する。次に、電極材料をエッチング等で所定のパターンに加工してランド５４を形成する。
【０００７】
次に、半導体ウエーハ５１、ランド５４及び絶縁層５２上に、これらを覆うようにして層間絶縁材料をスピンコート法や印刷法等で形成する。層間絶縁材料をエッチング等で所定のパターンに加工して、開口部５３に連通した他の開口部５８をスクライブライン領域に有し、更には、ランド５４上にビアホールを有する層間絶縁膜５６を形成する。
【０００８】
次に、半導体ウエーハ５１、ランド５４、層間絶縁膜５６及び絶縁層５２上に、これらを覆うようにして配線材料をスパッタリング等により形成する。配線材料をエッチング等で所定のパターンに加工して、ビアホール内及び層間絶縁膜５６上にわたって連続して設けられた配線５９を形成する。そして、半導体ウエーハ５１、層間絶縁膜５６、配線５９及び絶縁層５２上に、これらを覆うようにして配線保護材料をスピンコート法や印刷法等で形成する。
【０００９】
次に、配線保護材料をエッチング等で所定のパターンに加工して、開口部６２を有し、配線５９上にビアホール７４を有する配線保護層６１を形成する。ここで、後述のチップ状電子部品７９等の区画単位毎に、絶縁層５２、ランド５４、層間絶縁膜５６、配線５９及び配線保護層６１からなる積層体を表面配線部６３と称する。
【００１０】
次に、図１２（ｂ）に示すように、表面配線部６３の反対側である半導体ウエーハ５１の裏面から半導体ウエーハ５１の一部をＲＩＥ（Ｒｅａｃｔｉｖｅ Ｉｏｎ Ｅｔｃｈｉｎｇ）等で除去して、半導体ウエーハ５１にそれぞれのランド５４に至る貫通孔６４を形成する。
【００１１】
次に、図１３（ｃ）に示すように、後述の導電層６６と半導体ウエーハ５１とを電気的に絶縁するために、貫通孔６４の内壁面から半導体ウエーハ５１の裏面に連続して絶縁材料を所定の厚さに被着する。ここで、貫通孔６４の底部にはランド５４を露出させるように絶縁材料を被着させる。
【００１２】
次に、絶縁材料をエッチングして、貫通孔６４と半導体ウエーハ５１の裏面上の貫通孔６４の周辺部とに絶縁膜６５を残し、更に、貫通孔６４内に例えば無電解めっき法及び電解めっき法の組み合わせを用いた通常のスルーホールメッキにより導電性物質を充填して、導電層６６を形成する。このときの導電性物質は、ランド５４と接触して半導体ウエーハ裏面の絶縁膜６５の表面まで充填する。そして、半導体ウエーハ裏面においてはんだペーストを導電層６６上に印刷した後、ウエットバック法ではんだペーストを溶融してはんだバンプ６９を形成する。
【００１３】
次に、導電層６６やはんだバンプ６９及び表面配線部６３等を設けた半導体ウエーハ５１をブレード７０（又はレーザー）でスクライブライン７３に沿ってダイシング７１し、図１３（ｄ）に示すようなチップ状電子部品７９に個片化する。
【００１４】
次に、図１３（ｅ）に示すように、このチップ状電子部品７９の基板５１の表面配線部６３上においてはんだペーストを印刷法により配線５９上のビアホール７４内に転写し、更に、ウエットバック法ではんだペーストを溶融してはんだバンプ７８を形成する。
【００１５】
こうして作製されたチップ状電子部品７９は、例えば、図１４に示すように、はんだバンプ７８’を介してチップ状電子部品７９ａ及び７９ｂを上下にスタックでＭＣＭ（Ｍｕｌｔｉ Ｃｈｉｐ Ｍｏｄｕｌｅ）実装することができる。
【００１６】
一方、本出願人は、ウエーハ一括処理を行うことができ、最先端のＬＳＩ（大規模集積回路）やベアチップで入手した場合でも、高歩留り、低コストにして信頼性良く提供可能な半導体チップ等のチップ状電子部品を提案した（例えば、後記の特許文献２参照。）。
【００１７】
即ち、特許文献２に係る発明は、まず、基板上に、処理前は粘着力を持つが処理後は粘着力が低下する粘着手段を貼り付け、この粘着手段の上に複数個又は複数種の半導体チップをその電極面を下にして固定し、保護物質を前記半導体チップ間を含む全面に被着する。次いで、前記粘着手段に所定の処理を施して前記粘着手段の粘着力を低下させて、前記半導体チップをその側面及び裏面において前記保護物質で固定した疑似ウエーハを剥離し、前記半導体チップ間において前記保護物質を切断して、図１５に示すような、チップ状電子部品８０を分離する。得られたチップ状電子部品８０は、同図に示すように、例えばバンプ電極８１を介して再配線用のインターポーザ８２と電気的に接続することができる。
【００１８】
そして、図１６に示すように、インターポーザ８２に接続されたチップ状電子部品８０の複数個をはんだボール８３を介して積層し、更にこの積層体を回路基板８４と電気的に接続することができる。
【００１９】
この特許文献２による製造方法によれば、チップ状電子部品を疑似ウエーハから切り出す際に、保護物質の部分を切断するので、チップ状電子部品本体への悪影響（歪みやばり、亀裂等のダメージ）を抑えられる。
【００２０】
また、良品のチップ状電子部品を疑似ウエーハより切り出して再配列することにより、あたかも全品が良品チップのウエーハのようになって、ウエーハ一括でのはんだバンプ処理等が可能になり、低コストで歩留り良くフリップチップ用はんだバンプチップを形成できる。そして、自社製ウエーハのみならず、他社から購入したベアチップでも容易にはんだバンプ処理等が可能になる。
【００２１】
また、保護物質によってチップ側面及び裏面が覆われているので、Ｎｉ無電解めっき処理も可能であると共に、同じく保護物質によってチップ側面及び裏面が保護されているので、チップの個片後の実装ハンドリングにおいてもチップが保護され、良好な実装信頼性が得られる。
【００２２】
【特許文献１】
特開平５−６３１３７号公報（２頁２欄２５行目〜３頁３欄７行目、図１）
【特許文献２】
特開２００１−３１３３５０号公報（６頁９欄４２行目〜７頁１２欄２１行目、図１〜５）
【００２３】
【発明が解決しようとする課題】
しかしながら、上述したような特許文献１による方法は、図１２（ｂ）に示した工程で、シリコンからなる半導体ウエーハ５１中に貫通孔６４を形成するには、ＲＩＥ等のエッチング法を適用するが、この加工工程においては、高価な半導体製造装置を用いるためにコスト高となる。また、比較的脆弱な材質の半導体ウエーハ５１中に貫通孔６４を形成するので、半導体ウエーハ５１の破損を防ぐために、加工時間が長くなり、製造コストを更に上昇させてしまう。
【００２４】
また、半導体ウエーハ５１を構成するシリコン自体は導電性があるために、図１３（ｃ）に示した貫通孔６４内に導電層５７を設ける際には、予め貫通孔６４の内壁部及びはんだバンプ形成個所に絶縁膜６５を選択的に形成して絶縁分離処理を施す必要があり、これも作製工程を増加させ、かつ作業性が悪くなる。
【００２５】
また、外部接続用のはんだバンプ６９を形成する際に絶縁膜６５からはんだバンプ６９がはみ出してしまうと、はんだバンプ６９と半導体ウエーハ５１との間又ははんだバンプ６９間が短絡してしまう。
【００２６】
また、半導体ウエーハ５１を構成するシリコンは脆くて少しの衝撃でも欠け易い材質であるために、半導体ウエーハ５１又はシリコンが露出した構造物の取り扱いが困難となる。
【００２７】
一方、特許文献２は上記した優れた特長をもちつつも、改善すべき点がある。
【００２８】
即ち、図１５に示すように、得られるチップ状電子部品８０は、その片方の面側にのみ外部との接続が可能な電極８５を有するので、その複数個を積層する場合には、図１６に示すように、予めチップ状電子部品８０とインターポーザ８２とを電気的に接続した後、はんだボール８３を用いてチップ状電子部品８０の複数個を積層しなければならない。このため、全体としての厚みが大きくなる。
【００２９】
本発明は、上述したような問題点を解決するためになされたものであって、その目的は、容易かつ信頼性良く低コストに製造可能であり、単一部品としても更なる高機能化を図ることができる半導体集積回路チップ部品の如きチップ状電子部品及びその製造方法、並びにその実装構造を提供することにある。
【００３０】
【課題を解決するための手段】
即ち、本発明は、基体上に複数個又は複数種の半導体チップをその電極面を下にして固定する工程と；絶縁物質を前記複数個又は複数種の半導体チップ間を含む全面に被着する工程と；前記半導体チップを固定した疑似ウエーハを前記基体から剥離する工程と；前記絶縁物質からなる前記疑似ウエーハのダイシングエリアに、前記疑似ウエーハの厚さ方向に貫通した貫通孔を設ける工程と；前記貫通孔に導電性樹脂を充填する工程と；前記疑似ウエーハの一方の面側及びそれとは反対側の他方の面側において前記導電性樹脂に接続された配線をそれぞれ形成する工程と；前記複数個又は複数種の半導体チップ間を前記ダイシングエリアに沿って切断して、前記導電性樹脂を厚さ方向に保持したチップ状電子部品に個片化する工程と；を有する、チップ状電子部品の製造方法に係るものである。
【００３１】
また、一方の面側及びこれとは反対側の他方の面側にそれぞれ配線及びその端子が形成され、少なくとも側面に絶縁物質層が被着されており、かつ、前記一方の面側及び他方の面側の各配線間を電気的に接続するための導電性樹脂層が前記絶縁物質層上又は内に形成されている、チップ状電子部品に係り、更に、本発明のチップ状電子部品の複数個が、集積回路チップとして、前記一方の面側及び他方の面側の前記端子を介して積層されている、チップ状電子部品の実装構造に係るものである。
【００３２】
ここで、本発明における「チップ状電子部品」とは、チップ単品に留まらず、ＣＰＵ（ｃｅｎｔｒａｌ ｐｒｏｃｅｓｓｉｎｇ ｕｎｉｔ：（コンピュータ）中央演算処理装置）やメモリーなど異種複数の半導体チップ、或いは抵抗、コンデンサなどの実装部品を任意に平面的に組み合わせて配置し、樹脂などの前記絶縁物質で固定し、相互を再配線接続して、ひとつの高機能モジュール（システム・イン・パッケージ）として形成及び使用することが可能となるものである。
【００３３】
本発明の製造方法によれば、前記絶縁物質からなる前記疑似ウエーハの前記ダイシングエリアに、前記疑似ウエーハの厚さ方向に貫通した前記貫通孔を設けるので、上述した従来例のように、シリコンからなる半導体ウエーハそのものに貫通孔を形成し、この貫通孔に導電性物質を埋め込む加工を施すのに比べ、遥かに容易かつ信頼性が高く、また低コストである。また、前記貫通孔の孔径を比較的自由に選択することができる。
【００３４】
また、前記導電性樹脂は前記貫通孔に充填し易く、かつ前記絶縁物質との密着性に優れている。従って、例えば前記複数個又は複数種の半導体チップ間を前記ダイシングエリアに沿って切断する工程等で受ける外的力に対して、優れた耐久性を有する。これは、個片化された後のチップ状電子部品の形態又はチップ状電子部品の複数個が積層された形態においても同様である。
【００３５】
また、アナログ、デジタルにとらわれず、個々の良品チップのみ使用して組み合わせ、前記チップ状電子部品に個片化することができるので、ウエーハあたりの歩留まりにとらわれず、低コスト化することができる。また、自社製ウエーハのみならず、他社から購入したベアチップも取り混ぜての作製が可能である。
【００３６】
また、前記チップ状電子部品を前記疑似ウエーハから切り出す際に、前記絶縁物質の部分を切断し、従来例のようにシリコン部を切断することがないので、前記チップ状電子部品本体への悪影響（歪みやばり、亀裂等のダメージ）が少なく、さらに、大部分が前記絶縁物質で覆われているために実装ハンドリングがし易く、良好な実装信頼性が得られる。
【００３７】
また、上述したように、ＩＣチップだけでなく、チップ抵抗やコンデンサ等の受動部品、及び光学系部品等の多肢にわたる部品を一括して組み込むことができるので、高機能モジュールとしての形態も可能となる。
【００３８】
さらに、前記半導体チップの厚さ、大きさにとらわれずに作製することができ、かつ前記チップ状電子部品自体の厚さを非常に薄くすることができる。
【００３９】
そして、本発明の製造方法によって得られるチップ状電子部品及びその実装構造によれば、前記積層等の実装は樹脂からなる前記絶縁物質層上の前記端子を介して行うことができる。このため、線膨張係数を類似とすることができ、高信頼性のスタックドパッケージ（積層されたチップ状電子部品）を提供できる。
【００４０】
さらに、前記受動部品を含む前記複数個又は複数種の半導体チップを有し、高機能モジュールである本発明のチップ状電子部品を３次元的に積層することで、上記した高信頼性を保ちながら、高性能化を図ることができる。
【００４１】
【発明の実施の形態】
本発明の製造方法において、前記疑似ウエーハの前記ダイシングエリアに、ドリル等の機械加工又はレーザー等の光照射によって前記貫通孔を形成することが望ましい。
【００４２】
また、前記疑似ウエーハの前記ダイシングエリアに、前記複数個又は複数種の半導体チップのそれぞれに対応した前記貫通孔を複数列設けることが好ましい。この場合、前記個片化を行う前の状態で前記導電性樹脂層を介しての導通検査を行うことができる。
【００４３】
これに対し、前記個片化を行う前の状態では前記導電性樹脂層を介しての導通検査を行わず、前記個片化を行い、得られた前記チップ状電子部品のそれぞれに対して前記導電性樹脂層を介しての導通検査を行う場合は、上述した前記貫通孔を複数列設けるのに代えて、前記疑似ウエーハの前記ダイシングエリアに、前記複数個又は複数種の半導体チップに共用される前記貫通孔を一列に設けてもよい。前記一列の場合、上記した複数列の場合に比べて前記貫通孔の径をより大きくすることができる。
【００４４】
また、前記疑似ウエーハの表面及び裏面側において、前記貫通孔に充填された前記導電性樹脂に前記配線との接続電極をそれぞれ形成することが好ましい。
【００４５】
本発明のチップ状電子部品は、一方の面側及びこれとは反対側の他方の面側にそれぞれ配線及びその端子が形成され、少なくとも側面に絶縁物質層が被着されており、かつ、前記一方の面側及び他方の面側の各配線間を電気的に接続するための導電性樹脂層が前記絶縁物質層上又は内に形成されていることが特徴であるが、前記導電性樹脂層が前記ダイシングエリアに存在することが望ましい。
【００４６】
また、前記絶縁物質層にその厚さ方向に貫通した凹状部又は貫通孔が形成され、これらに前記導電性樹脂が充填されていることが望ましい。
【００４７】
次に、本発明の好ましい実施の形態を図面参照下に説明する。図１〜図５は、本発明に基づく製造方法の一例を工程順に示す概略断面図である。
【００４８】
まず、図１（ａ）に示すように、基体１上に、両面に粘着材層２ａ及び２ｂを有する両面テープ基材３をラミネーター等を用いて貼り付ける。
【００４９】
基体１としては、平坦性がよく、後述する半導体チップ４を配置する装置がマーカーを読み取れるものが好適に用いられ、例えばガラスやシリコン（Ｓｉ）等が挙げられる。
【００５０】
また、両面テープ基材３は上記したと同様に、後述する半導体チップ４を配置する装置がマーカーを読み取れるよう、光を透過することができるものが好適に用いられ、例えばポリエチレンテレフタレート（ＰＥＴ）やポリイミド等が挙げられる。
【００５１】
さらに、粘着材層２ａ及び２ｂとしては、両面テープ基材３の両面に同種の既存の自己剥離型粘着材等の粘着材を用いることができるが、例えば両面テープ基材３の基体１が配される面側に自己剥離型粘着材を用い、後述する半導体チップ４を配列する面側にはアクリル系粘着材を用いた方が、プロセス上好ましい。なお、粘着材層２ａ及び２ｂを有する両面テープ基材３は、図示するように基体１全面に付着してよいが、半導体チップ４の固定部分のみに局部的に（パターン化して）付着してもよく、半導体チップ４の表面に付着して基体１に貼付けてもよい。後者の場合は、後述する疑似ウエーハの剥離をより行い易くなる。
【００５２】
次に、図１（ｂ）に示すように、良品と確認された複数個又は複数種の半導体チップ４をチップ表面（デバイス面）を粘着材層２ｂ側にして配列し、粘着材層２ｂに貼り付ける。ここで重要なことは、自社、他社製のチップに関わらず、良品の半導体チップ４のみを基体１上に再配列させることである。
【００５３】
次に、図１（ｃ）に示すように、複数個又は複数種の半導体チップ４間を含む全面に、ポリエステル等の絶縁物質５を被着する。方法としては、金型プレスによる加圧成形、印刷法等による成形法などがある。この時、半導体チップ４は粘着材層２ｂの粘着性により保持固定されているので、動くことはない。印刷法ではエアー残り、巻き込みなどによるボイド発生や、狭ギャップ個所の未充填の懸念などがあるため、加圧成形法がより好ましい。
【００５４】
加圧成形法は、半導体チップ４が配列された基体１を金型に載せ、その上に樹脂（絶縁物質）５を載せてモールド成形する。金型温度は、粘着材層２ｂの材質の反応開始温度により制限されるが、例えば約１５０℃以下が好ましい。加熱加圧時間は使用する樹脂５により様々であるが、例えば１００ＫＮ前後で約１０分前後が好ましい。
【００５５】
次に、図１（ｄ）に示すように、半導体チップ４を固定した疑似ウエーハ６を基体１から剥離する。剥離方法は粘着材層２ａ及び２ｂの材質によるが、例えばＵＶ照射するか、或いは１３０〜１５０℃のオーブンに５〜１０分程度入れて加熱すればよい。これにより、図２（ｅ）に示すように、粘着材層２ａから基体１が強制的に剥離され、基体１と疑似ウエーハ６を分離することができる。
【００５６】
疑似ウエーハ６側に残った両面テープ基材３及び粘着材層２ａ、２ｂは、容易に手で引き剥がすことができる。そして、半導体チップ４面上の残留物を薬液を用いて除去する（図２（ｆ））。
【００５７】
次に、図２（ｇ）に示すように、ＢＧＲ（Ｂａｃｋ Ｇｒｉｎｄ）装置等を用いて疑似ウエーハ６の裏面７を所定の厚さに研削する。ここで、疑似ウエーハ６の厚さとしては、１００μｍ未満も作製は可能であるが、物理的強度保持上１００μｍ以上、３００μｍ以下程度が好ましい。
【００５８】
上記のようにして一括成形された疑似ウエーハ６が完成する。
【００５９】
次に、図３（ｈ）に示すように、研削した疑似ウエーハ６の裏面７側に保護膜８ａを塗布する。なお、半導体チップ４は、例えばＳｉ基板９上にＳｉＯ２膜（図示省略）を介してＡｌパッド電極１０及びパッシベーション膜１１が形成されたものである。保護膜８ａとしては、硬化収縮の小さいものが好適に用いられ、例えばエポキシの感光性絶縁樹脂等が挙げられる。
【００６０】
次に、図３（ｉ）に概略断面図及び図８に概略平面図を示すように、疑似ウエーハ６のダイシングエリア１２に、複数個又は複数種の半導体チップ４のそれぞれに対応した貫通孔１３を複数列設ける。貫通孔１３の形成方法はドリル等を用いた機械的な方法が簡便であるが、多数の貫通孔１３を速やかに形成する場合などにはレーザー等の光照射加工でもよい。
【００６１】
また、貫通孔１３の数が多く、またその径も小さい場合は、図８（ｂ）に示すように、貫通孔１３をダイシングライン１２から若干ずらした位置に設けることが好ましい。ここでは、後述するダイシング後に残る導電性樹脂層１４の体積が導通するに充分な体積を持つことが重要である。
【００６２】
なお、疑似ウエーハ６の厚さｔは任意であるが、例えば１２０μｍ〜２５０μｍの間を想定することができる。
【００６３】
本発明に基づく製造方法によれば、絶縁物質５からなる疑似ウエーハ６のダイシングエリア１２に、疑似ウエーハ６の厚さｔ方向に貫通した貫通孔１３を設けるので、従来例のように、シリコンからなる半導体ウエーハそのものに貫通孔を形成し、この貫通孔に導電性物質を埋め込む加工を施すのに比べ、遥かに容易かつ信頼性が高く、また低コストである。また、貫通孔１３の直径を比較的自由に選択することができ、例えば直径１５０〜３００μｍとすることができる。
【００６４】
次に、図３（ｊ）に示すように、貫通孔１３中に導電性樹脂１４ａを充填する。導電性樹脂１４ａとしては銀ペーストが一般的であるが、Ｃｕ等の導電性ペースト材も用いることができる。充填方法は、一枚の疑似ウエーハ６に無数にある貫通孔１３に対し、一括して導電性樹脂１４ａを充填することができる方法として、スキージ１５を用いた印刷法等がある。
【００６５】
導電性樹脂１４ａは貫通孔１３に充填し易く、かつ絶縁物質５との密着性に優れている。従って、後述する複数個又は複数種の半導体チップ４間をダイシングエリア１２に沿って切断する工程等で受ける外的力に対して、優れた耐久性を有する。これは、個片化された後のチップ状電子部品の形態又はチップ状電子部品の複数個が積層された形態においても同様である。
【００６６】
また、疑似ウエーハ６のダイシングエリア１２に、複数個又は複数種の半導体チップ４のそれぞれに対応した貫通孔１３を複数列設けたので、前記個片化を行う前の現段階で、導電性樹脂１４ａが充填された貫通孔１３を介しての導通検査を行うことができる。
【００６７】
次に、図４（ｋ）に示すように、導電性樹脂１４ａをキュアして固めて導電性樹脂層１４を形成した後、疑似ウエーハ６の両面における導電性樹脂層１４の部分に無電解Ｃｕめっきを施す。これは、導電性樹脂層１４と、後述する再配線１８との接続をより確実なものとするためである。
【００６８】
次に、図４（ｌ）に示すように、半導体チップ４の表面１７側に再配線１８を形成する。再配線１８は、半導体チップ４間の配線（図示省略）及び半導体チップ４のＡｌパッド電極１０と導電性樹脂層１４とを電気的に接続し、更には後述する再配線電極部１９を形成するのに用いられる。再配線１８の形成方法としては、まず、保護膜８ｂを塗布して半導体チップの表面１７側の保護を行い、Ａｌパッド電極１０及び無電解Ｃｕめっき１６の部分を開口する。次いで、バリアメタルとしてチタン（Ｔｉ）を全面にスパッタリングし、まためっき電極としてＣｕ薄膜を全面スパッタ成膜し、更にその上にめっきレジストを塗布し、露光及び現像して、Ｃｕ配線のパターニングを行う。次いで、電気めっきにてＣｕを成膜する。再配線１８に必要な厚さとしては、例えば３〜８μｍ程度である。そして、レジストを剥離、さらにＣｕ、Ｔｉをエッチングで除去することにより、図４（ｌ）に示すようなＣｕの再配線パターン１８が完成する。
【００６９】
次に、図４（ｍ）に概略断面図及び図９に概略平面図を示すように、上記と同様にして裏面７側にも再配線１８をパターン形成する。さらに、表面１７及び裏面７に保護膜８ｃを全面塗布し、再配線電極部１９ａ及び１９ｂとする所定の位置を開口し、再配線工程を終了する。保護膜８ｃは、パターニング性の良いものが好適に用いられ、例えばエポキシの感光性絶縁樹脂等が挙げられる。
【００７０】
次に、図５（ｎ）に示すように、複数個又は複数種の半導体チップ４間をダイシングライン（エリア）１２に沿ってダイシングブレード２０を用いてダイシング２１を行う。
【００７１】
以上のようにして、図６（ａ）に示すような、導電性樹脂層１４を厚さ方向に保持したチップ状電子部品２２を作製することができる。
【００７２】
本発明に基づく製造方法によれば、絶縁物質５からなる疑似ウエーハ６のダイシングエリア１２に、疑似ウエーハ６の厚さ方向に貫通した貫通孔１３を設けるので、シリコンからなる半導体ウエーハそのものに貫通孔を形成し、この貫通孔に導電性物質を埋め込む加工を施す従来の方法に比べ、遥かに容易かつ信頼性が高く、また低コストである。また、貫通孔１３の孔径を比較的自由に選択することができる。
【００７３】
また、導電性樹脂１４ａは貫通孔１３に充填し易く、かつ絶縁物質５との密着性に優れている。従って、例えば複数個又は複数種の半導体チップ４間をダイシングエリア１２に沿って切断する工程等で受ける外的力に対して、優れた耐久性を有する。これは、個片化された後のチップ状電子部品２２の形態又はチップ状電子部品２２の複数個が積層された形態においても同様である。
【００７４】
また、アナログ、デジタルにとらわれず、個々の良品チップのみ使用して組み合わせ、チップ状電子部品２２に個片化することができるので、疑似ウエーハ６あたりの歩留まりにとらわれず、低コスト化することができる。また、自社製ウエーハのみならず、他社から購入したベアチップも取り混ぜての作製が可能である。
【００７５】
また、チップ状電子部品２２を疑似ウエーハ６から切り出す際に、絶縁物質５の部分を切断し、従来例のようにシリコン部を切断することがないので、チップ状電子部品２２本体への悪影響（歪みやばり、亀裂等のダメージ）が少なく、さらに、大部分が絶縁物質５で覆われているために実装ハンドリングがし易く、良好な実装信頼性が得られる。
【００７６】
また、上述したように、ＩＣチップだけでなく、チップ抵抗やコンデンサ等の受動部品、及び光学系部品等の多肢にわたる部品を一括して組み込むことができるので、高機能モジュールとしての形態も可能となる。
【００７７】
さらに、半導体チップ４の厚さ、大きさにとらわれずに作製することができ、かつチップ状電子部品２２自体の厚さを非常に薄くすることができる。
【００７８】
なお、図６（ｂ）に図６（ａ）のＸ−Ｘ線部分断面図を示すように、チップ状電子部品２２は、絶縁物質５にその厚さ方向に貫通した凹状部２３が形成され、これらに導電性樹脂１４ａが充填されているので、外側からの摩擦等に対して磨耗を生じ難く、耐久性に優れている。この導電性樹脂層１４により、半導体チップ４のＡｌパッド電極１０と再配線電極部１９ａ及び１９ｂとが電気的に良好に接続される。
【００７９】
前記積層等の実装は、樹脂からなる絶縁物質５上の前記端子としての再配線電極部１９ａ、１９ｂを介して行うことができ、即ち、前記積層の接続及び実装の接続部を、図１１に示すようなＦａｎ−Ｏｕｔした絶縁物質５の部分で行うことができる。従って、線膨張係数を類似とすることができ、高信頼性のスタックドパッケージ（積層されたチップ状電子部品）を提供することができる。
【００８０】
図７は、上記のようにして作製されたチップ状電子部品２２（厚みは、例えば１００〜２５０μｍ）の複数個が積層された実装構造の一例を示す概略断面図である。図示するように、各チップ状電子部品２２ａ、２２ｂ、２２ｃは、はんだバンプ２４を介してそれぞれに対応した再配線電極部１９同士が接続され、積層体の構造をなしている。そして、この積層体は、例えばインターポーザ基板２５にはんだバンプ２４を用いて接続され、更に回路基板（マザーボード）（図示省略）に接続される。図示省略したが、上記の積層体を直接に回路基板に接続することも勿論可能である。
【００８１】
本発明に基づくチップ状電子部品２２は、その両面に、導電性樹脂層１４を介して電気的に接続された再配線電極部１９を有するので、積層構造を形成した場合でも、はんだバンプ２４等を用いることができ、従来例に比べて厚みを低減することができる。また、前記受動部品を含む複数個又は複数種の半導体チップ４を有し、高機能モジュールである本発明に基づくチップ状電子部品２２を３次元的に積層することで、上記した高信頼性を保ちながら、高性能化を図ることができる。
【００８２】
これら高機能モジュールは、例えば小型高速高周波の移動体通信機器や携帯端末、超小型パソコン（ＰＣ：Ｐｅｒｓｏｎａｌ Ｃｏｍｐｕｔｅｒ）等のあらゆる電子産業製品に使用することができる。
【００８３】
以上、本発明を実施の形態について説明したが、上述の例は、本発明の技術的思想に基づき種々に変形が可能である。
【００８４】
例えば、図８（ｂ）及び図９に示すように、疑似ウエーハ６のダイシングエリア１２に、複数個又は複数種の半導体チップ４のそれぞれに対応した貫通孔１３を複数列設ける例を説明したが、本発明はこれに限らない。即ち、前記個片化を行う前の状態では導電性樹脂層１４を介しての導通検査を行わず、前記個片化を行い、得られたチップ状電子部品２２のそれぞれに対して導電性樹脂層１４を介しての導通検査を行う場合は、上述した貫通孔１３を複数列設けるのに代えて、図１０に示すように、疑似ウエーハ６のダイシングエリア１２に、複数個又は複数種の半導体チップ４に共用される貫通孔１３を一列に設けてもよい。前記一列の場合、上記した複数列の場合に比べて貫通孔１３の径をより大きくすることができる。
【００８５】
また、図６（ｂ）に示すように、絶縁物質５からなる前記絶縁物質層にその厚さ方向に貫通した凹状部２３が形成され、これらに導電性樹脂１４ａが充填されている例を説明したが、例えば図６（ｃ）に示すように、前記絶縁物質層に貫通孔２６が形成され、これらに導電性樹脂１４ａが充填されていてもよい。この場合は、導電性樹脂１４ａが絶縁物質層に囲まれているために、耐久性が一層向上する。
【００８６】
【発明の作用効果】
本発明の製造方法によれば、前記絶縁物質からなる前記疑似ウエーハの前記ダイシングエリアに、前記疑似ウエーハの厚さ方向に貫通した前記貫通孔を設けるので、シリコンからなる半導体ウエーハそのものに貫通孔を形成し、この貫通孔に導電性物質を埋め込む加工を施すのに比べ、遥かに容易かつ信頼性が高く、また低コストである。また、前記貫通孔の孔径を比較的自由に選択することができる。
【００８７】
また、前記導電性樹脂は前記貫通孔に充填し易く、かつ前記絶縁物質との密着性に優れている。従って、例えば前記複数個又は複数種の半導体チップ間を前記ダイシングエリアに沿って切断する工程等で受ける外的力に対して、優れた耐久性を有する。これは、個片化された後のチップ状電子部品の形態又はチップ状電子部品の複数個が積層された形態においても同様である。
【００８８】
また、アナログ、デジタルにとらわれず、個々の良品チップのみ使用して組み合わせ、前記チップ状電子部品に個片化することができるので、ウエーハあたりの歩留まりにとらわれず、低コスト化することができる。また、自社製ウエーハのみならず、他社から購入したベアチップも取り混ぜての作製が可能である。
【００８９】
また、前記チップ状電子部品を前記疑似ウエーハから切り出す際に、前記絶縁物質の部分を切断し、従来例のようにシリコン部を切断することがないので、前記チップ状電子部品本体への悪影響（歪みやばり、亀裂等のダメージ）が少なく、さらに、大部分が前記絶縁物質で覆われているために実装ハンドリングがし易く、良好な実装信頼性が得られる。
【００９０】
また、上述したように、ＩＣチップだけでなく、チップ抵抗やコンデンサ等の受動部品、及び光学系部品等の多肢にわたる部品を一括して組み込むことができるので、高機能モジュールとしての形態も可能となる。
【００９１】
さらに、前記半導体チップの厚さ、大きさにとらわれずに作製することができ、かつ前記チップ状電子部品自体の厚さを非常に薄くすることができる。
【００９２】
そして、本発明の製造方法によって得られるチップ状電子部品及びその実装構造によれば、前記積層等の実装は樹脂からなる前記絶縁物質層上の前記端子を介して行うことができる。このため、線膨張係数を類似とすることができ、高信頼性のスタックドパッケージ（積層されたチップ状電子部品）を提供することができる。
【００９３】
さらに、前記受動部品を含む前記複数個又は複数種の半導体チップを有し、高機能モジュールである本発明のチップ状電子部品を３次元的に積層することで、上記した高信頼性を保ちながら、高性能化を図ることができる。
【図面の簡単な説明】
【図１】本発明の実施の形態における、本発明に基づく製造方法を工程順に示す概略断面図である。
【図２】同、本発明に基づく製造方法を工程順に示す概略断面図である。
【図３】同、本発明に基づく製造方法を工程順に示す概略断面図である。
【図４】同、本発明に基づく製造方法を工程順に示す概略断面図である。
【図５】同、本発明に基づく製造方法を工程順に示す概略断面図である。
【図６】同、本発明に基づくチップ状電子部品の概略図である。
【図７】同、本発明に基づくチップ状電子部品の実装構造を示す概略図である。
【図８】同、本発明に基づく製造方法において、前記貫通孔を形成したときの概略平面図である。
【図９】同、本発明に基づく製造方法において、前記貫通孔に前記導電性樹脂を充填し、さらに再配線を形成したときの概略平面図である。
【図１０】同、他の本発明に基づく製造方法において、前記貫通孔に前記導電性樹脂を充填し、さらに再配線を形成したときの概略平面図である。
【図１１】同、前記半導体チップの概略平面図である。
【図１２】従来例による、チップ状電子部品の製造方法の概略断面図である。
【図１３】同、チップ状電子部品の製造方法の概略断面図である。
【図１４】同、チップ状電子部品の積層構造の概略断面図である。
【図１５】他の従来例による、チップ状電子部品の概略断面図である。
【図１６】同、チップ状電子部品の積層構造の概略断面図である。
【符号の説明】
１…基体、２ａ、２ｂ…粘着材層、３…両面テープ基材、４…半導体チップ、
５…絶縁物質、６…疑似ウエーハ、７…裏面、８…保護膜、
９…シリコン（Ｓｉ）基板、１０…Ａｌパッド電極、
１１…パッシベーション膜、１２…ダイシングライン（エリア）、
１３、２６…貫通孔、１４ａ…導電性樹脂、１４…導電性樹脂層、
１５…スキージ、１６…無電解Ｃｕめっき、１７…表面、１８…再配線、
１９ａ、１９ｂ…再配線電極部、２０…ダイシングブレード、
２１…ダイシング、２２…チップ状電子部品、２３…凹状部、
２４…はんだバンプ、２５…インターポーザ基板[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a chip-shaped electronic component suitable for manufacturing a semiconductor device, a manufacturing method thereof, and a mounting structure thereof.
[0002]
[Prior art]
In recent years, with the downsizing of semiconductor component sets composed of modules, there is a demand for stack structures of these semiconductor packages for the purpose of improving the mounting efficiency of semiconductor chips and interposers that are chip-shaped components. is increasing.
[0003]
However, when a semiconductor chip is packaged, its planar size is larger than the chip area, so that the effect of the stack structure cannot be fully exploited.
[0004]
In order to solve this problem, research on a method that makes it possible to form an external terminal for electrical connection with an external circuit on the back surface of a semiconductor wafer by providing a through hole in a semiconductor wafer made of silicon. Development is progressing toward practical use (for example, refer to Patent Document 1 described later).
[0005]
Hereinafter, an example of the above-described method according to Patent Document 1 described later will be described with reference to FIGS. 12, 13, and 14.
[0006]
First, as shown in FIG. 12A, a semiconductor wafer 51 as a substrate made of silicon is manufactured, and an insulating material is formed on the semiconductor wafer 51 by a spin coating method, a printing method, or the like. Next, the insulating material is processed into a predetermined pattern by etching or the like to form an insulating layer 52 having an opening 53, and an electrode material is further formed on the semiconductor wafer 51 and the insulating layer 52 so as to cover them. It is formed by sputtering or the like. Next, the land 54 is formed by processing the electrode material into a predetermined pattern by etching or the like.
[0007]
Next, an interlayer insulating material is formed on the semiconductor wafer 51, the land 54, and the insulating layer 52 by a spin coating method, a printing method, or the like so as to cover them. The interlayer insulating material is processed into a predetermined pattern by etching or the like, and another opening 58 communicating with the opening 53 is provided in the scribe line region, and further, an interlayer insulating film 56 having a via hole is formed on the land 54. To do.
[0008]
Next, a wiring material is formed on the semiconductor wafer 51, the land 54, the interlayer insulating film 56, and the insulating layer 52 by sputtering or the like so as to cover them. The wiring material is processed into a predetermined pattern by etching or the like to form a wiring 59 provided continuously in the via hole and on the interlayer insulating film 56. Then, a wiring protective material is formed on the semiconductor wafer 51, the interlayer insulating film 56, the wiring 59, and the insulating layer 52 by a spin coating method, a printing method, or the like so as to cover them.
[0009]
Next, the wiring protective material is processed into a predetermined pattern by etching or the like to form the wiring protective layer 61 having the opening 62 and the via hole 74 on the wiring 59. Here, a laminated body including the insulating layer 52, the land 54, the interlayer insulating film 56, the wiring 59, and the wiring protective layer 61 is referred to as a surface wiring portion 63 for each partition unit of a chip-shaped electronic component 79 described later.
[0010]
Next, as shown in FIG. 12B, a part of the semiconductor wafer 51 is removed by RIE (Reactive Ion Etching) or the like from the back surface of the semiconductor wafer 51 on the opposite side of the front surface wiring portion 63, and the semiconductor wafer 51 is removed. The through holes 64 reaching the respective lands 54 are formed.
[0011]
Next, as shown in FIG. 13C, in order to electrically insulate a conductive layer 66 and a semiconductor wafer 51 described later, an insulating material is continuously formed from the inner wall surface of the through hole 64 to the back surface of the semiconductor wafer 51. Is applied to a predetermined thickness. Here, an insulating material is deposited on the bottom of the through hole 64 so that the land 54 is exposed.
[0012]
Next, the insulating material is etched to leave the insulating film 65 in the through hole 64 and the peripheral portion of the through hole 64 on the back surface of the semiconductor wafer 51. Further, in the through hole 64, for example, electroless plating and electrolytic plating are performed. The conductive layer 66 is formed by filling the conductive material by normal through-hole plating using a combination of methods. The conductive material at this time contacts the land 54 and fills up to the surface of the insulating film 65 on the back surface of the semiconductor wafer. Then, after the solder paste is printed on the conductive layer 66 on the back surface of the semiconductor wafer, the solder paste is melted by a wet back method to form solder bumps 69.
[0013]
Next, the semiconductor wafer 51 provided with the conductive layer 66, the solder bump 69, the surface wiring portion 63, and the like is diced 71 along the scribe line 73 with a blade 70 (or laser), and a chip as shown in FIG. Into individual electronic parts 79.
[0014]
Next, as shown in FIG. 13E, the solder paste is transferred into the via hole 74 on the wiring 59 on the surface wiring portion 63 of the substrate 51 of the chip-shaped electronic component 79 by a printing method, and further wet back. Solder paste is melted by the method to form solder bumps 78.
[0015]
For example, as shown in FIG. 14, the chip-shaped electronic component 79 manufactured in this way can be mounted in an MCM (Multi Chip Module) by stacking the chip-shaped electronic components 79 a and 79 b up and down via solder bumps 78 ′. .
[0016]
On the other hand, the present applicant can perform wafer batch processing, and even when obtained in the state of the art LSI (Large Scale Integrated Circuit) or bare chip, a semiconductor chip that can be provided with high yield, low cost and high reliability (See, for example, Patent Document 2 below).
[0017]
That is, in the invention according to Patent Document 2, first, an adhesive means having adhesive strength before processing but having reduced adhesive strength after processing is pasted on a substrate, and a plurality of or plural kinds of adhesive means are attached on the adhesive means. The semiconductor chip is fixed with its electrode surface facing down, and a protective substance is deposited on the entire surface including the space between the semiconductor chips. Next, the adhesive means is subjected to a predetermined treatment to reduce the adhesive force of the adhesive means, and the pseudo wafer in which the semiconductor chip is fixed with the protective substance on the side surface and the back surface thereof is peeled off, and the semiconductor chip is interposed between the semiconductor chips. The protective substance is cut to separate the chip-shaped electronic component 80 as shown in FIG. The obtained chip-shaped electronic component 80 can be electrically connected to a rewiring interposer 82 via, for example, a bump electrode 81 as shown in FIG.
[0018]
Then, as shown in FIG. 16, a plurality of chip-like electronic components 80 connected to the interposer 82 can be stacked via solder balls 83, and this stacked body can be electrically connected to the circuit board 84. .
[0019]
According to the manufacturing method according to Patent Document 2, when the chip-shaped electronic component is cut out from the pseudo wafer, the protective substance portion is cut, and thus adverse effects on the chip-shaped electronic component main body (damage such as distortion, flash, cracks, etc.). Can be suppressed.
[0020]
In addition, by cutting out good chip-shaped electronic components from the pseudo wafer and rearranging them, it becomes as if all the products are wafers of good chips, and solder bump processing etc. can be performed in a batch of wafers, yielding at low cost. A solder bump chip for flip chip can be formed well. And solder bump processing etc. become possible not only with the company-made wafer but also with bare chips purchased from other companies.
[0021]
In addition, since the chip side surface and the back surface are covered with the protective material, Ni electroless plating can be performed, and the chip side surface and the back surface are also protected by the protective material. In this case, the chip is protected and good mounting reliability can be obtained.
[0022]
[Patent Document 1]
JP-A-5-63137 (page 2, column 2, line 25 to page 3, column 3, line 7, FIG. 1)
[Patent Document 2]
JP 2001-313350 A (page 6, column 9, line 42 to page 7, column 12, line 21, FIGS. 1 to 5)
[0023]
[Problems to be solved by the invention]
However, the method according to Patent Document 1 as described above applies an etching method such as RIE to form the through-hole 64 in the semiconductor wafer 51 made of silicon in the step shown in FIG. In this processing step, since an expensive semiconductor manufacturing apparatus is used, the cost becomes high. Further, since the through-hole 64 is formed in the semiconductor wafer 51 made of a relatively fragile material, the processing time is increased and the manufacturing cost is further increased in order to prevent the semiconductor wafer 51 from being damaged.
[0024]
Further, since the silicon itself constituting the semiconductor wafer 51 is conductive, when the conductive layer 57 is provided in the through hole 64 shown in FIG. 13C, the inner wall portion of the through hole 64 and the solder bump are provided in advance. It is necessary to selectively form the insulating film 65 at the formation site and perform an insulation separation process, which also increases the number of manufacturing steps and deteriorates workability.
[0025]
Further, when the solder bump 69 protrudes from the insulating film 65 when the external connection solder bump 69 is formed, a short circuit occurs between the solder bump 69 and the semiconductor wafer 51 or between the solder bumps 69.
[0026]
Further, since the silicon constituting the semiconductor wafer 51 is fragile and is easily broken even with a slight impact, it becomes difficult to handle the semiconductor wafer 51 or the structure from which the silicon is exposed.
[0027]
On the other hand, Patent Document 2 has a point to be improved while having the above-described excellent features.
[0028]
That is, as shown in FIG. 15, the obtained chip-shaped electronic component 80 has an electrode 85 that can be connected to the outside only on one side thereof. As shown in FIG. 2, after the chip-shaped electronic component 80 and the interposer 82 are electrically connected in advance, a plurality of chip-shaped electronic components 80 must be stacked using the solder balls 83. For this reason, the thickness as a whole becomes large.
[0029]
The present invention has been made in order to solve the above-described problems, and its purpose is to be able to manufacture easily, reliably and at low cost, and to further enhance the functionality as a single component. An object of the present invention is to provide a chip-shaped electronic component such as a semiconductor integrated circuit chip component that can be manufactured, a method of manufacturing the same, and a mounting structure thereof.
[0030]
[Means for Solving the Problems]
That is, the present invention includes a step of fixing a plurality or types of semiconductor chips on a substrate with their electrode surfaces facing down; and depositing an insulating material on the entire surface including the plurality or types of semiconductor chips. A step of peeling the pseudo wafer to which the semiconductor chip is fixed from the base; a step of providing a through-hole penetrating in the thickness direction of the pseudo wafer in the dicing area of the pseudo wafer made of the insulating material; Filling the through hole with a conductive resin; forming a wiring connected to the conductive resin on one side of the pseudo wafer and the other side opposite to the pseudo wafer; Cutting between individual semiconductor chips or a plurality of types of semiconductor chips along the dicing area to separate the conductive resin into chip-shaped electronic components held in the thickness direction. Those relating to the manufacturing method of electronic chip components.
[0031]
Further, wiring and terminals are formed on one surface side and the other surface side opposite to the one surface side, respectively, an insulating material layer is deposited on at least the side surface, and the one surface side and the other surface side are coated. The present invention relates to a chip-shaped electronic component in which a conductive resin layer for electrically connecting the respective wirings on the surface side is formed on or in the insulating material layer, and further includes a plurality of chip-shaped electronic components of the present invention. The present invention relates to a chip-shaped electronic component mounting structure in which the individual pieces are stacked as integrated circuit chips via the terminals on the one surface side and the other surface side.
[0032]
Here, the “chip-shaped electronic component” in the present invention is not limited to a single chip, but includes a plurality of different semiconductor chips such as a CPU (Central Processing Unit) and a memory, or resistors, capacitors, and the like. Mounting components can be arranged and combined arbitrarily in a plane, fixed with the insulating material such as resin, and re-wired together to form and use as a single high-function module (system-in-package) It is possible.
[0033]
According to the manufacturing method of the present invention, the through-hole penetrating in the thickness direction of the pseudo wafer is provided in the dicing area of the pseudo wafer made of the insulating material. Compared to forming a through hole in the semiconductor wafer itself and embedding a conductive material in the through hole, the semiconductor wafer is much easier, more reliable, and lower in cost. Moreover, the hole diameter of the said through-hole can be selected comparatively freely.
[0034]
Further, the conductive resin is easy to fill the through hole and has excellent adhesion to the insulating material. Therefore, for example, it has excellent durability against the external force received in the process of cutting the plurality or types of semiconductor chips along the dicing area. The same applies to the form of the chip-shaped electronic component after being singulated or the form in which a plurality of chip-shaped electronic components are stacked.
[0035]
In addition, it is possible to reduce the cost without being restricted by the yield per wafer because the chip-like electronic components can be separated into individual pieces by combining only good products without being limited to analog and digital. It is also possible to produce not only in-house manufactured wafers but also bare chips purchased from other companies.
[0036]
Further, when the chip-shaped electronic component is cut out from the pseudo wafer, the insulating material portion is not cut and the silicon portion is not cut as in the conventional example. (Strain, flash, damage such as cracks) is small, and since most of them are covered with the insulating material, mounting handling is easy and good mounting reliability can be obtained.
[0037]
In addition, as described above, not only IC chips but also passive components such as chip resistors and capacitors, as well as multiple components such as optical system components, can be integrated at the same time, so it can be configured as a high-function module. It becomes.
[0038]
Further, the semiconductor chip can be manufactured regardless of the thickness and size of the semiconductor chip, and the thickness of the chip-like electronic component itself can be made very thin.
[0039]
And according to the chip-shaped electronic component obtained by the manufacturing method of the present invention and its mounting structure, the stacking and the like can be mounted through the terminals on the insulating material layer made of resin. For this reason, linear expansion coefficients can be made similar, and a highly reliable stacked package (stacked chip-shaped electronic components) can be provided.
[0040]
In addition, the above-described high reliability can be maintained by three-dimensionally stacking the chip-shaped electronic components of the present invention, which is a high-functional module, having the plurality or types of semiconductor chips including the passive components. High performance can be achieved.
[0041]
DETAILED DESCRIPTION OF THE INVENTION
In the manufacturing method of the present invention, it is preferable that the through hole is formed in the dicing area of the pseudo wafer by machining such as a drill or light irradiation such as laser.
[0042]
Further, it is preferable that a plurality of rows of through holes corresponding to each of the plurality or types of semiconductor chips are provided in the dicing area of the pseudo wafer. In this case, it is possible to perform a continuity test through the conductive resin layer in a state before the singulation.
[0043]
On the other hand, in the state before performing the singulation, the continuity inspection through the conductive resin layer is not performed, the singulation is performed, and the obtained chip-like electronic component is When conducting a continuity test through a conductive resin layer, the plurality of or a plurality of types of semiconductor chips are shared in the dicing area of the pseudo wafer instead of providing a plurality of the through holes described above. The through holes may be provided in a row. In the case of the one row, the diameter of the through hole can be made larger than in the case of the plurality of rows described above.
[0044]
In addition, it is preferable that connection electrodes for the wirings are respectively formed on the conductive resin filled in the through holes on the front and back sides of the pseudo wafer.
[0045]
The chip-like electronic component of the present invention has a wiring and a terminal formed on one surface side and the other surface side opposite to the one surface side, an insulating material layer is deposited on at least the side surface, and The conductive resin layer is characterized in that a conductive resin layer for electrically connecting the wirings on one side and the other side is formed on or in the insulating material layer. Is preferably present in the dicing area.
[0046]
In addition, it is desirable that a concave portion or a through-hole penetrating in the thickness direction is formed in the insulating material layer, and these are filled with the conductive resin.
[0047]
Next, a preferred embodiment of the present invention will be described with reference to the drawings. 1-5 is a schematic sectional drawing which shows an example of the manufacturing method based on this invention in process order.
[0048]
First, as shown to Fig.1 (a), the double-sided tape base material 3 which has the adhesive material layers 2a and 2b on both surfaces is affixed on the base | substrate 1 using a laminator.
[0049]
As the substrate 1, one having good flatness and capable of reading a marker by an apparatus for arranging a semiconductor chip 4 described later is preferably used, and examples thereof include glass and silicon (Si).
[0050]
In addition, as described above, the double-sided tape base material 3 is preferably used so that it can transmit light so that a device for placing the semiconductor chip 4 described later can read the marker, for example, polyethylene terephthalate (PET) or the like. Examples thereof include polyimide.
[0051]
Furthermore, as the adhesive material layers 2a and 2b, an adhesive material such as an existing self-peeling adhesive material of the same type can be used on both surfaces of the double-sided tape base material 3. For example, the base 1 of the double-sided tape base material 3 is disposed. In view of the process, it is preferable to use a self-peeling type adhesive material on the surface side to be processed and an acrylic adhesive material on the surface side on which semiconductor chips 4 to be described later are arranged. The double-sided tape base 3 having the adhesive layers 2a and 2b may be attached to the entire surface of the base 1 as shown in the figure, but is attached locally (patterned) only to the fixed portion of the semiconductor chip 4. Alternatively, it may be attached to the surface of the semiconductor chip 4 and attached to the substrate 1. In the latter case, it becomes easier to remove the pseudo wafer described later.
[0052]
Next, as shown in FIG. 1 (b), a plurality or types of semiconductor chips 4 confirmed as non-defective products are arranged with the chip surface (device surface) facing the adhesive material layer 2b, and the adhesive material layer 2b is arranged. paste. What is important here is that only good semiconductor chips 4 are rearranged on the substrate 1 regardless of the chips made by other companies or other companies.
[0053]
Next, as shown in FIG. 1C, an insulating material 5 such as polyester is deposited on the entire surface including a plurality of or a plurality of types of semiconductor chips 4. Examples of the method include pressure molding using a mold press and molding using a printing method. At this time, since the semiconductor chip 4 is held and fixed by the adhesiveness of the adhesive material layer 2b, it does not move. In the printing method, the pressure forming method is more preferable because of void generation due to air remaining and entrainment, and the possibility of unfilled narrow gaps.
[0054]
In the pressure molding method, the substrate 1 on which the semiconductor chips 4 are arranged is placed on a mold, and a resin (insulating substance) 5 is placed thereon and molded. The mold temperature is limited by the reaction start temperature of the material of the pressure-sensitive adhesive layer 2b, and is preferably about 150 ° C. or less, for example. The heating and pressing time varies depending on the resin 5 to be used, and for example, about 100 KN and about 10 minutes are preferable.
[0055]
Next, as shown in FIG. 1 (d), the pseudo wafer 6 to which the semiconductor chip 4 is fixed is peeled from the substrate 1. The peeling method depends on the material of the pressure-sensitive adhesive layers 2a and 2b. For example, UV irradiation may be performed, or heating may be performed in an oven at 130 to 150 ° C. for about 5 to 10 minutes. Thereby, as shown in FIG. 2E, the substrate 1 is forcibly separated from the adhesive layer 2a, and the substrate 1 and the pseudo wafer 6 can be separated.
[0056]
The double-sided tape base material 3 and the adhesive material layers 2a and 2b remaining on the pseudo wafer 6 side can be easily peeled off by hand. Then, the residue on the surface of the semiconductor chip 4 is removed using a chemical solution (FIG. 2 (f)).
[0057]
Next, as shown in FIG. 2G, the back surface 7 of the pseudo wafer 6 is ground to a predetermined thickness using a BGR (Back Grind) apparatus or the like. Here, the thickness of the pseudo wafer 6 can be less than 100 μm, but is preferably about 100 μm or more and 300 μm or less in order to maintain physical strength.
[0058]
The pseudo wafer 6 formed in a lump as described above is completed.
[0059]
Next, as shown in FIG. 3 (h), a protective film 8 a is applied to the back surface 7 side of the ground pseudo wafer 6. For example, the semiconductor chip 4 is formed by forming an Al pad electrode 10 and a passivation film 11 on a Si substrate 9 via a SiO 2 film (not shown). As the protective film 8a, one having a small curing shrinkage is preferably used, and examples thereof include an epoxy photosensitive insulating resin.
[0060]
Next, as shown in a schematic cross-sectional view in FIG. 3 (i) and a schematic plan view in FIG. 8, the through-holes 13 corresponding to the plurality or types of semiconductor chips 4 are formed in the dicing area 12 of the pseudo wafer 6. Are provided in multiple rows. A mechanical method using a drill or the like is simple as a method for forming the through holes 13, but light irradiation processing such as laser may be used when a large number of through holes 13 are formed quickly.
[0061]
Further, when the number of through holes 13 is large and the diameter thereof is small, it is preferable to provide the through holes 13 at a position slightly shifted from the dicing line 12 as shown in FIG. Here, it is important that the volume of the conductive resin layer 14 remaining after dicing, which will be described later, has a sufficient volume for conduction.
[0062]
Although the thickness t of the pseudo wafer 6 is arbitrary, it can be assumed to be between 120 μm and 250 μm, for example.
[0063]
According to the manufacturing method of the present invention, since the through-hole 13 penetrating in the thickness t direction of the pseudo wafer 6 is provided in the dicing area 12 of the pseudo wafer 6 made of the insulating material 5, as in the conventional example, silicon is used. Compared to forming a through hole in the semiconductor wafer itself and embedding a conductive material in the through hole, the semiconductor wafer is much easier, more reliable, and lower in cost. Moreover, the diameter of the through-hole 13 can be selected comparatively freely, for example, can be 150-300 micrometers in diameter.
[0064]
Next, as shown in FIG. 3J, the through hole 13 is filled with a conductive resin 14a. A silver paste is generally used as the conductive resin 14a, but a conductive paste material such as Cu can also be used. As a filling method, there is a printing method using a squeegee 15 or the like as a method of filling the conductive resin 14a into the innumerable through holes 13 in one pseudo wafer 6 in a lump.
[0065]
The conductive resin 14 a is easy to fill the through hole 13 and has excellent adhesion to the insulating material 5. Therefore, it has excellent durability against an external force received in a process of cutting a plurality or a plurality of types of semiconductor chips 4 described later along the dicing area 12. The same applies to the form of the chip-shaped electronic component after being singulated or the form in which a plurality of chip-shaped electronic components are stacked.
[0066]
Further, since a plurality of rows of through holes 13 corresponding to each of the plurality or types of semiconductor chips 4 are provided in the dicing area 12 of the pseudo wafer 6, a conductive resin is used at the present stage before the individualization. A continuity test can be performed through the through-hole 13 filled with 14a.
[0067]
Next, as shown in FIG. 4 (k), after the conductive resin 14a is cured and hardened to form the conductive resin layer 14, electroless Cu is formed on the portions of the conductive resin layer 14 on both sides of the pseudo wafer 6. Apply plating. This is to make the connection between the conductive resin layer 14 and the rewiring 18 described later more reliable.
[0068]
Next, as shown in FIG. 4L, the rewiring 18 is formed on the surface 17 side of the semiconductor chip 4. The rewiring 18 electrically connects the wiring (not shown) between the semiconductor chips 4, the Al pad electrode 10 of the semiconductor chip 4 and the conductive resin layer 14, and further forms a rewiring electrode portion 19 described later. Used for As a method for forming the rewiring 18, first, the protective film 8b is applied to protect the surface 17 side of the semiconductor chip, and the Al pad electrode 10 and the electroless Cu plating 16 are opened. Next, titanium (Ti) is sputtered on the entire surface as a barrier metal, and a Cu thin film is sputtered on the entire surface as a plating electrode. A plating resist is further coated thereon, exposed and developed, and Cu wiring is patterned. . Next, Cu is deposited by electroplating. A necessary thickness for the rewiring 18 is, for example, about 3 to 8 μm. Then, by removing the resist and further removing Cu and Ti by etching, a Cu rewiring pattern 18 as shown in FIG. 4L is completed.
[0069]
Next, as shown in the schematic cross-sectional view of FIG. 4M and the schematic plan view of FIG. 9, the rewiring 18 is patterned on the back surface 7 side in the same manner as described above. Further, a protective film 8c is applied to the entire surface 17 and the back surface 7 to open predetermined positions for the rewiring electrode portions 19a and 19b, and the rewiring process is completed. As the protective film 8c, a film having good patternability is preferably used, and examples thereof include an epoxy photosensitive insulating resin.
[0070]
Next, as shown in FIG. 5 (n), dicing 21 is performed between a plurality or types of semiconductor chips 4 along a dicing line (area) 12 using a dicing blade 20.
[0071]
As described above, a chip-shaped electronic component 22 that holds the conductive resin layer 14 in the thickness direction as shown in FIG. 6A can be manufactured.
[0072]
According to the manufacturing method of the present invention, since the through-hole 13 that penetrates in the thickness direction of the pseudo wafer 6 is provided in the dicing area 12 of the pseudo wafer 6 made of the insulating material 5, the through-hole is formed in the semiconductor wafer itself made of silicon. Compared with the conventional method in which the through hole is processed and the conductive material is embedded in the through hole, the method is much easier, more reliable, and lower in cost. Moreover, the hole diameter of the through-hole 13 can be selected comparatively freely.
[0073]
In addition, the conductive resin 14 a is easy to fill the through hole 13 and has excellent adhesion to the insulating material 5. Therefore, for example, it has excellent durability against an external force received in a process of cutting a plurality or types of semiconductor chips 4 along the dicing area 12. This also applies to the form of the chip-shaped electronic component 22 after being singulated or the form in which a plurality of chip-shaped electronic components 22 are stacked.
[0074]
Further, it is possible to reduce the cost without being restricted by the yield per pseudo wafer 6 because it is possible to combine only individual non-defective chips and combine them into chip-like electronic components 22 without being restricted to analog and digital. it can. It is also possible to produce not only in-house manufactured wafers but also bare chips purchased from other companies.
[0075]
Further, when the chip-shaped electronic component 22 is cut out from the pseudo wafer 6, the insulating material 5 is not cut and the silicon portion is not cut as in the conventional example. Further, since most of the material is covered with the insulating material 5, mounting handling is easy and good mounting reliability can be obtained.
[0076]
In addition, as described above, not only IC chips but also passive components such as chip resistors and capacitors, as well as multiple components such as optical system components, can be integrated at the same time, so it can be configured as a high-function module. It becomes.
[0077]
Further, the semiconductor chip 4 can be manufactured regardless of the thickness and size thereof, and the thickness of the chip-shaped electronic component 22 itself can be made very thin.
[0078]
6B shows a partial cross-sectional view taken along the line XX of FIG. 6A, the chip-like electronic component 22 has a recessed portion 23 formed through the insulating material 5 in the thickness direction. Since these are filled with the conductive resin 14a, they are less likely to be worn against friction from the outside and have excellent durability. With this conductive resin layer 14, the Al pad electrode 10 of the semiconductor chip 4 and the rewiring electrode portions 19 a and 19 b are electrically connected to each other in an excellent manner.
[0079]
The mounting such as the stacking can be performed through the rewiring electrode portions 19a and 19b as the terminals on the insulating material 5 made of resin. That is, the connection of the stacking and the connecting portion of the mounting are illustrated in FIG. This can be done in the portion of the fan-out insulating material 5 as shown. Therefore, the linear expansion coefficient can be made similar, and a highly reliable stacked package (stacked chip-shaped electronic components) can be provided.
[0080]
FIG. 7 is a schematic cross-sectional view showing an example of a mounting structure in which a plurality of chip-shaped electronic components 22 (thickness is, for example, 100 to 250 μm) manufactured as described above are stacked. As shown in the figure, each chip-like electronic component 22a, 22b, 22c is connected to the corresponding redistribution electrode portions 19 via solder bumps 24 to form a laminated structure. The laminate is connected to, for example, the interposer substrate 25 using solder bumps 24 and further connected to a circuit board (mother board) (not shown). Although not shown in the drawings, it is of course possible to directly connect the above laminate to the circuit board.
[0081]
Since the chip-like electronic component 22 according to the present invention has the rewiring electrode portions 19 electrically connected via the conductive resin layer 14 on both sides thereof, the solder bumps 24 and the like are formed even when a laminated structure is formed. The thickness can be reduced as compared with the conventional example. Further, the above-described high reliability can be achieved by three-dimensionally laminating the chip-like electronic component 22 according to the present invention, which has a plurality or a plurality of types of semiconductor chips 4 including the passive component and is a high-function module. High performance can be achieved while maintaining.
[0082]
These high-function modules can be used for all electronic industrial products such as small-sized, high-speed and high-frequency mobile communication devices, portable terminals, and personal computers (PCs).
[0083]
As mentioned above, although embodiment of this invention was described, the above-mentioned example can be variously modified based on the technical idea of this invention.
[0084]
For example, as shown in FIGS. 8B and 9, the example in which a plurality of rows of through holes 13 corresponding to each of a plurality or types of semiconductor chips 4 is provided in the dicing area 12 of the pseudo wafer 6 has been described. The present invention is not limited to this. That is, in the state before the singulation, the continuity inspection through the conductive resin layer 14 is not performed, the singulation is performed, and a conductive resin is obtained for each of the obtained chip-like electronic components 22. When conducting a continuity test through the layer 14, instead of providing a plurality of rows of the through-holes 13 as described above, as shown in FIG. The through holes 13 shared by the chips 4 may be provided in a row. In the case of the one row, the diameter of the through hole 13 can be made larger than in the case of the plurality of rows described above.
[0085]
Further, as shown in FIG. 6B, an example in which a concave portion 23 penetrating in the thickness direction is formed in the insulating material layer made of the insulating material 5 and filled with a conductive resin 14a will be described. However, for example, as shown in FIG. 6C, through-holes 26 may be formed in the insulating material layer, and these may be filled with a conductive resin 14a. In this case, since the conductive resin 14a is surrounded by the insulating material layer, the durability is further improved.
[0086]
[Effects of the invention]
According to the manufacturing method of the present invention, since the through hole penetrating in the thickness direction of the pseudo wafer is provided in the dicing area of the pseudo wafer made of the insulating material, the through hole is formed in the semiconductor wafer itself made of silicon. Compared with the process of forming and embedding a conductive material in the through hole, it is much easier, more reliable, and less expensive. Moreover, the hole diameter of the said through-hole can be selected comparatively freely.
[0087]
Further, the conductive resin is easy to fill the through hole and has excellent adhesion to the insulating material. Therefore, for example, it has excellent durability against the external force received in the process of cutting the plurality or types of semiconductor chips along the dicing area. The same applies to the form of the chip-shaped electronic component after being singulated or the form in which a plurality of chip-shaped electronic components are stacked.
[0088]
In addition, it is possible to reduce the cost without being restricted by the yield per wafer because the chip-like electronic components can be separated into individual pieces by combining only good products without being limited to analog and digital. It is also possible to produce not only in-house manufactured wafers but also bare chips purchased from other companies.
[0089]
Further, when the chip-shaped electronic component is cut out from the pseudo wafer, the insulating material portion is not cut and the silicon portion is not cut as in the conventional example. (Strain, flash, damage such as cracks) is small, and since most of them are covered with the insulating material, mounting handling is easy and good mounting reliability can be obtained.
[0090]
In addition, as described above, not only IC chips but also passive components such as chip resistors and capacitors, as well as multiple components such as optical system components, can be integrated at the same time, so it can be configured as a high-function module. It becomes.
[0091]
Further, the semiconductor chip can be manufactured regardless of the thickness and size of the semiconductor chip, and the thickness of the chip-like electronic component itself can be made very thin.
[0092]
And according to the chip-shaped electronic component obtained by the manufacturing method of the present invention and its mounting structure, the stacking and the like can be mounted through the terminals on the insulating material layer made of resin. For this reason, the linear expansion coefficient can be made similar, and a highly reliable stacked package (stacked chip-shaped electronic components) can be provided.
[0093]
In addition, the above-described high reliability can be maintained by three-dimensionally stacking the chip-shaped electronic components of the present invention, which is a high-functional module, having the plurality or types of semiconductor chips including the passive components. High performance can be achieved.
[Brief description of the drawings]
FIG. 1 is a schematic cross-sectional view showing a manufacturing method according to the present invention in the order of steps in an embodiment of the present invention.
FIG. 2 is a schematic cross-sectional view showing the manufacturing method according to the present invention in the order of steps.
FIG. 3 is a schematic cross-sectional view showing the manufacturing method according to the present invention in the order of steps.
FIG. 4 is a schematic sectional view showing the manufacturing method according to the present invention in the order of steps.
FIG. 5 is a schematic sectional view showing the manufacturing method according to the present invention in the order of steps.
FIG. 6 is a schematic view of a chip-shaped electronic component according to the present invention.
FIG. 7 is a schematic view showing a mounting structure of a chip-shaped electronic component according to the present invention.
FIG. 8 is a schematic plan view when the through hole is formed in the manufacturing method according to the present invention.
FIG. 9 is a schematic plan view when the through hole is filled with the conductive resin and a rewiring is formed in the manufacturing method according to the present invention.
FIG. 10 is a schematic plan view when the through hole is filled with the conductive resin and a rewiring is formed in another manufacturing method according to the present invention.
FIG. 11 is a schematic plan view of the semiconductor chip.
FIG. 12 is a schematic cross-sectional view of a chip-shaped electronic component manufacturing method according to a conventional example.
FIG. 13 is a schematic cross-sectional view of the method for manufacturing the chip-shaped electronic component.
FIG. 14 is a schematic cross-sectional view of a laminated structure of chip-like electronic components.
FIG. 15 is a schematic cross-sectional view of a chip-shaped electronic component according to another conventional example.
FIG. 16 is a schematic cross-sectional view of a laminated structure of chip-like electronic components.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ... Base | substrate, 2a, 2b ... Adhesive material layer, 3 ... Double-sided tape base material, 4 ... Semiconductor chip,
5 ... Insulating material, 6 ... Pseudo wafer, 7 ... Back side, 8 ... Protective film,
9 ... Silicon (Si) substrate, 10 ... Al pad electrode,
11 ... Passivation film, 12 ... Dicing line (area),
13, 26 ... through hole, 14a ... conductive resin, 14 ... conductive resin layer,
15 ... Squeegee, 16 ... Electroless Cu plating, 17 ... Surface, 18 ... Rewiring,
19a, 19b ... rewiring electrode part, 20 ... dicing blade,
21 ... Dicing, 22 ... Chip-shaped electronic component, 23 ... Concave part,
24 ... solder bump, 25 ... interposer substrate

Claims (9)

基体上に複数個又は複数種の半導体チップをその電極面を下にして固定する工程と；絶縁物質を前記複数個又は複数種の半導体チップ間を含む全面に被着する工程と；前記半導体チップを固定した疑似ウエーハを前記基体から剥離する工程と；前記絶縁物質からなる前記疑似ウエーハのダイシングエリアに、前記疑似ウエーハの厚さ方向に貫通した貫通孔を設ける工程と；前記貫通孔に導電性樹脂を充填する工程と；前記疑似ウエーハの一方の面側及びそれとは反対側の他方の面側において前記導電性樹脂に接続された配線をそれぞれ形成する工程と；前記複数個又は複数種の半導体チップ間を前記ダイシングエリアに沿って切断して、前記導電性樹脂を厚さ方向に保持したチップ状電子部品に個片化する工程と；を有する、チップ状電子部品の製造方法。A step of fixing a plurality or types of semiconductor chips on a substrate with their electrode surfaces facing down; a step of depositing an insulating material over the entire surface including the plurality of types of semiconductor chips; and the semiconductor chips Peeling the pseudo wafer with the substrate fixed from the substrate; providing a through hole penetrating in the thickness direction of the pseudo wafer in the dicing area of the pseudo wafer made of the insulating material; and making the through hole conductive Filling a resin; forming a wiring connected to the conductive resin on one side of the pseudo wafer and the other side opposite to the pseudo wafer; and the plurality or types of semiconductors Cutting between the chips along the dicing area and separating the chips into chip-shaped electronic components that hold the conductive resin in the thickness direction. The method of production. 前記疑似ウエーハの前記ダイシングエリアに、機械加工又は光照射によって前記貫通孔を形成する、請求項１に記載したチップ状電子部品の製造方法。The manufacturing method of the chip-shaped electronic component according to claim 1, wherein the through hole is formed in the dicing area of the pseudo wafer by machining or light irradiation. 前記疑似ウエーハの前記ダイシングエリアに、前記複数個又は複数種の半導体チップのそれぞれに対応した前記貫通孔を複数列設ける、請求項１に記載したチップ状電子部品の製造方法。2. The method for manufacturing a chip-shaped electronic component according to claim 1, wherein a plurality of the through holes corresponding to each of the plurality or types of semiconductor chips are provided in the dicing area of the pseudo wafer. 前記疑似ウエーハの前記ダイシングエリアに、前記複数個又は複数種の半導体チップに共用される前記貫通孔を一列に設ける、請求項１に記載したチップ状電子部品の製造方法。2. The method of manufacturing a chip-shaped electronic component according to claim 1, wherein the through holes shared by the plurality or types of semiconductor chips are provided in a row in the dicing area of the pseudo wafer. 前記疑似ウエーハの表面及び裏面側において、前記貫通孔に充填された前記導電性樹脂に前記配線との接続電極をそれぞれ形成する、請求項１に記載したチップ状電子部品の製造方法。2. The method for manufacturing a chip-shaped electronic component according to claim 1, wherein connection electrodes to the wiring are respectively formed on the conductive resin filled in the through holes on the front surface and the back surface side of the pseudo wafer. 一方の面側及びこれとは反対側の他方の面側にそれぞれ配線及びその端子が形成され、少なくとも側面に絶縁物質層が被着されており、かつ、前記一方の面側及び他方の面側の各配線間を電気的に接続するための導電性樹脂層が前記絶縁物質層上又は内に形成されている、チップ状電子部品。Wiring and its terminals are respectively formed on one surface side and the other surface side opposite to this, and an insulating material layer is deposited on at least the side surface, and the one surface side and the other surface side A chip-shaped electronic component in which a conductive resin layer for electrically connecting the wirings is formed on or in the insulating material layer. 前記導電性樹脂層がダイシングエリアに存在する、請求項６に記載したチップ状電子部品。The chip-shaped electronic component according to claim 6, wherein the conductive resin layer is present in a dicing area. 前記絶縁物質層に前記基体の厚さ方向に貫通した凹状部又は貫通孔が形成され、これらに前記導電性樹脂が充填されている、請求項６に記載したチップ状電子部品。The chip-shaped electronic component according to claim 6, wherein a concave portion or a through-hole penetrating in the thickness direction of the base is formed in the insulating material layer, and the conductive resin is filled in the concave portion or the through-hole. 請求項６〜８のいずれか１項に記載したチップ状電子部品の複数個が、集積回路チップとして、前記一方の面側及び他方の面側の前記端子を介して積層されている、チップ状電子部品の実装構造。A plurality of chip-like electronic components according to any one of claims 6 to 8, wherein the chip-like electronic components are stacked as integrated circuit chips via the terminals on the one surface side and the other surface side. Electronic component mounting structure.
JP2003171443A 2003-06-17 2003-06-17 Chip-like electronic part, its manufacturing method, and its mounting structure Pending JP2005011856A (en)

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7713788B2 (en) 2007-08-24 2010-05-11 Samsung Electronics Co., Ltd. Method of manufacturing semiconductor package using redistribution substrate
JP2010534951A (en) * 2007-07-27 2010-11-11 テッセラ，インコーポレイテッド Reconfigured wafer stack packaging with pad extension after application
JP2010536171A (en) * 2007-08-03 2010-11-25 テセラ・テクノロジーズ・ハンガリー・ケイエフティー Stacked package using recycled wafer

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010534951A (en) * 2007-07-27 2010-11-11 テッセラ，インコーポレイテッド Reconfigured wafer stack packaging with pad extension after application
JP2010536171A (en) * 2007-08-03 2010-11-25 テセラ・テクノロジーズ・ハンガリー・ケイエフティー Stacked package using recycled wafer
US7713788B2 (en) 2007-08-24 2010-05-11 Samsung Electronics Co., Ltd. Method of manufacturing semiconductor package using redistribution substrate

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