JP3918681B2 - Semiconductor device - Google Patents

Semiconductor device Download PDF

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Publication number
JP3918681B2
JP3918681B2 JP2002232289A JP2002232289A JP3918681B2 JP 3918681 B2 JP3918681 B2 JP 3918681B2 JP 2002232289 A JP2002232289 A JP 2002232289A JP 2002232289 A JP2002232289 A JP 2002232289A JP 3918681 B2 JP3918681 B2 JP 3918681B2
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Prior art keywords
insulating film
provided
semiconductor
semiconductor device
rewiring
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Expired - Fee Related
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JP2002232289A
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JP2004071998A (en
Inventor
裕康 定別当
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カシオ計算機株式会社
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Priority to JP2002232289A priority Critical patent/JP3918681B2/en
Priority claimed from EP03784529A external-priority patent/EP1527480A2/en
Publication of JP2004071998A publication Critical patent/JP2004071998A/en
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    • H01L24/93Batch processes
    • H01L24/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
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Description

[0001]
BACKGROUND OF THE INVENTION
  This inventionSemiconductor deviceAbout.
[0002]
[Prior art]
For example, in a semiconductor device called a BGA (ball grid array), a semiconductor chip made of LSI or the like is mounted on the center of the upper surface of a relay substrate (interposer) slightly larger than the size of the semiconductor chip, and is mounted on the lower surface of the relay substrate. There is one in which connection terminals by solder balls are arranged in a matrix. Here, the relay substrate is sufficiently large in size and pitch by rewiring in order to obtain connection strength and reliability when bonding the external connection electrode formed on the semiconductor chip to another circuit substrate. Used for.
[0003]
FIG. 30 is a sectional view showing an example of such a conventional semiconductor device. The semiconductor chip 1 has a structure in which a plurality of bump electrodes 3 made of copper or the like are provided on the periphery of a silicon substrate 2.
[0004]
The relay substrate 4 includes a base film 5 whose size is slightly larger than the size of the silicon substrate 2 of the semiconductor chip 1. A rewiring 6 connected to the bump electrode 3 of the semiconductor chip 1 is provided on the upper surface of the base film 5.
[0005]
The rewiring 6 includes a first connection pad 7 provided corresponding to the bump electrode 3 of the semiconductor chip 1, a second connection pad 8 provided in a matrix, and the first and second connection pads 7. , 8 and a lead-out line 9 connecting them. A circular hole 10 is provided in the base film 5 in a portion corresponding to the central portion of the second connection pad 8.
[0006]
The semiconductor chip 1 is mounted on the center of the upper surface of the relay substrate 4 via an anisotropic conductive adhesive 11. The anisotropic conductive adhesive 11 is made of a thermosetting resin 12 containing a large number of conductive particles 13.
[0007]
When the semiconductor chip 1 is mounted on the relay substrate 4, first, the semiconductor chip 1 is simply placed on the center of the upper surface of the relay substrate 4 with the sheet-like anisotropic conductive adhesive 11 being positioned. To do.
[0008]
Next, bonding is performed by applying a predetermined pressure at a temperature at which the thermosetting resin 12 is cured. Then, the bump electrode 3 pushes away the thermosetting resin 12 and is conductively connected to the upper surface of the first connection pad 7 via the conductive particles 13, and the lower surface of the semiconductor chip 1 is thermoset to the upper surface of the relay substrate 4. It adheres via the adhesive resin 12.
[0009]
Next, a resin sealing film 14 made of an epoxy resin is formed on the entire top surface of the relay substrate 4 including the semiconductor chip 1. Next, solder balls 15 are formed in the circular hole 10 and below the circular holes 10 by being connected to the second connection pads 8. In this case, since the second connection pads 8 are arranged in a matrix, the solder balls 15 are also arranged in a matrix.
[0010]
Here, the size of the solder balls 15 is larger than the size of the bump electrodes 3 of the semiconductor chip 1, and it is necessary to make the arrangement interval larger than the arrangement interval of the bump electrodes 3 in order to avoid contact between the solder balls 15. . Therefore, when the number of bump electrodes 3 of the semiconductor chip 1 is increased, it is necessary to make the arrangement area larger than the size of the semiconductor chip 1 in order to obtain a necessary arrangement interval for each solder ball 15, and for this reason, The size of the substrate 4 is slightly larger than the size of the semiconductor chip 1. Therefore, among the solder balls 15 arranged in a matrix, the peripheral solder balls 15 are arranged around the semiconductor chip 1.
[0011]
[Problems to be solved by the invention]
By the way, in the conventional semiconductor device, the relay substrate 4 on which the rewiring 6 is formed is used, and the lower surface of the bump electrode 3 of the semiconductor chip 1 is bonded to the first of the rewiring 6 of the relay substrate 4 by bonding after alignment. The number of bump electrodes 3 of the semiconductor chip 1 is increased, and the size and arrangement of the bump electrodes 3 are increased because of the conductive connection to the upper surface of the connection pads 7 via the conductive particles 13 of the anisotropic conductive adhesive 11. When the interval is small, there is a problem that alignment is extremely difficult. In this case, if the size of the semiconductor chip 1 is increased, it is natural that the size and the arrangement interval of the bump electrodes 3 can be increased. However, by doing so, the number of semiconductor chips taken from the wafer state is drastically reduced. It becomes extremely expensive. In addition, the semiconductor chips 1 must be bonded and mounted on the relay substrate 4 one by one, resulting in a problem that the manufacturing process is complicated. The same applies to a multi-chip module type semiconductor device having a plurality of semiconductor chips.
[0012]
  Therefore, the present invention can increase the arrangement interval of the external connection electrodes without using bonding.Semiconductor deviceThe purpose is to provide.
[0013]
[Means for Solving the Problems]
  The invention according to claim 1 is a semiconductor structure having a plurality of rewirings provided on an upper surface of a semiconductor substrate and a columnar electrode formed on one end of each rewiring, and the columnar shape of the semiconductor structure. An insulating film provided on an entire upper surface excluding the electrode and an extending portion outside the peripheral side surface of the semiconductor structure; and at least one layer provided on the insulating film and connected to the columnar electrode and having a connection pad An upper layer rewiring, and among the upper layer rewiring, at least a part of the uppermost layer upper layer rewiring has the connection pad on the extension portion outside the peripheral side surface of the semiconductor structure on the insulating film. Among the upper layer rewiring, the lower layer upper layer rewiring is directly connected to the columnar electrode through the opening formed in the insulating film, and the opening formed in the insulating film. Is 1/2 or more of the width of the columnar electrode It is characterized in that it has a width.
  According to a second aspect of the present invention, each includes a semiconductor substrate, a plurality of rewirings provided on the upper surface of the semiconductor substrate, and columnar electrodes formed on one end of each of the rewirings. A plurality of semiconductor structures disposed in a row, an insulating film provided on an entire upper surface excluding the columnar electrode of each semiconductor structure, and an extended portion outside the peripheral side surface of each semiconductor structure, and the insulating film And at least one upper layer rewiring provided to be connected to the columnar electrode and having a connection pad. Among the upper layer rewiring, at least a part of the uppermost layer upper layer rewiring includes the connection pad The upper layer redistribution of the lower layer among the upper layer redistribution is an opening formed in the insulating film. Directly connected to the columnar electrode via Is, wherein the opening formed in the insulating film is characterized in that it has less than half of the width of the width of the columnar electrode.
  According to a third aspect of the present invention, in the first or second aspect of the invention, the insulating film is provided so as to cover a peripheral side surface of the semiconductor structure.
  According to a fourth aspect of the present invention, in the third aspect of the present invention, the lower surface of the insulating film provided to cover the peripheral side surface of the semiconductor structure is on the same plane as the lower surface of the semiconductor structure. It is characterized by being arranged.
  The invention according to claim 5 is the invention according to claim 1 or 2, wherein the upper layer rewiring in the lowermost layer is on each of the columnar electrodes and in the upper layer rewiring.Lowest layerAnd a plating layer formed on the insulating film.
  The invention according to claim 6 is the invention according to claim 1 or 2,At least one intermediate insulating film and the intermediate insulating film are formed between the uppermost layer upper layer rewiring and the lowermost layer upper layer rewiring, and the uppermost layer upper layer rewiring and the lowermost layer upper layer rewiring are formed. wiringAn inter-layer rewiring is provided to connect the two.
  The invention according to claim 7 is the invention according to claim 1 or 2, wherein the columnar electrode has a height of 50 μm or more.
  According to an eighth aspect of the present invention, in the first or second aspect of the present invention, an uppermost layer is formed on a portion excluding at least a part of the connection pad of the upper layer rewiring on an upper surface of the insulating film including the upper layer rewiring. An insulating film is provided.
  The invention according to claim 9 is the invention according to claim 8, wherein projecting connection terminals are provided on the connection pads of the upper layer rewiring.
  The invention according to claim 10 is the invention according to claim 8, wherein an electronic component is provided on the uppermost insulating film so as to be connected to a connection pad portion of any one of the upper layer rewirings. It is what.
  According to an eleventh aspect of the present invention, in the invention according to any one of the eighth to tenth aspects, a heat dissipation layer is provided on a lower surface of the semiconductor structure and the insulating film provided on a peripheral side surface thereof. It is a feature.
  The invention described in claim 12 is the invention described in claim 1 or 2, wherein the insulating film is provided so as to cover a peripheral side surface of the semiconductor structure, and the insulation provided on the peripheral side surface of the semiconductor structure. The film is provided on the base plate.
  The invention according to claim 13 is the invention according to claim 1 or 2, wherein the insulating film is provided so as to cover a peripheral side surface of the semiconductor structure, and the insulation provided on the peripheral side surface of the semiconductor structure. A flexible wiring board is disposed on the membrane, and connection terminals formed on the flexible wiring board are connected to the connection pads of any one of the upper layer rewirings.
  According to a fourteenth aspect of the present invention, in the first or second aspect of the present invention, a flexible wiring board is disposed on the semiconductor structure, and the connection terminal formed on the flexible wiring board is one of the upper layer re-connections. It is connected to the connection pad of the wiring.
  According to a fifteenth aspect of the invention, in the invention of the fourteenth aspect, a protruding connection terminal is conductively connected to the flexible wiring board.
  The invention according to claim 16 is the invention according to claim 1 or 2, wherein the insulating film is provided so as to cover a peripheral side surface of the semiconductor structure, and the insulating film is formed on the peripheral side surface of the semiconductor structure. The outermost peripheral insulating film is provided so as to cover the film.
  The invention according to claim 17 is the invention according to claim 16, wherein the outermost peripheral insulating film is formed thicker than the insulating film formed on the peripheral side surface of the semiconductor structure. Is.
  The invention according to claim 18 is the invention according to claim 16, wherein the outermost peripheral insulating film is formed thinner than the insulating film formed on the peripheral side surface of the semiconductor structure. Is.
  The invention according to claim 19 is the invention according to claim 8, wherein an electronic component is provided on the uppermost insulating film so as to be connected to a connection pad of any one of the upper layer rewirings. A connection terminal formed on a flexible wiring board is connected to the external terminal of the upper layer rewiring.
  A twentieth aspect of the invention is the invention according to the first or second aspect, wherein the semiconductor structure includes a plurality of the semiconductor structures having the insulating film and the upper layer rewiring provided on an upper surface, and the upper surface of each semiconductor structure. The upper layer rewiring is connected by a flexible wiring board.
  A twenty-first aspect of the invention is characterized in that, in the twentieth aspect of the invention, the semiconductor structures are laminated with their lower surfaces facing each other.
[0014]
DETAILED DESCRIPTION OF THE INVENTION
(First embodiment)
FIG. 1 is a sectional view of a semiconductor device as a first embodiment of the present invention. The semiconductor device includes a planar square base plate 21 made of silicon, glass, ceramics, resin, metal, or the like. An adhesive layer 22 made of an adhesive, a pressure sensitive adhesive sheet, a double-sided adhesive tape, or the like is provided on the upper surface of the base plate 21.
[0015]
At the center of the upper surface of the adhesive layer 22, the lower surface of the planar square semiconductor structure 23 having a size slightly smaller than the size of the base plate 21 is bonded. In this case, the semiconductor structure 23 is called a CSP (chip size package) and includes a silicon substrate (semiconductor substrate) 24 bonded to the center of the upper surface of the adhesive layer 22. A plurality of connection pads 25 made of aluminum or the like are provided on the periphery of the upper surface of the silicon substrate 24, and an insulating film 26 made of silicon oxide or the like is provided on the upper surface of the silicon substrate 24 except for the central portion of the connection pads 25. .
[0016]
The connection pad 25 and the insulating film 26 provided on the silicon substrate 24 are usually obtained when a semiconductor substrate in a wafer state is diced into individual chips. However, in the present invention, in the state where the connection pad 25 and the insulating film 26 are formed on the semiconductor substrate in the wafer state, the dicing is not performed, and the semiconductor structure 23 having rewiring can be obtained as described below. The semiconductor substrate in a wafer state is diced. First, the configuration of the semiconductor structure 23 will be described.
[0017]
A protective film 27 made of polyimide or the like is provided on the insulating film 26 formed on the silicon substrate 24. A central portion of the connection pad 25 is exposed through an opening 28 formed in the insulating film 26 and the protective film 27. A base metal layer 31 a made of copper is provided from the upper surface of the connection pad 25 exposed through the opening 28 to a predetermined location on the upper surface of the protective film 27. An upper metal layer 31b made of copper is provided on the upper surface of the base metal layer 31a, and the rewiring 32 is constituted by the base metal layer 31a and the upper metal layer 31b.
[0018]
A columnar electrode 33 made of copper is provided on the upper surface of the pad portion of the rewiring 32. A sealing film (insulating film) 34 made of an epoxy resin is provided on the upper surface of the protective film 27 including the rewiring 32 so that the upper surface is flush with the upper surface of the columnar electrode 33. As described above, the semiconductor structure 23 includes the silicon substrate 24, the connection pad 25, and the insulating film 26, and further includes the protective film 27, the rewiring 32, the columnar electrode 33, and the sealing film 34.
[0019]
A sealing film (insulating film) 35 made of an epoxy resin is provided on the upper surface of the adhesive layer 22 around the semiconductor structure 23 so that the upper surface is flush with the upper surface of the sealing film 34. A first upper insulating film 36 made of photosensitive polyimide or the like is provided on the upper surfaces of both the sealing films 34 and 35 and the columnar electrode 33. An opening 37 is provided in a portion of the first upper insulating film 36 corresponding to the center of the upper surface of the columnar electrode 33. Provided on the first base metal layer 38a and the first base metal layer 38a from the upper surface of the columnar electrode 33 exposed through the opening 37 to a predetermined position on the upper surface of the first upper insulating film 36. A first upper layer rewiring 39 made of the first upper metal layer 38b is provided.
[0020]
A second upper layer insulating film 41 made of photosensitive polyimide or the like is provided on the entire upper surface of the first upper layer insulating film 36 including the first upper layer rewiring 39. An opening 42 is provided in a portion corresponding to the connection pad portion of the first upper layer rewiring 39 of the second upper layer insulating film 41. From the upper surface of the connection pad portion of the first upper-layer rewiring 39 exposed through the opening 42 to a predetermined position on the upper surface of the second upper-layer insulating film 41, the second base metal layer 43a and the second A second upper layer rewiring 44 made of a second upper metal layer 43b provided on the base metal layer 43a is provided.
[0021]
A third upper layer insulating film 45 made of photosensitive polyimide or the like is provided on the entire upper surface of the second upper layer insulating film 41 including the second upper layer rewiring 44. An opening 46 is provided in a portion corresponding to the connection pad portion of the second upper layer rewiring 44 of the third upper layer insulating film 45. Solder balls (protruding connection terminals) 47 are provided in and above the opening 46 so as to be connected to the connection pad portion of the second upper layer rewiring 44. The plurality of solder balls 47 are arranged in a matrix on the third upper insulating film 45.
[0022]
By the way, the size of the base plate 21 is made slightly larger than the size of the semiconductor structure 23 because the solder ball 47 is arranged in the semiconductor structure in accordance with the increase in the number of connection pads 25 on the silicon substrate 24. This is because the size and arrangement interval of the connection pads 25 are made larger than the size and arrangement interval of the columnar electrodes 33.
[0023]
For this reason, the connection pad portion of the second upper layer rewiring 44 arranged in a matrix (portion in the opening 46 of the third upper layer insulating film 45) is not only the region corresponding to the semiconductor structure 23, It is also disposed on the region of the insulating film 35 provided on the peripheral side surface of the semiconductor structure 23. That is, among the solder balls 47 arranged in a matrix, at least the outermost solder balls 47 are arranged around the semiconductor structure 23.
[0024]
In this case, as a modification, all the connection pad portions of the second upper layer rewiring 44 may be arranged around the semiconductor structure 23. Further, it is possible to arrange the upper layer rewiring as one layer, that is, only the first rewiring 39, and arrange at least the outermost connection pad portion around the semiconductor structure 23.
[0025]
As described above, the present invention has a semiconductor structure in which not only the connection pad 25 and the insulating film 26 are formed on the silicon substrate 24 but also the protective film 27, the rewiring 32, the columnar electrode 33, the sealing film 34, and the like are formed. A first upper-layer insulating film 36 covering the upper surface, a first upper-layer rewiring 39 connected to the columnar electrode 33 via an opening 37 formed on the first upper-layer insulating film 36, and The configuration is characterized by providing a sealing film 35 covering the peripheral side surface.
[0026]
Usually, in order to relieve the stress acting on the columnar electrode due to the difference in thermal expansion coefficient between the silicon substrate and the circuit substrate, the height of the columnar electrode needs to be 100 to 200 μm. A first upper-layer rewiring 39 and the first upper-layer insulating film 36 are formed on the columnar electrode 33, and the first upper-layer rewiring 39 and the first upper-layer insulating film 36 act to relieve stress. Therefore, the height of the columnar electrode 33 can be as low as about 50 to 100 μm. Of course, as the height of the columnar electrode 33 is increased, the stress relaxation action is increased. Therefore, depending on the circuit board to be bonded, the height may be the same as the conventional one.
[0027]
Next, an example of a method for manufacturing this semiconductor device will be described. First, as shown in FIG. 2, a base plate 21 in which an adhesive layer 22 is provided on the entire upper surface of the base plate 21 from which a plurality of base plates 21 shown in FIG. 1 can be collected is prepared. Then, the lower surface of the silicon substrate 24 of the semiconductor structure 23 is bonded to a plurality of predetermined locations on the upper surface of the adhesive layer 22.
[0028]
As described above, the semiconductor structure 23 is called a CSP and is manufactured in advance. Here, an example of a method for manufacturing the semiconductor structure 23 will be briefly described. First, a semiconductor substrate in which a connection pad 25, an insulating film 26, and a protective film 27 are provided on a semiconductor substrate in a wafer state (silicon substrate 24 before cutting) is prepared. Next, a base metal layer 31 a is formed on the entire upper surface of the protective film 27 including the upper surface of the connection pad 25 exposed through the opening 28.
[0029]
Next, the upper metal layer 31b is formed by electrolytic plating at a predetermined location on the upper surface of the base metal layer 31a. Next, the columnar electrode 33 is formed on the upper surface of the connection pad portion of the rewiring 32 by electrolytic plating. Next, unnecessary portions of the base metal layer 31a are removed by etching using the columnar electrode 33 and the upper metal layer 31b as a mask to leave the base metal layer 31a only under the upper metal layer 31b, and the remaining base metal layer 31a. And the rewiring 32 which consists of the upper metal layer 31b formed in the whole surface on this base metal layer 31a is formed.
[0030]
Next, the sealing film 34 is formed on the entire upper surface of the protective film 27 including the columnar electrode 33 and the rewiring 32 so that the thickness thereof is larger than the height of the columnar electrode 33. Therefore, in this state, the upper surface of the columnar electrode 33 is covered with the sealing film 34. Next, the sealing film 34 and the upper surface side of the columnar electrode 33 are appropriately polished to expose the upper surface of the columnar electrode 33. Next, a plurality of semiconductor structures 23 shown in FIG. 2 are obtained through a dancing process.
[0031]
Now, as shown in FIG. 2, once the lower surface of the silicon substrate 24 of the semiconductor structure 23 is bonded to a plurality of predetermined locations on the upper surface of the adhesive layer 22, respectively, next, as shown in FIG. A sealing film 35 made of polyimide, epoxy resin, or the like is formed on the upper surface of the adhesive layer 22 including 23 by printing so that its thickness is slightly larger than the height of the semiconductor structure 23. Therefore, in this state, the upper surface of the semiconductor structure 23 is covered with the sealing film 35. Next, the upper surface side of the sealing film 35 and the semiconductor structure 23 is appropriately polished to expose the upper surface of the columnar electrode 33 as shown in FIG.
[0032]
2 is manufactured, as described above, the sealing film 34 is formed on the upper surface of the protective film 27 including the columnar electrode 33 and the rewiring 32 so that the thickness thereof is higher than that of the columnar electrode 33. The upper surface of the columnar electrode 33 is exposed by appropriately polishing the upper surface side of the sealing film 34 and the columnar electrode 33. Therefore, the polishing process is performed twice.
[0033]
Then, next, the case where a grinding | polishing process can be made once is demonstrated. In the state shown in FIG. 2, a semiconductor structure 23 that does not include the sealing film 34 is prepared. That is, after forming the protective film 27, the rewiring 32, and the columnar electrode 33 on the semiconductor substrate in the wafer state on which the connection pad 25 and the insulating film 26 are formed, the dicing is performed without forming the sealing film 34. .
[0034]
Then, in the step shown in FIG. 3, the sealing films 34 and 35 are simultaneously formed with the same sealing material in the regions where the sealing films 34 and 35 are to be formed. The film is integrated and has no boundary), and the upper surface side of the columnar electrode 33 may be polished. That is, the polishing process can be performed once by setting the sealing film forming process once.
[0035]
However, when the polishing process is performed once, the height of the columnar electrode 33 of the semiconductor structure 23 in the state shown in FIG. 2 varies due to formation by electrolytic plating, whereas the polishing process is performed twice. In this case, the height of the semiconductor structure 23 in the state shown in FIG. 2 becomes uniform, and the height of the semiconductor structure 23 in the state shown in FIG.
[0036]
When the polishing step shown in FIG. 4 is completed, a first upper insulating film 36 is formed on the upper surfaces of the sealing films 34 and 35 and the columnar electrode 33 that are flush with each other, as shown in FIG. To do. The first upper insulating film 36 is made of photosensitive polyimide, photosensitive polybenzoxazole, photosensitive epoxy resin, photosensitive novolac resin, photosensitive acrylic or calzo resin, and is formed into a dry film. Therefore, when this dry film is laminated by a laminator, the first upper insulating film 36 is formed. The same applies to the second and third upper-layer insulating films 41 and 45 described later, but they may be formed by a coating method such as printing.
[0037]
Next, an opening 37 is formed by photolithography at a portion corresponding to the center of the upper surface of the columnar electrode 33 of the first upper insulating film 36. Next, as shown in FIG. 6, a first base metal layer 38 a is formed on the entire upper surface of the first upper insulating film 36 including the upper surface of the columnar electrode 33 exposed through the opening 37. In this case, the first base metal layer 38a is composed of only a copper layer formed by electroless plating, but may be only a copper layer formed by sputtering, titanium formed by sputtering, or the like. A copper layer may be formed on the thin film layer by sputtering. The same applies to the case of the second base metal layer 43a described later.
[0038]
Next, a plating resist film 51 is patterned on the upper surface of the first base metal layer 38a. In this case, an opening 52 is formed in the plating resist film 51 in a portion corresponding to the first upper layer rewiring 39 formation region. Next, the first upper metal layer is formed on the upper surface of the first base metal layer 38a in the opening 52 of the plating resist film 51 by performing copper electroplating using the first base metal layer 38a as a plating current path. A first upper layer rewiring 39 is formed. In FIGS. 1 and 6, only the first base metal layer 38a is formed in the opening 37 of the first upper insulating film 36. However, this is for the convenience of illustration, and in practice, A first upper metal layer 38b is also formed.
[0039]
Here, since the first upper layer rewiring 39 is directly bonded onto the columnar electrode 33 by plating, the opening 37 of the first upper layer insulating film 36 is a 10 μm × 10 μm square or a circular with the same area. It is sufficient in strength if it has an area of. This type of exposure machine has alignment accuracy of several μm, and the diameter of the columnar electrode 33 is normally about 100 to 150 μm (the pitch is usually twice this). Compared with bonding by rewiring, the method can be applied even when the size and arrangement interval of the columnar electrodes are much smaller, and the process is more efficient.
[0040]
As described above, according to the method of the present invention, the width of the opening of the insulating film for joining the upper layer rewiring to the columnar electrode can be reduced to ½ or less of the width of the columnar electrode. Thus, the size and arrangement interval of the columnar electrodes of the semiconductor structure can be made small, so that the size of the semiconductor device of the present invention having the upper layer rewiring can be made smaller.
[0041]
Next, the plating resist film 51 is peeled off, and then unnecessary portions of the first base metal layer 38a are removed by etching using the first upper metal layer 38b as a mask, as shown in FIG. The first upper layer rewiring 39 composed of the base metal layer 38a and the first upper metal layer 38b is formed.
[0042]
Next, as shown in FIG. 8, a second upper layer insulating film 41 made of photosensitive polyimide or the like is patterned on the entire upper surface of the first upper layer insulating film 36 including the first upper layer rewiring 39. In this case, an opening 42 is formed in a portion of the second upper insulating film 41 corresponding to the connection pad portion of the first upper layer rewiring 39. Next, a second base metal layer 43a is formed on the entire upper surface of the second upper insulating film 41 including the connection pad portion of the first upper redistribution 39 exposed through the opening 42 by electroless plating. .
[0043]
Next, a plating resist film 53 is formed on the upper surface of the second base metal layer 43a. In this case, an opening 54 is formed in the plating resist film 53 in a portion corresponding to the second upper layer rewiring 44 formation region. Next, by performing copper electroplating using the second base metal layer 43a as a plating current path, a second upper metal layer is formed on the upper surface of the second base metal layer 43a in the opening 54 of the plating resist film 53. 43b is formed.
[0044]
Next, the plating resist film 53 is peeled off, and then unnecessary portions of the second base metal layer 43 are removed by etching using the second upper layer rewiring 44 as a mask, as shown in FIG. A second upper layer rewiring 44 composed of the base metal layer 43 and the second upper metal layer 43b is formed.
[0045]
Next, as shown in FIG. 10, a third upper layer insulating film 45 made of photosensitive polyimide or the like is patterned on the entire upper surface of the second upper layer insulating film 41 including the second upper layer rewiring 44. In this case, an opening 46 is formed in a portion corresponding to the connection pad portion of the second upper layer rewiring 44 of the third upper layer insulating film 45. Next, a solder ball 47 is formed in the opening 46 and above it by connecting it to the connection pad portion of the second upper layer rewiring 44.
[0046]
Next, as shown in FIG. 11, when the three insulating films 45, 41, and 36, the sealing film 35, the adhesive layer 22 and the base plate 21 are cut between the adjacent semiconductor structures 23, FIG. A plurality of the semiconductor devices shown are obtained.
[0047]
In the semiconductor device thus obtained, the first base metal layer 38 and the first upper layer rewiring 39 connected to the columnar electrode 33 of the semiconductor structure 23 are formed by electroless plating (or sputtering) and electrolytic plating. The second base metal layer 43 and the second upper layer rewiring 44 that are formed and connected to the connection pad portion of the first upper layer rewiring 39 are formed by electroless plating (or sputtering) and electrolytic plating. Conductive connection between the columnar electrode 33 of the semiconductor structure 23 and the first upper layer rewiring 39 and between the first upper layer rewiring 39 and the second upper layer rewiring 44 without bonding. Can do.
[0048]
Further, in the above manufacturing method, the semiconductor structure 23 is bonded and arranged at a plurality of predetermined positions on the adhesive layer 22 on the base plate 21, and the first to third upper layers are arranged with respect to the plurality of semiconductor structures 23. The insulating films 36, 41, 45, the first and second base metal layers 38, 43, the first and second upper layer rewirings 39, 44 and the solder balls 47 are collectively formed and then divided. Since a plurality of semiconductor devices are obtained, the manufacturing process can be simplified.
[0049]
Moreover, since the several semiconductor structure 23 can be conveyed with the base plate 21, a manufacturing process can also be simplified by this. Furthermore, if the outer dimensions of the base plate 21 are made constant, the transport system can be shared regardless of the outer dimensions of the semiconductor device to be manufactured.
[0050]
Further, in the above manufacturing method, as shown in FIG. 2, since the CSP type semiconductor structure 23 including the rewiring 32 and the columnar electrode 33 is bonded onto the adhesive layer 22, for example, on the silicon substrate 24. A normal semiconductor chip provided with the connection pad 25, the insulating film 26 and the protective film 27 is bonded onto the adhesive layer 22, and rewiring and columnar electrodes are formed on the sealing film provided around the semiconductor chip. Compared with the case, the cost can be reduced.
[0051]
For example, when the base plate 21 before cutting has a substantially circular shape of a certain size like a silicon wafer, rewiring and columnar shapes are formed on the sealing film provided around the semiconductor chip bonded on the adhesive layer 22. When the electrode is formed, the processing area increases. In other words, since low-density processing is performed, the number of processed sheets per process is reduced and throughput is lowered, resulting in an increase in cost.
[0052]
On the other hand, in the above manufacturing method, since the CSP type semiconductor structure 23 provided with the rewiring 32 and the columnar electrode 33 is bonded on the adhesive layer 22 and built up, the number of processes increases. Since the high-density processing is performed until the columnar electrode 33 is formed, the efficiency is high, and the overall price can be reduced even if the increase in the number of processes is taken into consideration.
[0053]
Next, another example of the method for manufacturing the semiconductor device shown in FIG. 1 will be described. First, as shown in FIG. 12, an adhesive layer 56 made of an ultraviolet curable adhesive sheet or the like is bonded to the entire upper surface of another base plate 55 made of an ultraviolet transparent transparent resin plate or glass plate. Prepared by adhering the base plate 21 and the adhesive layer 22 to the upper surface.
[0054]
2 to 10, the insulating films 45, 41, 36, the sealing film 35, the adhesive layer 22, the base plate 21, and the adhesive layer 56 are formed as shown in FIG. 13. And the other base plate 55 is not cut. Next, the adhesive layer 56 is cured by irradiating ultraviolet rays from the lower surface side of another base plate 55. Then, the adhesiveness by the adhesive layer 56 with respect to the lower surface of the divided base plate 21 is lowered. Therefore, when the separated pieces existing on the adhesive layer 56 are peeled one by one and picked up, a plurality of semiconductor devices shown in FIG. 1 are obtained.
[0055]
In this manufacturing method, the individual semiconductor devices present on the adhesive layer 56 do not fall apart in the state shown in FIG. 13, so that a circuit (not shown) is used as it is without using a dedicated semiconductor device mounting tray. When mounting on a substrate, it can be removed and picked up one by one. Further, when the adhesive layer 56 with reduced adhesion remaining on the upper surface of another base plate 55 is peeled off, the other base plate 55 can be reused. Furthermore, if the outer dimensions of the other base plate 55 are made constant, the transport system can be shared regardless of the outer dimensions of the semiconductor device to be manufactured.
[0056]
In addition, it is also possible to use a normal dicing tape or the like in which the semiconductor device is removed by being expanded as another base plate 55. In this case, the adhesive layer may not be an ultraviolet curable type. Further, another base plate 55 may be removed by polishing or etching.
[0057]
Next, still another example of the method for manufacturing the semiconductor device shown in FIG. 1 will be described. In this manufacturing method, after the step shown in FIG. 5, as shown in FIG. 14, the entire upper surface of the first upper insulating film 36 including the upper surface of the columnar electrode 33 exposed through the opening 37 is electrolessly coated with copper. A first base metal layer 38a is formed by plating. Next, the first upper metal layer 38c is formed on the entire upper surface of the first base metal layer 38a by performing copper electroplating using the first base metal layer 38a as a plating current path. Next, a resist film 57 is patterned on a portion corresponding to the first upper layer rewiring formation region on the upper surface of the first upper metal forming layer 38c.
[0058]
Next, when unnecessary portions of the first upper metal forming layer 38c and the first base metal layer 38a are removed by etching using the resist film 57 as a mask, as shown in FIG. 15, only under the resist film 57. The first upper wiring layer 39 remains. Thereafter, the resist film 57 is peeled off. The second upper layer rewiring 44 may be formed by the same formation method.
[0059]
By the way, the base plate 21 shown in FIG. 2 or another base plate 55 shown in FIG. 12 can be formed in a tray shape. That is, the base plate is shaped like a saucer in which the region where the semiconductor structures 23 are arranged is recessed from the surroundings. Then, a metal layer for a plating current path is provided on the upper surface surrounding the array region of the semiconductor structure 23 of the tray-shaped base plate, and the metal layer for the plating current path and the base metal layer (38, 43 for the plating current path). ) May be connected by a conductive member to perform electrolytic plating. In this case, by setting the same outer size of the tray, the same manufacturing apparatus can be used even when the size of the semiconductor device to be manufactured is different, which is efficient.
[0060]
(Second Embodiment)
In the manufacturing process shown in FIG. 3, when the adhesive layer 22 is provided on the lower surface of the silicon substrate 24 of the semiconductor structure 23 and this adhesive layer 22 is adhered to each predetermined location on the upper surface of the base plate 21, FIG. The semiconductor device as the second embodiment of the present invention shown is obtained.
[0061]
In the semiconductor device thus obtained, the lower surface of the silicon substrate 24 is bonded to the upper surface of the base plate 21 via the adhesive layer 22, and the side surface of the silicon substrate 24 is interposed via the sealing film 36. Since it is connected to the upper surface of the base plate 21, the bonding strength of the semiconductor structure 23 to the base plate 21 can be increased to some extent.
[0062]
(Third and fourth embodiments)
FIG. 17 shows a sectional view of a semiconductor device as a third embodiment of the present invention. This semiconductor device is different from the semiconductor device shown in FIG. 1 in that the base plate 21 and the adhesive layer 22 are not provided.
[0063]
When manufacturing the semiconductor device according to the third embodiment, for example, as shown in FIG. 10, after forming the solder balls 47, the base plate 21 is peeled off from the adhesive layer 22, or the base plate 21 and the adhesive layer 22 are removed. After removing by polishing, etching, or the like and then removing the three insulating films 45, 41, and 36 and the sealing film 35 between the adjacent semiconductor structures 23, the semiconductor device shown in FIG. Several are obtained. Since the semiconductor device thus obtained does not include the base plate 21 and the adhesive layer 22, it can be reduced in thickness accordingly.
[0064]
Further, after removing the base plate 21 and the adhesive layer 22 by polishing, etching, or the like, the lower surface side of the silicon substrate 24 and the sealing film 35 is appropriately polished, and then between the adjacent semiconductor structures 23, three layers are formed. When the insulating films 45, 41, and 36 and the sealing film 35 are cut, a plurality of semiconductor devices as the fourth embodiment of the present invention shown in FIG. 18 are obtained. The semiconductor device thus obtained can be further reduced in thickness.
[0065]
Before forming the solder balls 47, the base plate 21 and the adhesive layer 22 are removed by polishing, etching, or the like (further, the lower surfaces of the silicon substrate 24 and the sealing film 35 are appropriately polished) Next, solder balls 47 may be formed, and then the three insulating films 45, 41, 36 and the sealing film 35 may be cut between the adjacent semiconductor structures 23.
[0066]
(Fifth embodiment)
FIG. 19 is a sectional view of a semiconductor device as a fifth embodiment of the present invention. This semiconductor device differs from the semiconductor device shown in FIG. 1 in that a metal layer 61 for heat dissipation is bonded to the lower surface of the adhesive layer 22. The metal layer 61 is made of a copper foil having a thickness of several tens of μm.
[0067]
In the case of manufacturing the semiconductor device of the fifth embodiment, for example, as shown in FIG. 10, after forming the solder balls 47, the base plate 21 is removed by polishing or etching, and then the entire lower surface of the adhesive layer 22 is formed. When the metal layer 61 is bonded to each other, and then the three insulating films 45, 41, and 36, the sealing film 35, the adhesive layer 22 and the metal layer 61 are cut between the adjacent semiconductor structures 23, FIG. A plurality of semiconductor devices are obtained.
[0068]
The adhesive layer 22 is also removed by polishing, etching, or the like (further, the lower surfaces of the silicon substrate 24 and the sealing film 35 are appropriately polished as necessary), and a new surface is added to the lower surfaces of the silicon substrate 24 and the sealing film 35. The metal layer 61 may be bonded through an adhesive layer.
[0069]
(Sixth embodiment)
In the case shown in FIG. 11, the semiconductor structures 23 adjacent to each other are cut. However, the present invention is not limited to this, and two or more semiconductor structures 23 are cut as one set. As in the sixth embodiment of the invention, the three semiconductor structures 23 may be cut as one set to obtain a multichip module type semiconductor device. In this case, the set of three semiconductor structures 23 may be the same type or different types.
[0070]
In FIG. 20, the base metal layer under the rewirings 32, 39, and 44 is omitted for convenience of illustration. Further, it is unclear whether or not the connection pad portion (solder ball 47) of the second upper layer rewiring 44 is disposed on the sealing film 35 around the semiconductor structure 23, but this is for the convenience of illustration. In fact, it is disposed on the sealing film 35. This also applies to the embodiments described later.
[0071]
However, in FIG. 20, for example, since the semiconductor structure 23 is bonded to the upper surface of the adhesive layer 22, unlike the conventional bonding, high accuracy is not required for alignment when bonding, and therefore the semiconductor It is possible to make the arrangement interval of the structural bodies 23 as small as possible. Therefore, when the arrangement interval of the semiconductor structures 23 is made as small as possible, at least a part of the second upper layer rewiring 44 may be arranged on the sealing film 35.
[0072]
(Seventh embodiment)
In the case shown in FIG. 20, only the solder ball 47 is provided on the connection pad portion of the second upper layer rewiring 44. However, the present invention is not limited to this. For example, the seventh embodiment of the present invention shown in FIG. As described above, the connection pad 62 is formed on the connection pad portion of the second upper layer rewiring 44, and the solder ball 47, the semiconductor chip 63 made of LSI, etc., and the chip component 64 made of capacitor, resistance, etc. are provided thereon. It may be.
[0073]
In this case, the semiconductor chip 63 and the chip component 64 are arranged at the center of the upper surface of the third upper insulating film 45, and the solder balls 47 are arranged at the periphery of the upper surface of the third upper insulating film 45. The semiconductor chip 63 has a structure in which a plurality of bump electrodes 63b are provided around the lower surface of the chip body 63a. The bump electrode 63b of the semiconductor chip 63 is conductively connected to the connection pad 62 via solder (not shown). Further, a sealing material 65 is filled between the chip body 63a and the third upper insulating film 45. The electrodes on both sides of the chip component 64 are connected to the connection pads 62 by solder 66.
[0074]
(Eighth embodiment)
In FIG. 21, a chip component 64 and the like are mounted on the center portion of a set of three semiconductor structures 23 and solder balls 47 are formed on the peripheral portion. As in the eighth embodiment of the present invention shown in FIG. 22, the size of the sealing film 35 around one semiconductor structure 23 is increased to some extent, and is disposed on the center of the third upper insulating film 45. A chip component 64 or the like may be mounted on the connection pad 62, and the lower portion of the connection pin 67 may be connected to the connection pad 62 disposed on the peripheral portion via solder (not shown). The connection pins 67 are soldered to the connection pads 62. Although not shown, the connection pins 67 are inserted into through holes formed in the circuit board and soldered to pad portions formed around the through holes on the back surface side. It is what is done.
[0075]
(Ninth embodiment)
FIG. 23 is a sectional view showing a semiconductor device according to the ninth embodiment of the present invention. Next, the structure of this semiconductor device will be described together with its manufacturing method. First, a description will be given with reference to FIG. 20. In FIG. 20, a solder ball 47 is not formed and the base plate 21 is removed. Hereinafter, the prepared one is referred to as a semiconductor block 71.
[0076]
Next, the central portion of the upper surface of the metal plate 72 for heat dissipation that is somewhat larger than the semiconductor block 71 is bonded to the lower surface of the adhesive layer 22 of the semiconductor block 71. Next, the sealing film 73 is formed on the upper surface of the metal plate 72 around the semiconductor block 71 so that the upper surface thereof is flush with the upper surface of the third upper insulating film 45 of the semiconductor block 71 by a molding method or a printing method. To do. Alternatively, the adhesive layer 22 may be removed, the metal plate 72 may be disposed in the mold for molding, and the semiconductor block 71 may be disposed at the center of the upper surface thereof.
[0077]
Next, a third upper layer rewiring (including a third base metal layer) 74 is connected to the connection pad portion of the second upper layer rewiring 44 on the upper surfaces of the third upper layer insulating film 45 and the sealing film 73. Form. Next, a fourth upper layer insulating film 75 is formed on the upper surface of the third upper layer insulating film 45 including the third upper layer rewiring 74. Next, an opening 76 is formed in a portion corresponding to the connection pad portion of the third upper layer rewiring 74 of the fourth upper layer insulating film 75. Next, a connection pad 77 is formed on the fourth upper layer insulating film 75 in and around the opening 76 so as to be connected to the connection pad portion of the third upper layer rewiring 74.
[0078]
Next, electrodes on both sides of the chip component 78 made of a capacitor, a resistor, and the like are connected to the upper surface of the connection pad 77 on the semiconductor block 71 via solder 79. Further, the lower portion of the connection pin 80 is connected to the upper surface of the connection pad 77 on the sealing film 73 via solder (not shown). Thus, the semiconductor device shown in FIG. 23 is obtained.
[0079]
(10th Embodiment)
FIG. 24 is a sectional view showing a semiconductor device according to the tenth embodiment of the present invention. Next, the structure of this semiconductor device will be described together with its manufacturing method. First, in this case as well, referring to FIG. 20, in FIG. 20, a solder ball 47 is not formed but the base plate 21 and the adhesive layer 22 are removed. Hereinafter, the prepared one is referred to as a semiconductor block 81. However, the arrangement of the second upper layer rewiring (including the second base metal layer) 44 is different between FIGS. 20 and 24 for the sake of illustration. In FIG. 24, connection pads 82 are formed at predetermined positions on the upper surface of the third upper layer insulating film 45 so as to be connected to the connection pad portions of the second upper layer rewiring 44.
[0080]
Next, a flexible wiring board 83 is prepared. The flexible wiring board 83 includes a film substrate 85 having an opening 84 that is slightly larger than the semiconductor block 81 at the center. A wiring 86 is provided on the upper surface of the film substrate 85. One end of the wiring 86 protrudes into the opening 84 and serves as a connection terminal 86a. A protective film 87 is provided on the upper surface of the film substrate 85 including the wiring 86. An opening 88 is provided in a portion corresponding to the other end of the wiring 86 of the protective film 87. A solder ball 89 is provided on the other end of the wiring 86 exposed through the opening 88, but when the flexible wiring board 83 is prepared, the solder ball 89 is not formed.
[0081]
Then, the connection terminals 86a of the flexible wiring board 83 are connected to the connection pads 82 arranged in the peripheral portion on the semiconductor block 81 via solder (not shown). Next, a sealing film 90 is formed on the lower surface of the flexible wiring board 83 around the semiconductor block 81 so that the lower surface thereof is flush with the lower surface of the semiconductor block 71 such as the silicon substrate 24 by a molding method or a printing method. Next, a heat radiating metal plate 92 is bonded to the lower surface of the semiconductor block 71 such as the silicon substrate 24 and the lower surface of the sealing film 90 via the adhesive layer 91.
[0082]
Next, the electrodes on both sides of the chip component 93 made of a capacitor, a resistor, or the like are connected to the upper surface of the connection pad 82 disposed at the central portion on the semiconductor block 81 via the solder 94. A solder ball 89 is formed on the other end of the wiring 86 exposed through the opening 88 of the flexible wiring board 83. Thus, the semiconductor device shown in FIG. 24 is obtained.
[0083]
(Eleventh embodiment)
In the case shown in FIG. 24, the thickness of the sealing film 90 in the peripheral portion is larger than the thickness of the sealing film 90 in the vicinity of the peripheral surface of the semiconductor block 81 as in the tenth embodiment of the present invention shown in FIG. Also, it may be made thinner. In this case, the sealing film 90 is formed by a molding method.
[0084]
(Twelfth embodiment)
FIG. 26 is a sectional view of a semiconductor device as a twelfth embodiment of the present invention. Next, the structure of this semiconductor device will be described together with its manufacturing method. First, in this case as well, referring to FIG. 20, a substrate is prepared by removing the base plate 21 and the adhesive layer 22 in FIG. Hereinafter, the prepared block is referred to as a semiconductor block 101. In this case, the solder ball 47 is formed, but a solder ball (47A) having a slightly smaller diameter than that shown in FIG. 20 is formed.
[0085]
Next, the flexible wiring board 102 is prepared. The flexible wiring board 102 includes a film substrate 103 that is somewhat larger than the semiconductor block 81. A wiring 104 is provided on the upper surface of the film substrate 103. A through hole 104 is provided in a portion corresponding to one end of the wiring 104 of the film substrate 103. A protective film 106 is provided on the upper surface of the film substrate 103 including the wiring 104. An opening 107 is provided in a portion of the protective film 106 corresponding to the other end of the wiring 104. A solder ball 108 is provided on the other end portion of the wiring 106 exposed through the opening 107, but when the flexible wiring board 102 is prepared, the solder ball 108 is not formed.
[0086]
Then, the solder ball (47A) of the semiconductor block 101 is inserted into the through hole 105 of the flexible wiring board 102, and the solder 47A is connected to the lower surface of one end of the wiring 104 in the through hole 105 by reflow processing. Next, a sealing film 109 is formed on the lower surface of the flexible wiring board 102 around the semiconductor block 101 so that the lower surface thereof is flush with the lower surface of the semiconductor block 101 such as the silicon substrate 24 by a molding method or a printing method.
[0087]
Next, a heat radiating metal plate 111 is bonded to the lower surface of the semiconductor block 101 such as the silicon substrate 24 and the lower surface of the sealing film 109 via the adhesive layer 110. Next, a solder ball 108 is formed on the other end of the wiring 104 exposed through the opening 107 of the flexible wiring board 8102. Thus, the semiconductor device shown in FIG. 26 is obtained.
[0088]
(13th Embodiment)
FIG. 27 shows a sectional view of a semiconductor device as a thirteenth embodiment of the present invention. This semiconductor device is greatly different from the semiconductor device shown in FIG. 20 in that it does not include any solder balls 47 but includes a flexible wiring board 121 instead.
[0089]
In this case, the flexible wiring board 121 is provided with a wiring 123 on one surface of the film substrate 122 and is protected on one surface of the film substrate 122 including a portion excluding the connection terminals 123a (the other is not shown) composed of both ends of the wiring 123. The structure is provided with a film 124. On the other hand, a plurality of connection terminals 125 are formed on one end portion of the upper surface of the third upper-layer insulating film 45 so as to be connected to connection pad portions of a predetermined second upper-layer rewiring 44. Then, one connection terminal 123a of the flexible wiring board 121 is connected to the connection terminal 125 via an anisotropic conductive adhesive or solder (not shown).
[0090]
In addition, a connection pad 126 is formed on the connection pad portion of the remaining second upper layer rewiring 44, and a chip component 127 made of a capacitor, a resistor, etc., and a CSP type semiconductor structure 128 are mounted thereon. Yes. In this case, the semiconductor structure 128 has substantially the same structure as the semiconductor structure 23. The lower surface of the columnar electrode 129 of the semiconductor structure 128 is connected to the upper surface of the connection pad 126 via solder (not shown).
[0091]
(14th Embodiment)
FIG. 28 is a sectional view of a semiconductor device as a fourteenth embodiment of the present invention. In this semiconductor device, for example, the semiconductor block 131 formed by removing the base plate 21 in the one shown in FIG. 20 and the base plate 21 and the adhesive layer 22 in the one shown in FIG. 21 are removed and the solder balls 47 are not formed. The semiconductor block 132 made of a material is bonded via the adhesive layer 22. In this case, only a plurality of semiconductor chips 63 are mounted on the upper semiconductor block 132.
[0092]
Moreover, both the semiconductor blocks 131 are connected to each other via, for example, the flexible wiring board 121 that is substantially the same as that shown in FIG. That is, a plurality of connection terminals 125 are formed at one end portion of the upper surface of the third upper insulating film 45 of the upper semiconductor block 132 so as to be connected to the connection pad portion of the predetermined second upper layer rewiring 44A. Then, one connection terminal 123a of the flexible wiring board 121 is connected to the connection terminal 125 via an anisotropic conductive adhesive or solder (not shown).
[0093]
In addition, a connection terminal including a predetermined second upper layer rewiring 44B is provided at one end of the lower surface of the third upper layer insulating film 45 of the lower semiconductor block 131. The other connection terminal 123b of the flexible wiring board 121 is connected to a connection terminal made of a predetermined second upper layer rewiring 44B via an anisotropic conductive adhesive (or solder) 133.
[0094]
(Fifteenth embodiment)
FIG. 29 is a sectional view showing a semiconductor device according to the fifteenth embodiment of the present invention. In this semiconductor device, the main difference from the case shown in FIG. 28 is that the flexible wiring board 121 is lengthened and adhered to the lower surface of the third upper insulating film 45 of the lower semiconductor block 131 via the adhesive layer 151. It is.
[0095]
In this case, the solder ball 47 protrudes outside the film substrate 122 through the adhesive layer 151, the protective film 124, and the opening 152 formed in the film substrate 122. Further, the other connection terminal 123b of the flexible wiring board 121 is an opening formed in the adhesive layer 151 and the protective film 124 in a connection terminal made of a predetermined second upper layer rewiring 44B at both ends of the other semiconductor block 131. They are connected via solder 154 disposed in the portion 153.
[0096]
【The invention's effect】
  As explained above, according to the present invention,A plurality of rewirings provided on the upper surface of the semiconductor substrate and at least one semiconductor structure having a columnar electrode formed on one end of each of the rewirings; and the entire upper surface of the semiconductor structure excluding the columnar electrode; An insulating film provided on an extending portion outside the peripheral side surface of the semiconductor structure; and at least one upper layer rewiring provided on the insulating film and connected to the columnar electrode and having a connection pad. In the upper layer rewiring, at least a part of the uppermost layer upper layer rewiring is such that the connection pad is disposed on the extended portion outside the peripheral side surface of the semiconductor structure on the insulating film. ,There is no conventional bonding process, so it is possible to increase the interval between the external connection electrodes without bonding.it can. Further, among the upper layer rewiring, the lower layer upper layer rewiring is electrically connected directly to the columnar electrode through the opening formed in the insulating film, and the opening formed in the insulating film has the columnar shape. The size of the semiconductor device according to the present invention having the upper layer rewiring because the width and the arrangement interval of the columnar electrodes of the semiconductor structure can be reduced. Can be made even smaller.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view of a semiconductor device as a first embodiment of the invention.
2 is a cross-sectional view of an initial manufacturing process in the example of the method for manufacturing the semiconductor device shown in FIG. 1;
FIG. 3 is a cross-sectional view of the manufacturing process following FIG. 2;
FIG. 4 is a cross-sectional view of the manufacturing process following FIG. 3;
FIG. 5 is a cross-sectional view of the manufacturing process following FIG. 4;
6 is a cross-sectional view of the manufacturing process following FIG. 5. FIG.
7 is a cross-sectional view of a manufacturing step that follows FIG. 6. FIG.
FIG. 8 is a cross-sectional view of the manufacturing process following FIG. 7;
FIG. 9 is a cross-sectional view of the manufacturing process following FIG. 8;
10 is a cross-sectional view of a manufacturing step that follows FIG. 9; FIG.
FIG. 11 is a cross-sectional view of the manufacturing process following FIG. 10;
12 is a cross-sectional view of a semiconductor device shown in FIG. 1 that is initially prepared in another example of the method for manufacturing the semiconductor device.
FIG. 13 is a cross-sectional view of a predetermined manufacturing process in the other example.
14 is a cross-sectional view of a predetermined manufacturing process in still another example of the method for manufacturing the semiconductor device shown in FIG.
FIG. 15 is a cross-sectional view of the manufacturing process following FIG. 14;
FIG. 16 is a sectional view of a semiconductor device as a second embodiment of the invention.
FIG. 17 is a cross-sectional view of a semiconductor device as a third embodiment of the present invention.
FIG. 18 is a cross-sectional view of a semiconductor device as a fourth embodiment of the invention.
FIG. 19 is a cross-sectional view of a semiconductor device as a fifth embodiment of the invention.
FIG. 20 is a sectional view of a semiconductor device as a sixth embodiment of the invention.
FIG. 21 is a sectional view of a semiconductor device as a seventh embodiment of the invention.
FIG. 22 is a sectional view of a semiconductor device as an eighth embodiment of the invention.
FIG. 23 is a cross-sectional view of a semiconductor device as a ninth embodiment of the invention.
FIG. 24 is a cross-sectional view of a semiconductor device as a tenth embodiment of the invention.
FIG. 25 is a sectional view of a semiconductor device as an eleventh embodiment of the present invention;
FIG. 26 is a sectional view of a semiconductor device as a twelfth embodiment of the present invention.
FIG. 27 is a sectional view of a semiconductor device as a thirteenth embodiment of the invention.
FIG. 28 is a cross-sectional view of a semiconductor device as a fourteenth embodiment of the present invention.
FIG. 29 is a sectional view of a semiconductor device as a fifteenth embodiment of the present invention.
FIG. 30 is a cross-sectional view of an example of a conventional semiconductor device.
[Explanation of symbols]
21 Base plate
22 Adhesive layer
23 Semiconductor structure
24 Silicon substrate
25 connection pads
31 Underlying metal layer
32 Rewiring
33 Columnar electrode
34 Sealing film
35 Sealing film
36 First upper-layer insulating film
38 First underlayer metal layer
39 First upper layer rewiring
41 Second upper-layer insulating film
43 Second ground metal layer
44 Second upper layer rewiring
45 Third upper layer insulating film
47 Solder balls

Claims (21)

  1. A semiconductor structure having a plurality of rewirings provided on an upper surface of a semiconductor substrate and a columnar electrode formed on one end of each of the rewirings, an entire upper surface of the semiconductor structure excluding the columnar electrode, and the semiconductor structure An insulating film provided on an extending portion outside the peripheral side surface of the body, and at least one upper layer rewiring provided on the insulating film and connected to the columnar electrode and having a connection pad, Among the rewirings, at least a part of the uppermost layer upper layer rewiring is such that the connection pad is disposed on the extension portion outside the peripheral side surface of the semiconductor structure on the insulating film, and the upper layer rewiring Among them, the uppermost layer redistribution layer is electrically connected directly to the columnar electrode through an opening formed in the insulating film, and the opening formed in the insulating film is 1 / of the width of the columnar electrode. characterized in that it has two less wide Semiconductor device.
  2. A plurality of semiconductor configurations each having a semiconductor substrate, a plurality of rewirings provided on the upper surface of the semiconductor substrate, and a columnar electrode formed on one end of each rewiring, and arranged separately from each other Body, an insulating film provided on the entire upper surface excluding the columnar electrode of each semiconductor structure and an extending portion outside the peripheral side surface of each semiconductor structure, and the columnar electrode is connected to the insulating film on the insulating film. At least one upper layer redistribution having a connection pad, and among the upper layer redistribution, at least a part of the uppermost layer redistribution includes any one of the connection pad on the insulating film. The upper layer rewiring is disposed on the extension portion outside the peripheral side surface of the semiconductor structure , and the lower layer upper layer rewiring is directly connected to the columnar electrode through the opening formed in the insulating film. Connected to the insulating film. It said openings semiconductor device characterized by having a half or less of the width of the width of the columnar electrode.
  3.   3. The semiconductor device according to claim 1, wherein the insulating film is provided so as to cover a peripheral side surface of the semiconductor structure.
  4.   The invention according to claim 3 is characterized in that the lower surface of the insulating film provided to cover the peripheral side surface of the semiconductor structure is disposed on substantially the same plane as the lower surface of the semiconductor structure. Semiconductor device.
  5. 3. The invention according to claim 1, wherein, in the upper layer rewiring, the uppermost layer rewiring includes a plating layer formed on each of the columnar electrodes and the lowermost insulating film. Semiconductor device.
  6. 3. The invention according to claim 1, wherein the uppermost layer is formed on at least one intermediate insulating film and the intermediate insulating film between the uppermost layer upper layer rewiring and the lowermost layer upper layer rewiring, and An interlayer rewiring that connects the upper layer rewiring and the uppermost layer rewiring of the lowermost layer is provided.
  7.   3. The semiconductor device according to claim 1, wherein the columnar electrode has a height of 50 [mu] m or more.
  8.   3. The invention according to claim 1, wherein an uppermost layer insulating film is provided on a top surface of the insulating film including the upper layer rewiring except for at least a part of the connection pad of the upper layer rewiring. A featured semiconductor device.
  9. 9. The semiconductor device according to claim 8 , wherein a projecting connection terminal is provided on the connection pad of the upper layer rewiring.
  10. 9. The semiconductor device according to claim 8 , wherein an electronic component is provided on the uppermost insulating film so as to be connected to a connection pad portion of any one of the upper layer rewirings.
  11. In the invention of any one of claims 8-10, wherein a heat dissipation layer on a lower surface of the semiconductor structure and the insulating film provided on the peripheral side surface is provided.
  12.   The invention according to claim 1 or 2, wherein the insulating film is provided so as to cover a peripheral side surface of the semiconductor structure, and the insulating film provided on the peripheral side surface of the semiconductor structure is provided on a base plate. A semiconductor device characterized by comprising:
  13.   The invention according to claim 1 or 2, wherein the insulating film is provided so as to cover a peripheral side surface of the semiconductor structure, and a flexible wiring board is disposed on the insulating film provided on the peripheral side surface of the semiconductor structure. A semiconductor device, wherein a connection terminal formed on the flexible wiring board is connected to the connection pad of any one of the upper layer rewirings.
  14.   The invention according to claim 1 or 2, wherein a flexible wiring board is arranged on the semiconductor structure, and a connection terminal formed on the flexible wiring board is connected to the connection pad of any one of the upper layer rewirings. A semiconductor device characterized by comprising:
  15. 15. The semiconductor device according to claim 14 , wherein a protruding connection terminal is provided on the flexible wiring board in a conductive connection.
  16.   The invention according to claim 1 or 2, wherein the insulating film is provided to cover a peripheral side surface of the semiconductor structure, and an outermost peripheral insulating film covers the insulating film formed on the peripheral side surface of the semiconductor structure. A semiconductor device provided.
  17. 17. The semiconductor device according to claim 16 , wherein the outermost peripheral insulating film is formed thicker than the insulating film formed on a peripheral side surface of the semiconductor structure.
  18. 17. The semiconductor device according to claim 16 , wherein the outermost peripheral insulating film is formed thinner than the insulating film formed on the peripheral side surface of the semiconductor structure.
  19. 9. The electronic device according to claim 8 , wherein an electronic component is provided on the uppermost insulating film so as to be connected to a connection pad of any one of the upper layer rewirings and is flexibly connected to an external terminal of any other upper layer rewiring. A semiconductor device, wherein a connection terminal formed on a wiring board is connected.
  20.   3. The invention according to claim 1, wherein a plurality of the semiconductor structures having the insulating film and the upper layer rewiring provided on an upper surface are provided, and the upper layer rewiring on the upper surface of each semiconductor structure is formed by a flexible wiring board. A semiconductor device which is connected.
  21. 21. The semiconductor device according to claim 20 , wherein the semiconductor structures are stacked with their lower surfaces facing each other.
JP2002232289A 2002-08-09 2002-08-09 Semiconductor device Expired - Fee Related JP3918681B2 (en)

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JP2002232289A JP3918681B2 (en) 2002-08-09 2002-08-09 Semiconductor device
EP03784529A EP1527480A2 (en) 2002-08-09 2003-08-05 Semiconductor device and method of manufacturing the same
KR1020047005322A KR100593049B1 (en) 2002-08-09 2003-08-05 Semiconductor device and method of manufacturing the same
CA2464078A CA2464078C (en) 2002-08-09 2003-08-05 Semiconductor device and method of manufacturing the same
PCT/JP2003/009958 WO2004015771A2 (en) 2002-08-09 2003-08-05 Semiconductor device and method of manufacturing the same
AU2003253425A AU2003253425C1 (en) 2002-08-09 2003-08-05 Semiconductor device and method of manufacturing the same
CN038012693A CN1568546B (en) 2002-08-09 2003-08-05 Semiconductor device and method of manufacturing the same
TW092121811A TWI231551B (en) 2002-08-09 2003-08-08 Semiconductor device and method of manufacturing the same
US10/826,039 US7294922B2 (en) 2002-08-09 2004-04-16 Semiconductor device and method of manufacturing the same
HK05105873.6A HK1073389A1 (en) 2002-08-09 2005-07-11 Semiconductor device and method of manufacturing the same
US11/671,268 US7618886B2 (en) 2002-08-09 2007-02-05 Semiconductor device and method of manufacturing the same
US11/671,318 US7547967B2 (en) 2002-08-09 2007-02-05 Semiconductor device and method of manufacturing the same
US12/415,782 US7737543B2 (en) 2002-08-09 2009-03-31 Semiconductor device and method of manufacturing the same

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