JP3664432B2 - Semiconductor device and manufacturing method thereof - Google Patents

Semiconductor device and manufacturing method thereof Download PDF

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JP3664432B2
JP3664432B2 JP2000146012A JP2000146012A JP3664432B2 JP 3664432 B2 JP3664432 B2 JP 3664432B2 JP 2000146012 A JP2000146012 A JP 2000146012A JP 2000146012 A JP2000146012 A JP 2000146012A JP 3664432 B2 JP3664432 B2 JP 3664432B2
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protective film
side protective
silicon substrate
semiconductor device
manufacturing
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JP2001326299A (en
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猛 若林
治 桑原
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Casio Computer Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L21/6836—Wafer tapes, e.g. grinding or dicing support tapes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68327—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]

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Description

【０００１】
【発明の属する技術分野】
本発明は、ＣＳＰ（Chip Size Package）構造の半導体装置およびその製造方法に関する。
【０００２】
【従来の技術】
近年、チップとパッケージのサイズがほぼ等しくなるＣＳＰ構造の半導体装置が知られている。図１３〜図１６はこの種の半導体装置である、ウエハレベルＣＳＰの製造方法の一例を示す断面図である。以下、これら図面を参照してその製造工程について説明する。
【０００３】
半導体装置は、まず図１３に図示するように、ウエハ（シリコン基板）１の表面（回路面）側にアルミ電極等からなる複数の接続パッド（アルミ電極）２を形成した後、図示していないが、各接続パッド２の中央部を露出するように、ウエハ１の表面側全面を覆う酸化シリコンや窒化シリコン等で形成された保護皮膜を形成する。そして、この保護被膜の上に、各接続パッド２の中央部分が開口するよう表面側保護膜３を形成する。
表面側保護膜３は、例えばウエハ１の回路面側全面にポリイミド系樹脂材を塗布硬化させた後に、エッチング液を用いてレジストパターンニングおよび保護膜パターニングを施してからレジスト剥離することで形成される。
【０００４】
次に、表面側保護膜３が形成する開口部４を介して露出される各接続パッド２上に再配線５を形成する。再配線５は、後述する如く、切断されて個片化された各半導体装置の各接続パッド２に接続された柱状電極（後述のポスト６）を中央部にマトリクス上に配列することにより、各半導体装置の周辺部のみに形成された接続パッド２のピッチおよび電極面積を広げ、回路基板とのボンディング強度および接続の信頼性を向上するためのものである。
【０００５】
再配線５を形成した後には、再配線５上の所定箇所に複数のポスト（柱状電極）６を設ける。ポスト６は、例えば１００〜１５０μｍ程度の厚さでポスト形成用のレジストを塗布硬化させ、レジストパターニングを施し、これにより開口された部分に電解メッキを施すことで形成される。
こうして、図１３に図示する構造となったら、図１４に図示するように、ポスト６を覆うように、ウエハ１の回路面側全体をエポキシ等の樹脂材によってモールドし表面側保護膜７を形成する。そして、この表面側保護膜７を硬化させた後、ウエハ１全体を研削加工テーブルに移載し、研削装置にて表面側保護膜７の上面側を研磨してポスト６の端面６ａ（図１５参照）を露出させる。
【０００６】
この後、ウエハ１を所定厚にすべく背面側を研磨加工したり、研磨加工した背面側に製品番号やロット番号をマーキングする処理を施す。次いで、この背面側を下向きにしてウエハ１をダイシングフレームに装着されたダイシングテープ上に載置した後、図１６に図示する通り、カットライン８に沿ってウエハ１をダイシングすることによって、チップに個片化された半導体装置１０が形成されるようになっている。
【０００７】
【発明が解決しようとする課題】
ところで、上述した従来の半導体装置１０では、図１６に図示した通り、シリコン基板（ウエハ１）の側面（切断面を含む）や背面が露出した状態となっており、これがチップ破損や露出面からの水分浸透等、信頼性を低下させる要因になる、という問題がある。
そこで本発明は、このような事情に鑑みてなされたもので、信頼性を向上することができる半導体装置およびその製造方法を提供することを目的としている。
【０００８】
【課題を解決するための手段】
上記目的を達成するため、請求項１に記載の半導体装置では、表面に複数の接続パッドを有するシリコン基板と、前記シリコン基板の背面を覆う裏面側保護膜と、前記シリコン基板の表面、側面および前記裏面側保護膜の側面の少なくとも一部を覆って形成され前記各接続パッドを露出する開口部を有する第１の表面側保護膜と、前記第１の表面側保護膜上に形成され、各々、前記開口部を介して前記各接続パッドに接続された複数の再配線と、各々、前記各再配線の一端上に形成された複数の柱状電極と、前記シリコン基板の前記各柱状電極を除く表面全体を覆い、その表面が前記柱状電極の表面とほぼ同一面となるように形成された第２の表面側保護膜とを具備することを特徴とする。請求項３に記載の半導体装置では、表面に複数の接続パッドを有するシリコン基板と、前記シリコン基板の背面を覆う裏面側保護膜と、前記シリコン基板の表面および側面を覆って形成され前記各接続パッドを露出する開口部を有する第１の表面側保護膜と、前記第１の表面側保護膜上に形成され、各々、前記開口部を介して前記各接続パッドに接続された複数の再配線と、各々、前記各再配線の一端上に形成された複数の柱状電極と、前記シリコン基板の前記各柱状電極を除く表面全体を覆い、その表面が前記柱状電極の表面とほぼ同一面となるように形成された第２の表面側保護膜と、を具備し、前記裏面側保護膜の表面に装置属性のマーキングが設けられていることを特徴とする。
【０００９】
請求項４に記載の半導体装置の製造方法では、表面に複数の接続パッドを有するシリコン基板にその背面を覆う裏面側保護膜を形成する第１の工程と、前記シリコン基板を個片化する箇所に切削溝を設け、その後に前記シリコン基板の表面および側面を覆うと共に、前記切削溝を充填する第１の表面側保護膜を形成する第２の工程と、前記シリコン基板の表面を覆う第１の表面側保護膜に前記各接続パッドを露出する開口部を形成し、前記第１の表面側保護膜上に形成され、各々、前記開口部を介して前記各接続パッドに接続された複数の再配線を形成する第３の工程と、各々、前記各再配線の一端上に複数の柱状電極を形成する第４の工程と、前記シリコン基板の前記各柱状電極を除く表面全体を覆う第２の表面側保護膜を形成する第５の工程と、前記第１の表面側保護膜が切断面に残るように、前記切削溝より狭い幅でシリコン基板を個片に切断する第６の工程とを具備することを特徴とする。
【００１１】
本発明による半導体装置は、背面が裏面側保護膜で、表面および側面が表面側保護膜で覆われる為、信頼性が向上する。
また、本発明による半導体装置の製造方法では、シリコン基板の背面を覆う裏面側保護膜を形成した後、シリコン基板を個片化する箇所に切削溝を設けておき、その後に当該シリコン基板の表面および側面を覆うと共に、切削溝を充填する表面側保護膜を形成してから該表面側保護膜が切断面に残るように、切削溝より狭い幅でシリコン基板を個片に切断するので、個片化された半導体装置は背面、表面および側面が全て保護膜で覆われることになり、この結果、チップ破損や露出面からの水分浸透等、信頼性を低下させる要因を除去でき、信頼性を向上させ得る。
【００１２】
【発明の実施の形態】
以下、図面を参照して本発明の実施の一形態について説明する。図１〜図９は、実施の一形態による半導体装置の構造およびその製造工程を説明する為の断面図である。これらの図において、上述した従来例と共通する部分には同一の番号を付してある。
本発明による製造工程では、先ず図１に図示する通り、表面側に複数の接続パッド２が形成された厚さｔ1のウエハ１について、その背面側を切削研磨して厚さｔ2≒（１／３〜２／３）ｔ1のウエハ１に成形する。
【００１３】
ウエハ１の表面側に形成された複数の接続パッド２は、工程の最終過程において切断され個片化される各半導体チップの周辺部に設けられているものであり、各半導体チップの接続パッド２間に形成された、図示しない集積回路素子に接続されているものである。
なお、ウエハ１の表面側には該ウエハの全面を覆う、酸化シリコンや窒化シリコン等で形成された保護皮膜Ｐが形成されており、この保護皮膜Ｐには上記各接続パッド２の中央部を露出する開口部が形成されている。
【００１４】
次に、図２に図示するように、切削研磨されたウエハ１の背面側に、所定の膜厚となるよう保護樹脂（例えば、ポリイミド、エポキシ等の有機樹脂材）を塗布して裏面側保護膜１１を形成する。裏面側保護膜１１は、ポリイミドまたはエポキシ等の樹脂の単層であってもよいが、これら複数の樹脂層の積層構造としても良い。
次に、裏面側保護膜１１を硬化させ、この後はレーザーによりこの裏面側保護膜１１上にロット番号や製品番号などをマーキングする（図３参照）。そして、マーキング完了後には、図４に示すように、ダイシングフレーム（支持部材）２０に装着されたダイシングテープ２１上に、裏面側保護膜１１が対向するようにウエハ１をマウントする。ウエハ１をダイシングテープ２１上にマウントしたら、予め定められたカットラインＣＬに沿ってウエハ１に切削溝１ａを刻設するダイシング処理を施す。この際、裏面側保護膜１１はハーフカットしても良いし、あるいはフルカットする形態としても構わない。
【００１５】
ダイシング完了後には、図５に図示する通り、ダイシングテープ２１を介してダイシングフレーム２０にマウントされた状態のウエハ１に対し、その側面（周囲面）およびを覆うと共に、表面側に設けられた各接続パッド２の中央部分を開口させながら、上述した切削溝１ａを充填するよう表面を覆う表面側保護膜３を形成する。
この表面側保護膜３は、ウエハ１の表面側に形成された保護皮膜Ｐおよび該保護皮膜Ｐの開口部から露出する各接続パッド２上に、例えばポリイミド系樹脂材を塗布してスピンコートすることにより形成する方法が望ましいが、スピンコートに限らず、スキージを用いる印刷法やノズルからのインク吐出による塗布法等適宜な手法を用いることが可能である。
【００１６】
次に、このようにしてウエハ１の表面に形成された表面側保護膜３を硬化させた後に、側面および上面にフォトレジストを塗布し（図示せず）ウエハ１の表面側については該フォトレジスト（図示せず）パターンニングおよび表面側保護膜３を順次パターニングして、表面側保護膜３に、前述した従来例と同様、各接続パッド２の中央部を露出する開口部４を形成する。この後、フォトレジスト剥離する。
【００１７】
この後、図５中の要部Ａを拡大した図６に図示するように、表面側保護膜３に形成された開口部４を介して露出される接続パッド２上に再配線５を形成する。再配線５はフォトレジスト剥離後の、表面側保護膜３の全面にＵＢＭスパッタ処理等によりＵＢＭ層を堆積し、この後、再配線用のフォトレジスト塗布、硬化し、フォトリソグラフィ技術により、再配線用のフォトレジストを図６に図示される再配線が形成されるよう、所定形状の開口を有するパターニングを施した後、このレジストによって開口された部分に電解メッキを施すことで形成される。
なお、この電解メッキにより再配線５を形成する状態では、表面側保護膜３の全表面上に堆積されたＵＢＭ層は、ダイシングフレーム２０上に蒸着されたＵＢＭ層部分も含めてメッキ電極として残されている。
【００１８】
このようにして、一端が各接続パッド２に接続され、他端が表面側保護膜３上を、切断により個片化される各半導体チップの中央側に延出される各再配線５を形成した後は、各再配線５上の上記他端上に所定箇所にポスト（柱状電極）６を設ける。ポスト６は、図示しないが、例えば１００〜１５０μｍ程度の厚さでポスト形成用のフォトレジストを塗布、硬化させた上、各再配線５の他端の中央部を露出する開口部を形成し、この開口部内に電解メッキを施すことで形成される。この電解メッキを施す際、表面側保護膜３の全表面上およびダイシングフレーム２０上に蒸着されたＵＢＭ層が一方の電極として用いられる。
なお、このメッキ処理後にはポスト形成用のフォトレジストを剥離しておくと共に、不要部分に蒸着されたＵＢＭ層をエッチングにより除去しておく。図６はこの工程が完了した状態の拡大断面図である。
【００１９】
こうして、図６に図示した構造が形成された後は、図７に図示するように、ポスト６を覆うように、ウエハ１の回路面全体をポリイミド、エポキシ等の樹脂材によってモールドして表面側保護膜７を形成する。表面側保護膜７は、ポリイミド、エポキシ等の単層からなるものでもよいが、これら樹脂層の積層構造としてもよい。この場合、上述せる裏面側保護層１１、表面側保護層３および表面側保護膜７は、環境変化に対応する信頼性を確保する上で、主成分が実質的に同一な材料を含む樹脂層で形成することが望ましい。そして、この表面側保護膜７を硬化させ、次に、その上面側を研磨してポスト６の端面６ａ（図８参照）を露出させる。
露出した端面６ａについては、その表面の酸化膜を取り除き、そこにハンダ印刷等のメタライズ処理を施す。この後、図９に示すように、切断面に所定厚の表面側保護膜３が残るように切削溝１ａの部分を再度ダイシングしてウエハ１をチップに個片化して半導体装置１０を形成する。
【００２０】
以上のように、本発明の実施の一形態によれば、ウエハ１の背面を覆うように裏面側保護膜１１を形成してからウエハ１を個片化する箇所に予めダイシングを施して切削溝１ａを刻設しておき、その後にウエハ１の表面および側面を覆うと共に、切削溝１ａを充填する表面側保護膜３を形成し、続いて再配線５、ポスト６および表面側保護膜７を設けた後、切断面に所定厚の表面側保護膜３が残るように切削溝１ａ部分を再度ダイシングして半導体装置１０を形成するので、個片化された半導体装置１０は背面、表面および側面が全て保護膜３，１１で覆われることになり、この結果、チップ破損や露出面からの水分浸透等、信頼性を低下させる要因を除去でき、信頼性が向上する。
【００２１】
また、この発明の実施の形態にあっては、ダイシングフレーム２０上に蒸着されたＵＢＭ層をメッキ電極として残すようにしたので、従来のように、ウエハ１上に別途に電極形成せずとも再配線５やポスト６を形成する電解メッキ処理を行うことが可能になっている。
さらに、この発明の実施の形態では、半導体装置１０の背面、表面および側面の全てを保護膜３，１１で覆う為、チップに個片化された半導体装置１０をトレイに移載する時などのハンドリングが極めて容易になる。
【００２２】
なお、上述した実施の形態では、表面側に接続パッド２が形成されたウエハ１の背面側を切削研磨した後に、その切削研磨されたウエハ１の背面側に裏面側保護膜１１を形成し、この裏面側保護膜１１上にロット番号や製品番号などをレーザーマーキングしてから、ダイシングフレーム２０にウエハ１をマウントする工程としたが（図４参照）、これに替えて、図１０に示すように、切削研磨されたウエハ１の背面側にロット番号や製品番号などをレーザーマーキングした後、ダイシングフレーム２０に装着されたダイシングテープ２１上に所定の膜厚となるよう保護樹脂（例えば、ポリイミド等の有機樹脂材）を塗布し（図１１参照）、塗布された保護樹脂の上にウエハ１の背面側を貼り合わせて裏面側保護膜１１を形成する工程としても良い。
【００２３】
さらに、上述した形態に替えて、表面保護膜３の材料として感光性樹脂を用いるようにすれば、表面保護膜３を形成する為のフォトレジストの塗布、硬化および剥離の各工程を省略することができる。
【００２４】
また、裏面側保護膜１１を形成した後のダイシング工程（図４参照）において、例えば図１２（イ）に示すように、ウエハ１をダイシングして個片化したら、個片化されたチップの内から良品のみを選別して同図（ロ）または同図（ハ）に図示する形態で並べ替え、この後、図５以降に図示した表面保護膜３、再配線５、ポスト６、第２の表面側保護膜７を形成するようにしても良い。
こうした並び替えを行う際にチップ配置間隔を広げる等、任意に設定することが可能となり、図９における切削溝１ａの部分を再度ダイシングしてウエハ１をチップに個片化して半導体装置１０を形成する際に、各半導体装置１０の側面に形成される表面側保護膜３の厚さを充分なものとすることができる。
【００２５】
また、上述した実施形態では、ウエハ１上に再配線５を形成し、この再配線５上にポスト６を形成する半導体装置に関するものとしたため、表面側保護膜を２層の積層構造としたが、本発明は、ウエハ１の表面側に再配線５を形成せずに直接、ポスト６を形成する半導体装置にも適用することが可能であり、その場合には、表面側保護膜を単層化することができる。
【００２６】
【発明の効果】
請求項１に記載の半導体装置によれば、シリコン基板の背面を裏面側保護膜で覆い、シリコン基板の表面、側面および前記裏面側保護膜の側面の少なくとも一部を第１の表面側保護膜で覆い、該第１の表面側保護膜上に開口部を介して各接続パッドに接続された再配線および該再配線の一端上に柱状電極を形成し、前記シリコン基板の前記各柱状電極を除く表面全体を覆い、その表面が前記柱状電極の表面とほぼ同一面となるように第２の表面側保護膜を形成することにより、シリコン基板の全面が保護膜で覆われ、更に、裏面側保護膜の側面の少なくとも一部が第１の表面側保護膜で覆われる為、再配線を有する半導体装置の信頼性を向上することができる。請求項３に記載の半導体装置によれば、シリコン基板の背面を裏面側保護膜で覆い、シリコン基板の表面および側面を第１の表面側保護膜で覆い、該第１の表面側保護膜上に開口部を介して各接続パッドに接続された再配線および該再配線の一端上に柱状電極を形成し、前記シリコン基板の前記各柱状電極を除く表面全体を覆い、その表面が前記柱状電極の表面とほぼ同一面となるように第２の表面側保護膜を形成し、前記裏面側保護膜の表面に装置属性のマーキングを設けることにより、シリコン基板の全面が保護膜で覆われることにより、半導体装置の信頼性を向上することができるとともに、マーキングを見易くすることができる。請求項４に記載の半導体装置の製造方法によれば、シリコン基板の背面を覆う裏面側保護膜を形成した後、シリコン基板を個片化する箇所に切削溝を刻設しておき、その後に前記シリコン基板の表面および側面を覆うと共に、切削溝を充填する第１の表面側保護膜を形成し、前記第１の表面側保護膜上に各接続パッドに接続された再配線および該再配線の一端上に柱状電極を形成し、前記シリコン基板の前記各柱状電極を除く表面全体を覆う第２の表面側保護膜を形成してから前記第１の表面側保護膜が切断面に残るように、切削溝より狭い幅でシリコン基板を個片に切断するので、個片化された半導体装置は背面、表面および側面が全て保護膜で覆われることになり、この結果、チップ破損や露出面からの水分浸透等、信頼性を低下させる要因を除去でき、信頼性を向上させることができる。
【図面の簡単な説明】
【図１】この発明の第１の実施形態を説明するための図であり、半導体装置製造工程の最初の状態を示す断面図である。
【図２】図１に続く半導体装置の製造工程を説明する為の断面図である。
【図３】図２に続く半導体装置の製造工程を説明する為の断面図である。
【図４】図３に続く半導体装置の製造工程を説明する為の断面図である。
【図５】図４に続く半導体装置の製造工程を説明する為の断面図である。
【図６】図５に続く半導体装置の製造工程を説明する為の断面図である。
【図７】図６に続く半導体装置の製造工程を説明する為の断面図である。
【図８】図８に続く半導体装置の製造工程を説明する為の断面図である。
【図９】図９に続く半導体装置の製造工程を説明する為の断面図であり、本発明の個片化された半導体装置の完成状態を示すものである。
【図１０】本発明の半導体装置の第１の実施形態の変形例を説明するための断面図である。
【図１１】本発明の半導体装置の第２の実施形態を説明するための断面図である。
【図１２】本発明の第１及び第２の実施形態の変形例を説明するための平面図である。
【図１３】従来例の半導体装置の製造方法を説明するための断面図である。
【図１４】図１３に続く工程を説明するための断面図である。
【図１５】図１４に続く工程を説明するための断面図である。
【図１６】図１５に続く工程を説明するための断面図である。
【符号の説明】
１ ウエハ（シリコン基板）
１ａ 切削溝
２ 接続パッド
３ 表面側保護膜（第１の表面側保護膜）
４ 開口部
５ 再配線
６ ポスト（柱状電極）
７ 表面側保護膜（第２の表面側保護膜）
１０ 半導体装置
１１ 裏面側保護膜
２０ ダイシングフレーム
２１ ダイシングテープ（支持部材）[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device having a CSP (Chip Size Package) structure and a manufacturing method thereof.
[0002]
[Prior art]
In recent years, semiconductor devices having a CSP structure in which the sizes of a chip and a package are almost equal are known. 13 to 16 are sectional views showing an example of a method for manufacturing a wafer level CSP, which is this type of semiconductor device. Hereinafter, the manufacturing process will be described with reference to these drawings.
[0003]
First, as shown in FIG. 13, the semiconductor device is not shown after a plurality of connection pads (aluminum electrodes) 2 made of aluminum electrodes or the like are formed on the surface (circuit surface) side of the wafer (silicon substrate) 1. However, a protective film made of silicon oxide, silicon nitride, or the like covering the entire surface side of the wafer 1 is formed so as to expose the central portion of each connection pad 2. And the surface side protective film 3 is formed on this protective film so that the center part of each connection pad 2 may open.
The surface-side protective film 3 is formed, for example, by applying and curing a polyimide resin material on the entire circuit surface side of the wafer 1, performing resist patterning and protective film patterning using an etching solution, and then removing the resist. The
[0004]
Next, the rewiring 5 is formed on each connection pad 2 exposed through the opening part 4 which the surface side protective film 3 forms. As will be described later, the rewiring 5 is formed by arranging columnar electrodes (posts 6 to be described later) connected to the connection pads 2 of each semiconductor device that has been cut and separated into individual pieces on a matrix at the center. This is to widen the pitch and electrode area of the connection pads 2 formed only in the peripheral portion of the semiconductor device, and to improve the bonding strength and connection reliability with the circuit board.
[0005]
After the rewiring 5 is formed, a plurality of posts (columnar electrodes) 6 are provided at predetermined locations on the rewiring 5. The post 6 is formed, for example, by applying and curing a resist for forming a post with a thickness of about 100 to 150 μm, performing resist patterning, and performing electroplating on the opened portion.
In this way, when the structure shown in FIG. 13 is obtained, as shown in FIG. 14, the entire circuit surface side of the wafer 1 is molded with a resin material such as epoxy so as to cover the post 6, and the surface side protective film 7 is formed. To do. And after hardening this surface side protective film 7, the whole wafer 1 is transferred to a grinding process table, the upper surface side of the surface side protective film 7 is grind | polished with a grinding device, and the end surface 6a of the post 6 (FIG. 15). Exposure).
[0006]
Thereafter, the back side is polished to make the wafer 1 have a predetermined thickness, or a product number or lot number is marked on the polished back side. Next, after placing the wafer 1 on the dicing tape mounted on the dicing frame with the back side facing downward, the wafer 1 is diced along the cut line 8 as shown in FIG. An individual semiconductor device 10 is formed.
[0007]
[Problems to be solved by the invention]
By the way, in the above-described conventional semiconductor device 10, as shown in FIG. 16, the side surface (including the cut surface) and the back surface of the silicon substrate (wafer 1) are exposed. There is a problem that it becomes a factor of lowering reliability, such as moisture permeation.
Therefore, the present invention has been made in view of such circumstances, and an object thereof is to provide a semiconductor device capable of improving reliability and a method for manufacturing the same.
[0008]
[Means for Solving the Problems]
In order to achieve the above object, in the semiconductor device according to claim 1, a silicon substrate having a plurality of connection pads on the surface, a back surface side protective film covering the back surface of the silicon substrate, a surface , a side surface , and a surface of the silicon substrate A first surface-side protective film formed on at least a part of the side surface of the back-side protective film and having an opening exposing the connection pads; and formed on the first surface-side protective film, Excluding a plurality of rewirings connected to each connection pad through the openings, a plurality of columnar electrodes formed on one end of each rewiring, and the columnar electrodes of the silicon substrate And a second surface-side protective film formed so as to cover the entire surface and be substantially flush with the surface of the columnar electrode. 4. The semiconductor device according to claim 3, wherein the connection is formed by covering a silicon substrate having a plurality of connection pads on the surface, a back-side protective film covering the back surface of the silicon substrate, and covering the surface and side surfaces of the silicon substrate. A first surface-side protective film having an opening exposing the pad, and a plurality of rewirings formed on the first surface-side protective film, each connected to the connection pads via the opening And covering each of the plurality of columnar electrodes formed on one end of each rewiring and the entire surface of the silicon substrate excluding the columnar electrodes, and the surface thereof is substantially flush with the surface of the columnar electrode. A second surface-side protective film formed as described above, and device attribute markings are provided on the surface of the back-side protective film.
[0009]
In the method of manufacturing a semiconductor device according to claim 4, a first step of forming a back surface side protective film covering the back of the silicon substrate Niso having a plurality of connection pads on the surface, singulating the silicon substrate the cutting groove is provided at a position, with subsequent covering the surface and side of the silicon substrate, covering a second step of forming a first surface-side protective layer filling the cut groove, the surface of the silicon substrate A plurality of openings formed on the first surface-side protective film, each of which is connected to each of the connection pads via the opening; A third step of forming the rewiring, a fourth step of forming a plurality of columnar electrodes on one end of each of the rewirings, and a second step of covering the entire surface of the silicon substrate excluding the columnar electrodes. Forming a second surface side protective film And degree, the first surface-side protective film is to remain cutting plane, characterized by comprising a sixth step of cutting the silicon substrate in a width narrower than that of the cutting grooves into pieces.
[0011]
In the semiconductor device according to the present invention, since the back surface is covered with the back surface side protective film and the surface and side surfaces are covered with the surface side protective film, the reliability is improved.
Further, in the method of manufacturing a semiconductor device according to the present invention, after forming the back surface side protective film covering the back surface of the silicon substrate, a cutting groove is provided at a location where the silicon substrate is separated, and then the surface of the silicon substrate is formed. The silicon substrate is cut into individual pieces with a width narrower than the cutting groove so that the surface side protective film remains on the cut surface after the surface side protective film is formed to cover the side surface and fill the cutting groove. The separated semiconductor device is covered with a protective film on the back, surface, and side surfaces. As a result, it is possible to eliminate factors that reduce reliability, such as chip breakage and moisture penetration from the exposed surface, and improve reliability. Can be improved.
[0012]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, an embodiment of the present invention will be described with reference to the drawings. 1 to 9 are cross-sectional views for explaining a structure of a semiconductor device according to an embodiment and a manufacturing process thereof. In these drawings, the same reference numerals are given to portions common to the above-described conventional example.
In the manufacturing process according to the present invention, as shown in FIG. 1, first, a wafer 1 having a thickness t1 having a plurality of connection pads 2 formed on the front side is cut and polished on the back side to obtain a thickness t2≈ (1 / 3 to 2/3) Molded into wafer 1 at t1.
[0013]
The plurality of connection pads 2 formed on the front surface side of the wafer 1 are provided in the periphery of each semiconductor chip that is cut and separated in the final process, and the connection pads 2 of each semiconductor chip. It is connected to an integrated circuit element (not shown) formed therebetween.
A protective film P made of silicon oxide, silicon nitride or the like is formed on the front side of the wafer 1 so as to cover the entire surface of the wafer, and the central portion of each connection pad 2 is formed on the protective film P. An exposed opening is formed.
[0014]
Next, as shown in FIG. 2, a protective resin (for example, an organic resin material such as polyimide or epoxy) is applied to the back side of the cut and polished wafer 1 to protect the back side. A film 11 is formed. The back surface side protective film 11 may be a single layer of resin such as polyimide or epoxy, but may have a laminated structure of these resin layers.
Next, the back side protective film 11 is cured, and thereafter, a lot number, a product number, etc. are marked on the back side protective film 11 by a laser (see FIG. 3). After the completion of marking, as shown in FIG. 4, the wafer 1 is mounted on the dicing tape 21 mounted on the dicing frame (support member) 20 so that the back surface side protective film 11 faces. When the wafer 1 is mounted on the dicing tape 21, a dicing process is performed in which a cutting groove 1a is formed in the wafer 1 along a predetermined cut line CL. At this time, the back surface side protective film 11 may be half cut or may be full cut.
[0015]
After completion of the dicing, as shown in FIG. 5, the side surface (peripheral surface) of the wafer 1 mounted on the dicing frame 20 via the dicing tape 21 is covered and each surface provided on the surface side is covered. A surface-side protective film 3 is formed to cover the surface so as to fill the above-described cutting groove 1a while opening the central portion of the connection pad 2.
The surface-side protective film 3 is spin-coated by, for example, applying a polyimide resin material on the protective film P formed on the surface side of the wafer 1 and each connection pad 2 exposed from the opening of the protective film P. However, the method is not limited to spin coating, and an appropriate method such as a printing method using a squeegee or a coating method by discharging ink from a nozzle can be used.
[0016]
Next, after the surface side protective film 3 formed on the surface of the wafer 1 in this way is cured, a photoresist is applied to the side surface and the upper surface (not shown). (Not shown) The patterning and the surface-side protective film 3 are sequentially patterned, and the opening 4 exposing the central portion of each connection pad 2 is formed in the surface-side protective film 3 as in the conventional example described above. Thereafter, the photoresist is peeled off.
[0017]
Thereafter, as shown in FIG. 6 in which the main part A in FIG. 5 is enlarged, the rewiring 5 is formed on the connection pad 2 exposed through the opening 4 formed in the surface-side protective film 3. . The rewiring 5 is formed by depositing a UBM layer on the entire surface of the protective film 3 on the surface side after the photoresist is peeled off by UBM sputtering or the like. A photoresist for use is patterned by applying a pattern having an opening of a predetermined shape so that the rewiring shown in FIG. 6 is formed, and then electroplating is performed on a portion opened by the resist.
In the state where the rewiring 5 is formed by this electrolytic plating, the UBM layer deposited on the entire surface of the surface-side protective film 3 remains as a plating electrode including the UBM layer portion deposited on the dicing frame 20. Has been.
[0018]
In this way, each rewiring 5 was formed with one end connected to each connection pad 2 and the other end extending over the surface side protective film 3 to the center side of each semiconductor chip separated by cutting. Thereafter, a post (columnar electrode) 6 is provided at a predetermined position on the other end on each rewiring 5. Although the post 6 is not shown in the figure, for example, a post-forming photoresist is applied and cured with a thickness of about 100 to 150 μm, and an opening that exposes the center of the other end of each rewiring 5 is formed. It is formed by applying electrolytic plating in the opening. When this electrolytic plating is performed, the UBM layer deposited on the entire surface of the surface side protective film 3 and the dicing frame 20 is used as one electrode.
After the plating process, the post-forming photoresist is peeled off, and the UBM layer deposited on unnecessary portions is removed by etching. FIG. 6 is an enlarged cross-sectional view in a state where this process is completed.
[0019]
After the structure shown in FIG. 6 is formed in this way, the entire circuit surface of the wafer 1 is molded with a resin material such as polyimide or epoxy so as to cover the post 6 as shown in FIG. A protective film 7 is formed. The surface-side protective film 7 may be composed of a single layer such as polyimide or epoxy, but may have a laminated structure of these resin layers. In this case, the back-side protective layer 11, the front-side protective layer 3, and the front-side protective film 7 described above are resin layers containing substantially the same main component in order to ensure reliability corresponding to environmental changes. It is desirable to form with. And this surface side protective film 7 is hardened, then the upper surface side is grind | polished and the end surface 6a (refer FIG. 8) of the post | mailbox 6 is exposed.
About the exposed end surface 6a, the oxide film on the surface is removed, and a metallization process such as solder printing is performed thereon. Thereafter, as shown in FIG. 9, the portion of the cutting groove 1a is diced again so that the surface-side protective film 3 having a predetermined thickness remains on the cut surface, and the wafer 1 is separated into chips to form the semiconductor device 10. .
[0020]
As described above, according to one embodiment of the present invention, the back surface side protective film 11 is formed so as to cover the back surface of the wafer 1, and then the wafer 1 is diced in advance to obtain a cutting groove. 1a is engraved, and then the surface and side surfaces of the wafer 1 are covered and the surface side protective film 3 filling the cutting grooves 1a is formed. Subsequently, the rewiring 5, the post 6 and the surface side protective film 7 are formed. Since the semiconductor device 10 is formed by dicing again the cutting groove 1a so that the surface-side protective film 3 having a predetermined thickness remains on the cut surface after being provided, the separated semiconductor device 10 has a back surface, a surface, and a side surface. Are all covered with the protective films 3 and 11. As a result, it is possible to remove factors that lower the reliability such as chip breakage and moisture permeation from the exposed surface, and the reliability is improved.
[0021]
In the embodiment of the present invention, since the UBM layer deposited on the dicing frame 20 is left as a plating electrode, it is possible to re-execute without separately forming an electrode on the wafer 1 as in the prior art. It is possible to perform an electrolytic plating process for forming the wiring 5 and the post 6.
Furthermore, in the embodiment of the present invention, since all of the back surface, front surface and side surface of the semiconductor device 10 are covered with the protective films 3 and 11, the semiconductor device 10 separated into chips is transferred to a tray. Handling becomes extremely easy.
[0022]
In the above-described embodiment, after the back side of the wafer 1 having the connection pads 2 formed on the front side is cut and polished, the back side protective film 11 is formed on the back side of the cut and polished wafer 1. The lot number or product number is laser-marked on the back side protective film 11 and then the wafer 1 is mounted on the dicing frame 20 (see FIG. 4). Instead, as shown in FIG. Further, after laser marking the lot number, product number, etc. on the back side of the cut and polished wafer 1, a protective resin (for example, polyimide or the like) is formed on the dicing tape 21 mounted on the dicing frame 20 to a predetermined thickness. The organic resin material) is applied (see FIG. 11), and the back side of the wafer 1 is bonded to the applied protective resin to form the back side protective film 11. There.
[0023]
Furthermore, if a photosensitive resin is used as the material of the surface protective film 3 instead of the above-described form, the steps of applying, curing, and peeling the photoresist for forming the surface protective film 3 can be omitted. Can do.
[0024]
Further, in the dicing process (see FIG. 4) after forming the back surface side protective film 11, if the wafer 1 is diced into individual pieces as shown in FIG. Only non-defective products are selected from the inside and rearranged in the form shown in FIG. 5B or FIG. 6C. Thereafter, the surface protective film 3, the rewiring 5, the post 6, and the second shown in FIG. The surface side protective film 7 may be formed.
When such rearrangement is performed, it is possible to arbitrarily set the chip arrangement interval, for example, and the portion of the cutting groove 1a in FIG. 9 is diced again to separate the wafer 1 into chips to form the semiconductor device 10. In doing so, the thickness of the surface-side protective film 3 formed on the side surface of each semiconductor device 10 can be made sufficient.
[0025]
In the embodiment described above, since the rewiring 5 is formed on the wafer 1 and the post 6 is formed on the rewiring 5, the surface side protective film has a two-layer laminated structure. The present invention can also be applied to a semiconductor device in which the post 6 is formed directly without forming the rewiring 5 on the surface side of the wafer 1, and in this case, the surface side protective film is formed as a single layer. Can be
[0026]
【The invention's effect】
According to the semiconductor device of claim 1, the back surface of the silicon substrate is covered with the back surface side protective film, and at least a part of the front surface and side surface of the silicon substrate and the side surface of the back surface side protective film is the first surface side protective film. And forming a columnar electrode on one end of the rewiring connected to each connection pad through the opening on the first surface side protective film, and each columnar electrode of the silicon substrate excluding covers the entire surface by the surface to form the second surface side protective film so as to be substantially flush with the surface of the columnar electrode, the entire surface of the silicon substrate is covered with a protective film, further, the back side since at least a part of the side surface of the protective film is Ru covered by the first surface protective film, it is possible to improve the reliability of the semiconductor device having the rewiring. According to the semiconductor device of claim 3, the back surface of the silicon substrate is covered with the back surface side protective film, the front surface and the side surface of the silicon substrate are covered with the first surface side protective film, and the first surface side protective film is formed. A rewiring connected to each connection pad through an opening and a columnar electrode formed on one end of the rewiring, covering the entire surface of the silicon substrate except for each columnar electrode, the surface of which is the columnar electrode By forming a second surface side protective film so as to be substantially flush with the surface of the substrate, and providing device attribute markings on the surface of the back side protective film, the entire surface of the silicon substrate is covered with the protective film. The reliability of the semiconductor device can be improved, and the marking can be easily seen. According to the method for manufacturing a semiconductor device according to claim 4, after forming the back surface side protective film covering the back surface of the silicon substrate, a cutting groove is engraved at a location where the silicon substrate is separated, and then A rewiring that covers the surface and side surfaces of the silicon substrate and that forms a first surface-side protective film that fills a cutting groove, and is connected to each connection pad on the first surface-side protective film and the rewiring A columnar electrode is formed on one end of the silicon substrate, a second surface-side protective film covering the entire surface of the silicon substrate excluding the columnar electrodes is formed, and then the first surface-side protective film remains on the cut surface. In addition, since the silicon substrate is cut into individual pieces with a width narrower than the cutting groove, the back, front and side surfaces of the separated semiconductor device are all covered with a protective film. Reduces reliability, such as water penetration from Cause the possible removal, thereby improving the reliability.
[Brief description of the drawings]
FIG. 1 is a diagram for explaining a first embodiment of the present invention, and is a cross-sectional view showing an initial state of a semiconductor device manufacturing process;
FIG. 2 is a cross-sectional view for illustrating the manufacturing process of the semiconductor device following FIG. 1;
FIG. 3 is a cross-sectional view for illustrating the manufacturing process of the semiconductor device following FIG. 2;
4 is a cross-sectional view for explaining a manufacturing step of the semiconductor device following that of FIG. 3; FIG.
FIG. 5 is a cross-sectional view for illustrating the manufacturing process of the semiconductor device following FIG. 4;
6 is a cross-sectional view for explaining a manufacturing step of the semiconductor device following that of FIG. 5; FIG.
7 is a cross-sectional view for explaining a manufacturing step of the semiconductor device following that of FIG. 6; FIG.
FIG. 8 is a cross-sectional view for illustrating the manufacturing process of the semiconductor device following FIG. 8;
FIG. 9 is a cross-sectional view for explaining the manufacturing process of the semiconductor device continued from FIG. 9, and shows a completed state of the semiconductor device separated into pieces of the present invention;
FIG. 10 is a cross-sectional view for explaining a modification of the first embodiment of the semiconductor device of the present invention.
FIG. 11 is a cross-sectional view for explaining a second embodiment of a semiconductor device of the invention.
FIG. 12 is a plan view for explaining a modification of the first and second embodiments of the present invention.
FIG. 13 is a cross-sectional view for explaining the manufacturing method of the conventional semiconductor device.
FIG. 14 is a cross-sectional view for illustrating a process following the process in FIG. 13;
FIG. 15 is a cross-sectional view for explaining a process following the process in FIG. 14;
16 is a cross-sectional view for illustrating a process following the process in FIG. 15. FIG.
[Explanation of symbols]
1 Wafer (silicon substrate)
1a Cutting groove 2 Connection pad 3 Surface side protective film (first surface side protective film)
4 Opening 5 Rewiring 6 Post (columnar electrode)
7 Surface protective film (second surface protective film)
DESCRIPTION OF SYMBOLS 10 Semiconductor device 11 Back surface side protective film 20 Dicing frame 21 Dicing tape (support member)

Claims (12)

表面に複数の接続パッドを有するシリコン基板と、
前記シリコン基板の背面を覆う裏面側保護膜と、
前記シリコン基板の表面、側面および前記裏面側保護膜の側面の少なくとも一部を覆って形成され前記各接続パッドを露出する開口部を有する第１の表面側保護膜と、
前記第１の表面側保護膜上に形成され、各々、前記開口部を介して前記各接続パッドに接続された複数の再配線と、
各々、前記各再配線の一端上に形成された複数の柱状電極と、
前記シリコン基板の前記各柱状電極を除く表面全体を覆い、その表面が前記柱状電極の表面とほぼ同一面となるように形成された第２の表面側保護膜と
を具備することを特徴とする半導体装置。A silicon substrate having a plurality of connection pads on the surface;
A back side protective film covering the back side of the silicon substrate;
A first surface-side protective film formed to cover at least a part of the surface, side surface and side surface of the back-side protective film of the silicon substrate and having an opening that exposes the connection pads;
A plurality of rewirings formed on the first surface-side protective film, each connected to the connection pads via the openings;
A plurality of columnar electrodes each formed on one end of each rewiring;
A second surface-side protective film formed so as to cover the entire surface of the silicon substrate excluding the columnar electrodes and to have the surface substantially flush with the surface of the columnar electrodes. Semiconductor device. 前記裏面側保護膜、前記第１の表面側保護膜及び前記第２の表面側保護膜は主成分が実質的に同一な材料を含むものであることを特徴とする請求項１記載の半導体装置。  2. The semiconductor device according to claim 1, wherein the back surface side protective film, the first surface side protective film, and the second surface side protective film contain substantially the same material. 表面に複数の接続パッドを有するシリコン基板と、
前記シリコン基板の背面を覆う裏面側保護膜と、
前記シリコン基板の表面および側面を覆って形成され前記各接続パッドを露出する開口部を有する第１の表面側保護膜と、
前記第１の表面側保護膜上に形成され、各々、前記開口部を介して前記各接続パッドに接続された複数の再配線と、
各々、前記各再配線の一端上に形成された複数の柱状電極と、
前記シリコン基板の前記各柱状電極を除く表面全体を覆い、その表面が前記柱状電極の表面とほぼ同一面となるように形成された第２の表面側保護膜と、を具備し、
前記裏面側保護膜の表面に装置属性のマーキングが設けられていることを特徴とする半導体装置。A silicon substrate having a plurality of connection pads on the surface;
A back side protective film covering the back side of the silicon substrate;
A first surface-side protective film formed to cover the surface and side surfaces of the silicon substrate and having an opening that exposes each connection pad;
A plurality of rewirings formed on the first surface-side protective film, each connected to the connection pads via the openings;
A plurality of columnar electrodes each formed on one end of each rewiring;
A second surface-side protective film that covers the entire surface of the silicon substrate excluding the columnar electrodes and is formed so that the surface thereof is substantially flush with the surface of the columnar electrodes;
A device attribute marking is provided on the surface of the back side protective film. 表面に複数の接続パッドを有するシリコン基板にその背面を覆う裏面側保護膜を形成する第１の工程と、
前記シリコン基板を個片化する箇所に切削溝を設け、その後に前記シリコン基板の表面および側面を覆うと共に、前記切削溝を充填する第１の表面側保護膜を形成する第２の工程と、
前記シリコン基板の表面を覆う第１の表面側保護膜に前記各接続パッドを露出する開口部を形成し、前記第１の表面側保護膜上に形成され、各々、前記開口部を介して前記各接続パッドに接続された複数の再配線を形成する第３の工程と、
各々、前記各再配線の一端上に複数の柱状電極を形成する第４の工程と、
前記シリコン基板の前記各柱状電極を除く表面全体を覆う第２の表面側保護膜を形成する第５の工程と、
前記第１の表面側保護膜が切断面に残るように、前記切削溝より狭い幅でシリコン基板を個片に切断する第６の工程と
を具備することを特徴とする半導体装置の製造方法。A first step of forming a back surface side protective film covering the back surface of a silicon substrate having a plurality of connection pads on the surface;
A second step of forming a first groove on the silicon substrate and then forming a first surface-side protective film that covers the surface and side surfaces of the silicon substrate and fills the cutting groove;
An opening exposing each of the connection pads is formed in a first surface-side protective film covering the surface of the silicon substrate, and formed on the first surface-side protective film, and the opening is exposed through the opening. A third step of forming a plurality of rewirings connected to each connection pad;
A fourth step of forming a plurality of columnar electrodes on one end of each of the rewirings;
A fifth step of forming a second surface-side protective film that covers the entire surface of the silicon substrate excluding the columnar electrodes;
And a sixth step of cutting the silicon substrate into pieces with a width narrower than the cutting groove so that the first surface-side protective film remains on the cut surface. 前記裏面側保護膜は、前記シリコン基板の背面に被着して形成することを特徴とする請求項４記載の半導体装置の製造方法。  5. The method of manufacturing a semiconductor device according to claim 4, wherein the back-side protective film is formed by being attached to the back surface of the silicon substrate. 前記第１の工程は、支持部材上に前記裏面側保護膜を形成し、該裏面側保護膜に前記シリコン基板の背面を被着する工程を含むことを特徴とする請求項４記載の半導体装置の製造方法。  5. The semiconductor device according to claim 4, wherein the first step includes a step of forming the back surface side protective film on a support member, and depositing a back surface of the silicon substrate on the back surface side protective film. Manufacturing method. 前記第１の工程は、前記シリコン基板をダイシングテープ上に装着する工程を含むことを特徴とする請求項４記載の半導体装置の製造方法。  5. The method of manufacturing a semiconductor device according to claim 4, wherein the first step includes a step of mounting the silicon substrate on a dicing tape. 前記第１の工程は、表面側に電極を設けた前記シリコン基板の背面側を切削研磨してから前記裏面側保護膜を形成し、この裏面側保護膜上に装置属性をマーキングすることを特徴とする請求項４記載の半導体装置の製造方法。  In the first step, the back side of the silicon substrate provided with electrodes on the front side is cut and polished, the back side protective film is formed, and device attributes are marked on the back side protective film. A method for manufacturing a semiconductor device according to claim 4. 前記第１の工程は、切削研磨されたシリコン基板の背面側に装置属性をマーキングした後、支持部材に塗布された樹脂材上に当該シリコン基板の背面側を貼り合わせて前記裏面側保護膜を形成することを特徴とする請求項４に記載の半導体装置の製造方法。  In the first step, the device attribute is marked on the back side of the cut and polished silicon substrate, and then the back side of the silicon substrate is bonded to the resin material applied to the support member to attach the back side protective film. The method of manufacturing a semiconductor device according to claim 4, wherein the semiconductor device is formed. 前記第２の工程は、前記表面側保護膜を感光性樹脂を用いて形成することを特徴とする請求項４記載の半導体装置の製造方法。  5. The method of manufacturing a semiconductor device according to claim 4, wherein in the second step, the surface-side protective film is formed using a photosensitive resin. 前記第２の工程は、第１の表面側保護膜を印刷または塗布により切削溝を充填する工程を含むことを特徴とする請求項４記載の半導体装置の製造方法。5. The method of manufacturing a semiconductor device according to claim 4, wherein the second step includes a step of filling the cutting groove by printing or applying the first surface-side protective film. 前記第１の工程は、前記シリコン基板をダイシングテープ上に装着する工程を含み、前記第２の工程は、前記ダイシングテープ上を含めて前記シリコン基板の表面および側面に前記第１の表面側保護膜を形成する工程を含むことを特徴とする請求項４記載の半導体装置の製造方法。Wherein the first step includes a step of mounting the silicon substrate on the dicing tape, the second step, the surface and the first surface on a side surface of the silicon substrate including the pre Symbol dicing tape on 5. The method of manufacturing a semiconductor device according to claim 4, further comprising a step of forming a protective film.
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