CN110473792B - Reconstruction method for integrated circuit wafer level packaging - Google Patents

Reconstruction method for integrated circuit wafer level packaging Download PDF

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Publication number
CN110473792B
CN110473792B CN201910823826.0A CN201910823826A CN110473792B CN 110473792 B CN110473792 B CN 110473792B CN 201910823826 A CN201910823826 A CN 201910823826A CN 110473792 B CN110473792 B CN 110473792B
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China
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layer
chip
metal
cutting
plastic packaging
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CN201910823826.0A
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Chinese (zh)
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CN110473792A (en
Inventor
徐开凯
刘炜恒
施宝球
曾德贵
赵建明
曾尚文
钱呈
钱津超
李建全
廖楠
徐银森
刘继芝
李洪贞
陈勇
黄平
李健儿
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Chongqing Zhongke Yuxin Electronic Co ltd
Shanghai Fine Chip Semiconductor Co ltd
Sichuan Jinghui Semiconductor Co ltd
Sichuan Shangte Technology Co ltd
Sichuan Suining Lipuxin Microelectronic Co ltd
Sichuan Xinhe Li Cheng Technology Co ltd
University of Electronic Science and Technology of China
Guangan Vocational and Technical College
Sichuan Blue Colour Electronics Technology Co Ltd
Original Assignee
Chongqing Zhongke Yuxin Electronic Co ltd
Shanghai Fine Chip Semiconductor Co ltd
Sichuan Jinghui Semiconductor Co ltd
Sichuan Shangte Technology Co ltd
Sichuan Suining Lipuxin Microelectronic Co ltd
Sichuan Xinhe Li Cheng Technology Co ltd
University of Electronic Science and Technology of China
Guangan Vocational and Technical College
Sichuan Blue Colour Electronics Technology Co Ltd
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Application filed by Chongqing Zhongke Yuxin Electronic Co ltd, Shanghai Fine Chip Semiconductor Co ltd, Sichuan Jinghui Semiconductor Co ltd, Sichuan Shangte Technology Co ltd, Sichuan Suining Lipuxin Microelectronic Co ltd, Sichuan Xinhe Li Cheng Technology Co ltd, University of Electronic Science and Technology of China, Guangan Vocational and Technical College, Sichuan Blue Colour Electronics Technology Co Ltd filed Critical Chongqing Zhongke Yuxin Electronic Co ltd
Priority to CN201910823826.0A priority Critical patent/CN110473792B/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods

Abstract

The invention discloses a reconstruction method for integrated circuit wafer level packaging, which comprises the following steps: (1) re-laying and wiring the original chip; (2) performing passivation treatment on the surface of the re-laid wiring layer; (3) filling a first plastic packaging layer after the chip is inverted; (4) depositing a metal epitaxial layer on a pin externally connected with the chip; (5) performing a first cutting process; (6) filling a second plastic packaging layer; (7) carrying out a chemical mechanical polishing process until the metal epitaxial layer is exposed out of the welding surface; (8) generating a metal solder ball on the welding surface of the metal epitaxial layer; (9) a second cutting process is performed. The invention can solve the technical problem of high cost caused by the need of using a high-cost die in the prior art, does not need to use a high-cost die, and greatly reduces the production cost. The invention belongs to the technical field of semiconductors.

Description

Reconstruction method for integrated circuit wafer level packaging
Technical Field
The invention belongs to the technical field of semiconductors, and relates to a reconstruction method of semiconductor packaging, in particular to a reconstruction method for integrated circuit wafer level packaging.
Background
With the development of semiconductor technology, after the semiconductor chip enters deep submicron and even higher process progress, the number of integrated transistors of the chip is continuously increased, the function integration is more and more, the performance is better and better, and meanwhile, the volume of the whole chip is smaller and smaller. However, in today's complex application scenarios, a high-power chip usually needs a plurality of power pins to ensure normal output and heat dissipation of power consumption, and a SoC chip needs a plurality of I/O interfaces to support high speed, so that more and more metal connection points need to be led out. However, external circuit connectors have not been able to be further reduced in size as semiconductor manufacturing processes have advanced, and thus, rearranging and scaling up chip metal connection points has become very important in practical applications.
However, the conventional reconfiguration technique is performed after the die is cut, and a mold is often required to be manufactured, which is expensive.
Disclosure of Invention
The invention aims to provide a reconstruction method for integrated circuit wafer level packaging, which solves the technical problem of high cost caused by the need of using a high-cost mold in the prior art, and achieves the technical effects of reducing the production cost without using the high-cost mold.
In order to achieve the purpose, the invention adopts the following technical scheme:
a reconfiguration method for an integrated circuit wafer level package, the method comprising the steps of:
(1) re-laying out and wiring the chip which is not subjected to the cutting process to form a re-laid wiring layer;
(2) passivating the surface of the rewiring layer, and then performing a chemical mechanical polishing process until the chip external pins of the rewiring layer are exposed;
(3) the top layer of the chip is placed on the bearing plate in an inverted mode, epoxy resin is poured on the bottom layer of the chip, and a first plastic packaging layer is formed;
(4) the chip and the first plastic packaging layer are integrally turned over, the first plastic packaging layer is placed on the bearing plate, and a metal deposition process or an electroplating process is carried out on the chip external pins to form a metal epitaxial layer;
(5) performing a first cutting process on the chip and the first plastic package layer, wherein the cutting width is L1, and the cutting depth is greater than the thickness of the chip and less than the sum of the thicknesses of the chip and the first plastic package layer to form a first cutting channel;
(6) filling epoxy resin in the first cutting channel to cover the welding surface of the metal epitaxial layer to form a second plastic packaging layer;
(7) carrying out a chemical mechanical polishing process on the second plastic packaging layer until the metal epitaxial layer is exposed out of the welding surface;
(8) carrying out an electroplating process or a ball planting process on the welding surface to grow a metal welding ball;
(9) and performing a second cutting process on the first plastic packaging layer and the second plastic packaging layer, wherein the cutting width is L2 (L1 > L2), and the cutting depth is completely cut to the surface of the bearing plate.
As a limitation of the present invention: in the step (1), the re-layout wiring layer is provided with a layer of wiring, and the re-layout wiring process is to perform metal deposition on the exposed surface of the original chip pin, grow a metal layer, form an external chip pin and etch redundant metal to form a metal connecting wire.
As another limitation of the invention: the passivation treatment in the step (2) is to re-lay a passivation layer of which the covering material of the wiring layer is a curing agent, resin or silicon nitride.
Due to the adoption of the technical scheme, compared with the prior art, the invention has the following beneficial effects:
(1) the invention provides a reconstruction method for integrated circuit wafer level packaging, which is characterized in that the wafer chip which is not cut is firstly re-arranged and wired, then the cutting process, the injection of a plastic package layer, the manufacture of a metal epitaxial layer and other process steps are carried out, the process steps are simple, wherein the manufacture of the metal epitaxial layer is used for leading out a welding surface, a foundation is laid for the manufacture of the re-arranged wiring layer, the bad influence on a chip circuit caused by the process steps of reconstruction and plastic package is prevented, and the high-cost mould is not needed, so that the production cost is greatly reduced;
(2) the invention completes the re-layout wiring of the chip by the metal deposition process and the etching process, and the process is simple;
(3) the passivation layer is covered on the re-layout wiring layer, so that the metal connecting wire of the re-layout wiring layer is hidden, and the protection effect is achieved.
In conclusion, the invention has simple process steps, ensures that a chip circuit is not influenced, also plays a role in protecting the metal connecting wire, does not need to use a high-cost die and greatly reduces the production cost.
Drawings
The invention is described in further detail below with reference to the figures and the embodiments.
FIG. 1 is a top view of a single chip to be reconstituted;
FIG. 2 is a partial top view of an uncut wafer to be reconstituted;
FIG. 3 is a partial top view of a single chip after re-placement and routing;
FIG. 4 is a partial top view of a wafer after rerouting;
FIG. 5 is a schematic diagram of a wafer local chip external pin structure viewed from above after re-layout and wiring (the subsequent reconfiguration process is shown by a section at a dotted line position in the diagram);
FIGS. 6-13 are schematic diagrams of a reconfiguration method for integrated circuit wafer level packaging;
fig. 14 is a flow chart of a wafer level reconfigured package structure.
In the figure: 101. A primary chip pin; 301. a metal connection line; 302. the chip is externally connected with a pin; 610. a first plastic packaging layer; 620. A chip; 621. A chip top layer; 630. a metal epitaxial layer; 640. a second plastic packaging layer; 641. Welding the surface; 650. a metal solder ball; 660. a carrier plate.
Detailed Description
Embodiments of the present invention will be described below with reference to the accompanying drawings. It is to be understood that the examples described herein are for purposes of illustration and understanding only and are not intended to limit the invention.
Embodiment a reconstruction method for integrated circuit wafer level packaging
As shown in fig. 1-13, the present embodiment proceeds in the following sequence of steps:
(1) as shown in fig. 1 to 4, a re-layout wiring process is performed on a chip on which a cutting process is not performed;
carrying out metal deposition on the exposed surface of the original chip pin 101, growing a metal layer to form a chip external pin 302, etching redundant metal to form a metal connecting wire 301, and enabling the metal connecting wire 301 and the chip external pin 302 to form a re-layout wiring layer with re-arranged pins;
(2) covering a passivation layer made of a curing agent, resin or silicon nitride on the surface of the re-layout wiring layer, then performing a chemical mechanical polishing process on the passivation layer until the chip external pin 302 of the re-layout wiring layer is exposed, and overlooking the structure diagram of the chip external pin 302 of the wafer part as shown in fig. 5;
(3) the top layer 621 of the chip is placed on the bearing plate 660 upside down, and is glued and fixed, epoxy resin is poured on the bottom layer of the chip 620, and a first plastic packaging layer 610 which plays a role in supporting and sealing the lower surface of the packaging structure reconstructed by the chip 620 is formed;
in this embodiment, the thickness of the first plastic package layer 610 is equal to the thickness of the silicon wafer;
(4) turning over the chip 620 and the first plastic package layer 610 integrally to enable the first plastic package layer 610 to be placed on the bearing plate 660, gluing and fixing, and performing a metal deposition process or an electroplating process on the chip external pin 302 to form a metal epitaxial layer 630;
(5) cutting down from the top layer 621 of the chip 620, performing a first cutting process;
the cutting width of the first cutting process is L1, the cutting depth is greater than the thickness of the chip 620 and less than the sum of the thicknesses of the chip 620 and the first plastic packaging layer 610, and finally a first cutting channel is formed;
(6) filling epoxy resin in the first cutting channel until covering the metal epitaxial layer welding surface 641 to form a second plastic packaging layer 640;
(7) performing a chemical mechanical polishing process on the second plastic package layer 640 until the metal epitaxial layer 630 exposes the welding surface 641;
(8) performing an electroplating process or a ball-planting process on the soldering surface 641 to grow a metal solder ball 650 interconnected with an external test circuit or an application circuit;
(9) performing a second cutting process on the first and second plastic-sealed layers 610 and 640;
the second cutting process has a cutting width of L2 (L1 > L2) and a cutting depth of completely cutting the surface of the carrier plate 660.
In this embodiment, the chip 620 may be a logic chip such as a CPU, a DSP, an FPGA, or a general memory chip such as an ASIC, a DRAM; the metal epitaxial layer 630 may be a common metal such as aluminum, copper, etc., or a combination thereof, or a compound thereof.

Claims (2)

1. A reconfiguration method for an integrated circuit wafer level package, said method comprising the steps of:
(1) executing a re-layout wiring process on the chip which is not subjected to the cutting process to form a re-layout wiring layer;
the re-layout wiring layer is provided with a layer of wiring, and the re-layout wiring process is to perform metal deposition on the exposed surface of the original chip pin, grow a metal layer to form a chip external pin, and etch redundant metal to form a metal connecting wire;
(2) passivating the surface of the rewiring layer, and then performing a chemical mechanical polishing process until the chip external pins of the rewiring layer are exposed;
(3) the top layer of the chip is placed on the bearing plate in an inverted mode, epoxy resin is poured on the bottom layer of the chip, and a first plastic packaging layer is formed;
(4) turning over the chip and the first plastic packaging layer to enable the first plastic packaging layer to be arranged on the bearing plate, and carrying out a metal deposition process or an electroplating process on the chip external pins to form a metal epitaxial layer;
(5) performing a first cutting process on the chip and the first plastic package layer, wherein the cutting width is L1, and the cutting depth is greater than the thickness of the chip and less than the sum of the thicknesses of the chip and the first plastic package layer to form a first cutting channel;
(6) filling epoxy resin in the first cutting channel to cover the welding surface of the metal epitaxial layer to form a second plastic packaging layer;
(7) carrying out a chemical mechanical polishing process on the second plastic packaging layer until the metal epitaxial layer is exposed out of the welding surface;
(8) carrying out an electroplating process or a ball planting process on the welding surface to grow a metal welding ball;
(9) and performing a second cutting process on the first plastic packaging layer and the second plastic packaging layer, wherein the cutting width is L2 (L1 > L2), and the cutting depth is completely cut to the surface of the bearing plate.
2. The method as claimed in claim 1, wherein the passivation process in step (2) is a passivation layer made of curing agent, resin or silicon nitride.
CN201910823826.0A 2019-09-02 2019-09-02 Reconstruction method for integrated circuit wafer level packaging Active CN110473792B (en)

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001326299A (en) * 2000-05-18 2001-11-22 Iep Technologies:Kk Semiconductor device and method for manufacturing the same
JP2005191485A (en) * 2003-12-26 2005-07-14 Seiko Instruments Inc Semiconductor device
CN102122646A (en) * 2011-02-01 2011-07-13 南通富士通微电子股份有限公司 Wafer packaging device and chip packaging unit
CN110098160A (en) * 2019-02-26 2019-08-06 上海朕芯微电子科技有限公司 A kind of wafer-level packaging chip and preparation method thereof
US20190267302A1 (en) * 2018-02-28 2019-08-29 Stmicroelectronics Pte Ltd Semiconductor package with protected sidewall and method of forming the same

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3465617B2 (en) * 1999-02-15 2003-11-10 カシオ計算機株式会社 Semiconductor device
JP4126389B2 (en) * 2002-09-20 2008-07-30 カシオ計算機株式会社 Manufacturing method of semiconductor package
CN108336052B (en) * 2018-02-08 2021-01-05 颀中科技（苏州）有限公司 Metal rewiring structure, chip packaging device and chip packaging device manufacturing process

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001326299A (en) * 2000-05-18 2001-11-22 Iep Technologies:Kk Semiconductor device and method for manufacturing the same
JP2005191485A (en) * 2003-12-26 2005-07-14 Seiko Instruments Inc Semiconductor device
CN102122646A (en) * 2011-02-01 2011-07-13 南通富士通微电子股份有限公司 Wafer packaging device and chip packaging unit
US20190267302A1 (en) * 2018-02-28 2019-08-29 Stmicroelectronics Pte Ltd Semiconductor package with protected sidewall and method of forming the same
CN110098160A (en) * 2019-02-26 2019-08-06 上海朕芯微电子科技有限公司 A kind of wafer-level packaging chip and preparation method thereof

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