CN110473792B - Reconstruction method for integrated circuit wafer level packaging - Google Patents
Reconstruction method for integrated circuit wafer level packaging Download PDFInfo
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- CN110473792B CN110473792B CN201910823826.0A CN201910823826A CN110473792B CN 110473792 B CN110473792 B CN 110473792B CN 201910823826 A CN201910823826 A CN 201910823826A CN 110473792 B CN110473792 B CN 110473792B
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- plastic packaging
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- 238000000034 method Methods 0.000 title claims abstract description 41
- 238000004806 packaging method and process Methods 0.000 title claims abstract description 31
- 229910052751 metal Inorganic materials 0.000 claims abstract description 35
- 239000002184 metal Substances 0.000 claims abstract description 35
- 238000005520 cutting process Methods 0.000 claims abstract description 34
- 239000004033 plastic Substances 0.000 claims abstract description 31
- 238000003466 welding Methods 0.000 claims abstract description 12
- 238000002161 passivation Methods 0.000 claims abstract description 8
- 238000007517 polishing process Methods 0.000 claims abstract description 7
- 239000000126 substance Substances 0.000 claims abstract description 7
- 238000001465 metallisation Methods 0.000 claims description 7
- 238000009713 electroplating Methods 0.000 claims description 6
- 239000003822 epoxy resin Substances 0.000 claims description 6
- 229920000647 polyepoxide Polymers 0.000 claims description 6
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 3
- 239000003795 chemical substances by application Substances 0.000 claims description 3
- 229920005989 resin Polymers 0.000 claims description 3
- 239000011347 resin Substances 0.000 claims description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 3
- 238000004021 metal welding Methods 0.000 claims description 2
- 238000004519 manufacturing process Methods 0.000 abstract description 8
- 239000004065 semiconductor Substances 0.000 abstract description 6
- 229910000679 solder Inorganic materials 0.000 abstract description 3
- 238000000151 deposition Methods 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 238000004026 adhesive bonding Methods 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
Claims (2)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201910823826.0A CN110473792B (en) | 2019-09-02 | 2019-09-02 | Reconstruction method for integrated circuit wafer level packaging |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201910823826.0A CN110473792B (en) | 2019-09-02 | 2019-09-02 | Reconstruction method for integrated circuit wafer level packaging |
Publications (2)
Publication Number | Publication Date |
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CN110473792A CN110473792A (en) | 2019-11-19 |
CN110473792B true CN110473792B (en) | 2021-04-02 |
Family
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Family Applications (1)
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CN201910823826.0A Active CN110473792B (en) | 2019-09-02 | 2019-09-02 | Reconstruction method for integrated circuit wafer level packaging |
Country Status (1)
Country | Link |
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CN (1) | CN110473792B (en) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
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CN112838057B (en) * | 2021-01-08 | 2022-04-05 | 江苏东海半导体股份有限公司 | Scribing method suitable for IGBT semiconductor device |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2001326299A (en) * | 2000-05-18 | 2001-11-22 | Iep Technologies:Kk | Semiconductor device and method for manufacturing the same |
JP2005191485A (en) * | 2003-12-26 | 2005-07-14 | Seiko Instruments Inc | Semiconductor device |
CN102122646A (en) * | 2011-02-01 | 2011-07-13 | 南通富士通微电子股份有限公司 | Wafer packaging device and chip packaging unit |
CN110098160A (en) * | 2019-02-26 | 2019-08-06 | 上海朕芯微电子科技有限公司 | A kind of wafer-level packaging chip and preparation method thereof |
US20190267302A1 (en) * | 2018-02-28 | 2019-08-29 | Stmicroelectronics Pte Ltd | Semiconductor package with protected sidewall and method of forming the same |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3465617B2 (en) * | 1999-02-15 | 2003-11-10 | カシオ計算機株式会社 | Semiconductor device |
JP4126389B2 (en) * | 2002-09-20 | 2008-07-30 | カシオ計算機株式会社 | Manufacturing method of semiconductor package |
CN108336052B (en) * | 2018-02-08 | 2021-01-05 | 颀中科技(苏州)有限公司 | Metal rewiring structure, chip packaging device and chip packaging device manufacturing process |
-
2019
- 2019-09-02 CN CN201910823826.0A patent/CN110473792B/en active Active
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2001326299A (en) * | 2000-05-18 | 2001-11-22 | Iep Technologies:Kk | Semiconductor device and method for manufacturing the same |
JP2005191485A (en) * | 2003-12-26 | 2005-07-14 | Seiko Instruments Inc | Semiconductor device |
CN102122646A (en) * | 2011-02-01 | 2011-07-13 | 南通富士通微电子股份有限公司 | Wafer packaging device and chip packaging unit |
US20190267302A1 (en) * | 2018-02-28 | 2019-08-29 | Stmicroelectronics Pte Ltd | Semiconductor package with protected sidewall and method of forming the same |
CN110098160A (en) * | 2019-02-26 | 2019-08-06 | 上海朕芯微电子科技有限公司 | A kind of wafer-level packaging chip and preparation method thereof |
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Publication number | Publication date |
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CN110473792A (en) | 2019-11-19 |
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Legal Events
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PB01 | Publication | ||
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SE01 | Entry into force of request for substantive examination | ||
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TA01 | Transfer of patent application right |
Effective date of registration: 20200703 Address after: 611731 Chengdu province high tech Zone (West) West source Avenue, No. 2006 Applicant after: UNIVERSITY OF ELECTRONIC SCIENCE AND TECHNOLOGY Applicant after: GUANG'AN VOCATIONAL AND TECHNICAL College Applicant after: SICHUAN JINGHUI SEMICONDUCTOR Co.,Ltd. Applicant after: Sichuan Suining Lipuxin Microelectronic Co.,Ltd. Applicant after: SICHUAN BLUE COLOUR ELECTRONICS TECHNOLOGY Co.,Ltd. Applicant after: SHANGHAI FINE CHIP SEMICONDUCTOR Co.,Ltd. Applicant after: SICHUAN SHANGTE TECHNOLOGY Co.,Ltd. Applicant after: CHONGQING ZHONGKE YUXIN ELECTRONIC Co.,Ltd. Applicant after: Sichuan Xinhe Li Cheng Technology Co.,Ltd. Address before: 611731 Chengdu province high tech Zone (West) West source Avenue, No. 2006 Applicant before: UNIVERSITY OF ELECTRONIC SCIENCE AND TECHNOLOGY Applicant before: Sichuan Xinhe Li Cheng Technology Co.,Ltd. Applicant before: GUANGDONG CHIPPACKING TECHNOLOGY Co.,Ltd. Applicant before: GUANG'AN VOCATIONAL AND TECHNICAL College Applicant before: SICHUAN JINGHUI SEMICONDUCTOR Co.,Ltd. Applicant before: Sichuan Suining Lipuxin Microelectronic Co.,Ltd. Applicant before: SICHUAN BLUE COLOUR ELECTRONICS TECHNOLOGY Co.,Ltd. Applicant before: SHANGHAI FINE CHIP SEMICONDUCTOR Co.,Ltd. Applicant before: SICHUAN SHANGTE TECHNOLOGY Co.,Ltd. Applicant before: CHONGQING ZHONGKE YUXIN ELECTRONIC Co.,Ltd. |
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