JP3727939B2 - Manufacturing method of semiconductor device - Google Patents

Description

  The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device including a back surface grinding process for thinning a wafer in a wafer level package in which a plurality of devices are fabricated.

  In the following description, unless otherwise defined, “semiconductor device” refers to individual semiconductor chips (devices) after being cut and divided from the wafer, unless otherwise defined. It also refers to individual semiconductor elements (devices) that are still in a state before being cut and divided.

  In recent years, along with demands for downsizing electronic devices and apparatuses, downsizing and higher density of semiconductor devices used therefor have been attempted. For this reason, a semiconductor device having a chip size package (CSP) structure in which the size of the semiconductor device is reduced as close as possible to the shape of each semiconductor element (semiconductor chip) has been developed and manufactured.

  In a semiconductor device having a typical CSP structure, a passivation film (insulating film) as a protective film is formed on the surface of a semiconductor wafer on which a device is built, and a required film of the insulating film is formed on the insulating film. A rewiring layer (rewiring pattern) is formed to connect the wiring layer (electrode pad) of each device to the outside of the package through a via hole formed in the location, and further in the terminal formation portion of this rewiring layer A metal post is provided, and the entire surface on which the metal post is formed is sealed with sealing resin (but the top of the metal post is exposed), and further on the top of the metal post Metal bumps as external connection terminals are joined.

  With regard to various devices such as flash memory and DRAM, which are used for such CSP-structured semiconductor devices, as a future trend, there is a further demand for thinner wafer-level packages in the stage before being divided into individual semiconductor chips. It is growing. In order to reduce the thickness, a process of grinding the back surface of the wafer is generally performed.

  In the conventional wafer level package manufacturing process, the process of grinding the back surface of the wafer is performed in the first stage. In other words, at the stage after forming a plurality of devices on a semiconductor wafer (the stage before forming a passivation film (insulating film) on the wafer surface), back grinding using a wafer back grinding apparatus, which is a general technique ( After the wafer was thinned by back grinding (BG) processing, the subsequent steps were flowed.

  In the process related to the wafer back surface grinding process, a tape for protecting the pattern surface (hereinafter referred to as “BG tape” for the sake of convenience) is applied during back surface grinding. At this time, a dedicated laminator for attaching the BG tape and a dedicated remover for removing the BG tape after grinding the wafer back surface are required. Tape was also needed. In addition to the function of protecting the pattern surface, the BG tape used for back surface grinding also has a function of keeping the surface on which the pattern is formed flat. For this reason, a thick film type tape that can absorb irregularities on the surface is generally used for the BG tape.

As a technique related to the back surface grinding process for reducing the thickness of the wafer as described above, for example, there is a technique in which the back surface of the wafer is ground after resin sealing (for example, Patent Document 1 and Patent Document 2). reference).
JP 2002-270720 A JP 2002-231854 A

  As described above, in the manufacturing process of the conventional wafer level package, a thick film type BG tape is required in the process related to the wafer back grinding process, and this thick film type BG tape is very expensive. In addition, since a dedicated laminator and a dedicated remover (including a peeling tape) are indispensable, it has been a major obstacle (increase in manufacturing cost) in terms of cost in realizing a thin wafer level package.

  In addition, the wafer back surface grinding process is performed at the first stage in the manufacturing process of the wafer level package, and it is necessary to process all subsequent processes in a thin wafer state (thin wafer state). The possibility of a fatal defect called “wafer cracking” was high.

  In order to cope with this, for example, it may be possible to handle the thin wafer so that wafer cracking does not occur by elaborating the holding / transfer mechanism of the apparatus transfer system. There was a problem that the cost concerned increased. As another method for avoiding wafer cracking due to processing in a thin wafer state, the wafer back surface grinding process is performed as much as possible in the wafer level package manufacturing process (ideally, the final stage). It is possible to do so. For example, if the wafer back surface grinding process is performed after the resin sealing is performed in the final assembly process, at least a wafer crack caused by the process in a thin wafer state can be avoided.

  However, if the wafer back surface grinding process is performed after resin sealing, there is a possibility that the wafer cracks due to another cause. That is, when resin sealing is performed, for example, as shown in FIG. 10 (a), the mold resin (19) diffuses to the outer peripheral portion of the wafer (30), and the diffused mold resin protrudes to the wafer edge portion and the wafer back surface. (In other words, the mold resin protrudes from the back surface of the wafer.) When the wafer back surface grinding process is performed in this state, the resin enters the polishing grindstone that should originally polish only the wafer material (silicon). There is a risk of clogging, which prevents smooth polishing and may cause the wafer to crack. Therefore, unless some contrivance is applied, it is not appropriate to perform the wafer back surface grinding after the resin sealing.

  Further, as a later stage, it is conceivable to mount solder balls and perform wafer back grinding after reflow (after solder bump bonding). However, even at this stage, the mold resin that protrudes from the wafer back remains. In addition, an expensive BG tape, a dedicated laminator, and a dedicated remover (including a peeling tape) are still required, and the problem that the manufacturing cost increases remains.

  Further, when the wafer is thinned, there is a problem that the entire wafer is warped during the manufacturing process. For example, when sealing and thermosetting (curing) a mold resin, an extremely thin wafer is pulled to the resin layer side under the influence of thermal shrinkage of the sealing resin, and the entire wafer is warped. For this reason, the processes after the resin sealing step (solder ball mounting, reflow, dicing, etc.) must be caused to flow while the wafer is warped. As described above, the conventional technique has a disadvantage that the entire wafer is warped when the wafer level package is thinned.

  As a method for dealing with such inconvenience, for example, it is conceivable to form a film layer (for example, an insulating resin film made of an epoxy resin, a silicone resin, a polyimide resin, etc.) for warpage correction on the back surface of the wafer by a vacuum laminating method. . In this case, the epoxy-based, silicone-based, and polyimide-based film layers cannot be peeled off after being formed (after the thermosetting treatment), and therefore need to be left as a permanent film. For this reason, it is necessary to perform various reliability tests (such as an adhesion reliability test with the wafer) on the wafer with the permanent film (film layer for correcting warpage).

  However, in this case, when the wafer is finally diced and divided into individual semiconductor chips (devices), chipping or cracks occur in the individual chips due to mechanical impact during dicing, and this is caused by the chipping. There is a problem that peeling occurs between the film layer and the chip back surface. That is, since the peeling of the permanent film (film layer) from the back surface of the chip occurs after various reliability tests, the meaning of performing the reliability test is lost.

  The present invention was created in view of the problems in the prior art, and a semiconductor device manufacturing method capable of preventing wafer cracking and contributing to a reduction in manufacturing cost in realizing a thin wafer level package. The purpose is to provide.

  In addition, the present invention corrects the warpage of the wafer and realizes the warp correction layer on the back surface as a non-permanent film and eliminates the need for various reliability tests when realizing a thin wafer level package. An object is to provide a method for manufacturing a semiconductor device.

  In order to solve the above-described problems of the prior art, according to the first aspect of the present invention, an opening through which the electrode pad of each device is exposed is formed on the surface of the semiconductor wafer on which a plurality of devices are formed. A step of forming an insulating film so as to have, a step of forming a conductor layer patterned into a required shape so as to cover the opening from which the electrode pad is exposed on the insulating film, and on the conductor layer, Forming a resist layer so as to have an opening exposing a terminal forming portion of the conductor layer, forming a metal post on the terminal forming portion of the conductor layer using the resist layer as a mask, and the semiconductor wafer Grinding the surface opposite to the side on which the metal post is formed and thinning it to a predetermined thickness, and after removing the resist layer, exposing the top of the metal post Sealed A step of sealing a wafer surface with grease, a step of bonding metal bumps to the top of the metal post, and a step of dividing a semiconductor wafer to which the metal bumps are bonded into each device unit. A method for manufacturing a semiconductor device is provided.

  According to the semiconductor device manufacturing method of the first embodiment, the wafer back surface grinding is performed at a relatively later stage (stage immediately after forming the metal post) in the wafer level package manufacturing process. Since the semiconductor wafer can be processed in a thick state (thick wafer state) until the post is formed, a fatal defect such as that seen in the prior art can be realized in reducing the thickness of the wafer level package. Occurrence of certain “wafer cracking” can be prevented.

  In addition, the wafer surface (the surface on which the pattern is formed) is almost flat due to the surface of the metal post and the surface of the resist layer immediately before performing the wafer back surface grinding process. At this time, it is not necessary to affix an expensive BG tape of a thick film type used in the conventional process, so that a dedicated laminator and a dedicated remover (including a peeling tape) are not required at all. This greatly contributes to the reduction of manufacturing costs.

  Further, according to the modification of the method for manufacturing a semiconductor device according to the first embodiment, the surface of the semiconductor wafer on the side where a plurality of devices are formed has an opening through which the electrode pad of each device is exposed. Forming an insulating film on the insulating film; forming a metal thin film on the entire surface of the insulating film so as to cover the opening from which the electrode pad is exposed; and patterning the metal thin film into a desired shape. Forming a resist layer; forming a rewiring layer on the metal thin film using the resist layer as a mask; and grinding a surface of the semiconductor wafer opposite to the side on which the rewiring layer is formed Then, the step of thinning to a predetermined thickness, the step of forming a metal post on the terminal forming portion of the rewiring layer after removing the resist layer, and the metal thin film exposed on the wafer surface Removing process A step of exposing the top of the metal post to seal the wafer surface with a sealing resin, a step of bonding a metal bump to the top of the metal post, and a semiconductor wafer to which the metal bump is bonded A method of manufacturing a semiconductor device, comprising the step of dividing the device into units.

  Also in the manufacturing method according to this modified embodiment, the wafer back surface grinding process is performed at a relatively later stage in the wafer level package manufacturing process (the stage immediately after the formation of the rewiring layer) until the rewiring layer is formed. Since processing can be performed in a thick wafer state, wafer cracking can be prevented. Further, since the wafer surface is almost flat by the surface of the rewiring layer and the surface of the resist layer immediately before the wafer back surface grinding process is performed, an expensive BG tape is attached to the back surface grinding. This eliminates the need for a dedicated laminator and a dedicated remover (including a peeling tape), thereby contributing to a reduction in manufacturing costs.

  Further, according to the second aspect of the present invention, the step of forming the insulating film on the surface of the semiconductor wafer on the side where a plurality of devices are formed has an opening through which the electrode pad of each device is exposed. And forming a conductor layer patterned in a required shape so as to cover the opening from which the electrode pad is exposed on the insulating film, and a terminal forming portion of the conductor layer is exposed on the conductor layer. Forming a resist layer so as to have an opening to be formed, forming a metal post on a terminal formation portion of the conductor layer using the resist layer as a mask, and forming the metal post of the semiconductor wafer Grinding the surface opposite the side and thinning it to a predetermined thickness, forming a heat-resistant film layer on the thinned surface of the semiconductor wafer, and the resist layer Removed A step of exposing the top of the metal post to seal the wafer surface with a sealing resin, a step of bonding a metal bump to the top of the metal post, and a semiconductor wafer to which the metal bump is bonded, A step of adhering and mounting the surface of the semiconductor wafer on which the film layer is formed on a support member, and then cutting the semiconductor wafer along a line defining a region of each device; And a step of picking up each of the devices with the layer adhered onto the support member.

  According to the method for manufacturing a semiconductor device according to the second embodiment, as in the case of the method for manufacturing a semiconductor device according to the first embodiment described above, a relatively later stage (metal post is used in the wafer level package manufacturing process). The wafer backside grinding is performed at the stage immediately after the formation), and after the wafer backside grinding, before the resist layer is removed, a heat resistant film layer is formed on the backside of the semiconductor wafer. Therefore, after this step, this film layer functions as a reinforcing layer against wafer cracking. That is, almost all processes can be made to flow in a thick wafer state, so that the risk of wafer cracking can be further reduced as compared with the case of the first embodiment described above.

  Further, the film layer formed on the back surface of the semiconductor wafer serves to hold the semiconductor wafer flat so as not to cause warpage of the semiconductor wafer when resin sealing with heat treatment is performed at a later stage. In addition, this film layer is peeled off from the interface of each device while being adhered on the support member at the stage of the final pickup process. In other words, since the film layer formed on the backside of the wafer for warping correction can be finally removed, there is no need to leave it as a permanent film as in the past. As a result, various reliability tests (reliability of adhesion to the wafer) The need to conduct tests etc. is also eliminated.

  According to the third aspect of the present invention, the step of forming the insulating film on the surface of the semiconductor wafer on the side where a plurality of devices are formed has an opening through which the electrode pad of each device is exposed. And forming a conductor layer patterned in a required shape so as to cover the opening from which the electrode pad is exposed on the insulating film, and a terminal forming portion of the conductor layer is exposed on the conductor layer. Forming a resist layer so as to have an opening to be formed; forming a metal post on a terminal forming portion of the conductor layer using the resist layer as a mask; and removing the resist layer; A step of exposing the top and sealing the wafer surface with a sealing resin; a step of removing unnecessary sealing resin protruding from the wafer edge when the wafer surface is sealed with the sealing resin; and the semiconductor Hue Grinding the surface opposite to the side on which the metal post is formed and thinning it to a predetermined thickness, joining a metal bump to the top of the metal post, and the metal And a step of dividing the semiconductor wafer to which the bumps are bonded into the device units.

  According to the method of manufacturing a semiconductor device according to the third embodiment, when resin sealing is performed, the wafer back surface grinding is performed after removing unnecessary resin protruding from the wafer edge portion. Wafer back surface grinding after the resin sealing step, which could not be achieved so far, can be realized without causing wafer cracking due to the protrusion of resin as seen in the art. As a result, almost all processes can be made to flow in a thick wafer state, so that there is a risk of wafer cracking as compared to the case of making a flow in a thick wafer state until the middle of the manufacturing process as in the first embodiment described above. Can be further reduced.

  Furthermore, according to the modification of the semiconductor device manufacturing method according to the third embodiment, the surface of the semiconductor wafer on the side where a plurality of devices are formed has an opening through which the electrode pad of each device is exposed. Forming an insulating film on the insulating film; forming a conductor layer patterned on the insulating film so as to cover the opening from which the electrode pad is exposed; and forming the conductor layer on the conductor layer. Forming a resist layer so that the terminal forming portion of the layer has an exposed opening, forming a metal post on the terminal forming portion of the conductor layer using the resist layer as a mask, and removing the resist layer Then, forming a groove in a ring shape along the wafer edge portion on the surface of the semiconductor wafer where the metal post is formed, and exposing the top of the metal post to form a sealing tree Sealing the wafer surface, grinding the surface of the semiconductor wafer opposite to the side on which the metal post is formed, and thinning it to a predetermined thickness; and There is provided a method for manufacturing a semiconductor device, comprising a step of bonding metal bumps to the top and a step of dividing a semiconductor wafer to which the metal bumps are bonded into each device unit.

  According to the manufacturing method according to this modified embodiment, the resin that diffuses to the outer peripheral portion of the semiconductor wafer when resin sealing is performed can be dropped into a groove formed in a ring shape along the wafer edge portion. The protrusion of the resin to the back surface can be suppressed. As a result, as in the case of the third embodiment described above, the wafers after the resin sealing process that could not be achieved so far without causing the wafer cracking caused by the protrusion of the resin as seen in the prior art. Backside grinding can be realized, and almost all processes can be made to flow in a thick wafer state. Thereby, the risk of wafer cracking can be further reduced.

  Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.

(First embodiment)
FIG. 1 schematically shows a cross-sectional structure of a semiconductor device having a CSP structure according to a first embodiment of the present invention.

  In FIG. 1, 10 indicates a semiconductor device (CSP) according to the present embodiment, 11 indicates a silicon (Si) substrate on which a device is formed, and this silicon substrate 11 cuts (divides) a semiconductor (silicon) wafer described later. ). Further, 12 is an electrode pad defined by a partial region of the wiring pattern formed on the device, and 13 is a passivation as a protective film formed on one surface (upper surface in the illustrated example) of the silicon substrate 11. A film 14 is an insulating film (polyimide resin layer) formed on the passivation film 13, and 15 is a metal thin film (patterned and formed on the insulating film 14 in a required shape so as to cover the opening from which the electrode pad 12 is exposed). (Feeding layer / plating base film), 16 is a redistribution layer formed on the metal thin film 15, 17 is a metal post formed in a terminal formation portion of the rewiring layer 16, and 18 is formed on the top of the metal post 17. The barrier metal layer 19 covers the entire surface of the silicon substrate 11 on which the metal post 17 is formed (however, the metal post 17 (barrier metal The sealing resin layer formed by exposing the top of the layer 18), 20 is a solder bump as an external connection terminal joined to the top of the exposed metal post 17 (barrier metal layer 18), and 21 is a silicon substrate. 11 shows an insulating resin layer for reinforcement for preventing cracking of the wafer formed on the other surface 11 (the lower surface in the illustrated example). The material and thickness of each member will be omitted here, and will be described as appropriate in the manufacturing method described later.

  Hereinafter, the semiconductor device 10 having the CSP structure according to the present embodiment will be described with reference to FIGS. In addition, the cross-sectional structure shown in each figure (except FIG.5 (d)) expands and shows a part (left-side part) of the cross-sectional structure shown in FIG.

  First, in the first step (see FIG. 2A), a wafer 30 in which a plurality of devices are formed is manufactured by a known method. That is, after a required device process is performed on a wafer having a predetermined thickness (for example, a thickness of about 725 μm in the case of an 8-inch diameter wafer), one side of the wafer (in the illustrated example, the upper side) A passivation film 13 as a protective film made of silicon nitride (SiN), phosphorous glass (PSG), or the like is formed on the surface of the aluminum (Al) wiring layer in a predetermined pattern on each device. The portion of the passivation film 13 corresponding to the electrode pad 12 defined by the region is removed (that is, the portion of the passivation film 13 is opened). The opening of the passivation film 13 is performed by, for example, laser processing such as YAG laser or excimer laser. As a result, a wafer 30 whose surface is covered with the passivation film 13 and the electrode pads 12 are exposed as shown in the drawing is produced.

  In the next step (see FIG. 2B), an insulating film 14 is formed on the passivation film 13 of the wafer 30. For example, a photosensitive polyimide resin is applied to the surface of the wafer 30 by photolithography, and a soft baking (pre-baking) treatment of the polyimide resin is performed, followed by exposure and development (polyimide resin layer) using a mask (not shown). Patterning), and a hard bake (post-bake) process is performed to form an insulating film (polyimide resin layer) 14 having an opening VH at a predetermined location as shown in the figure. At this time, the patterning of the polyimide resin layer is performed in accordance with the shape of the electrode pad 12. Therefore, when exposure and development are performed, a portion of the polyimide resin layer 14 corresponding to the electrode pad 12 is removed as shown in the figure, and a via hole (opening VH) reaching the electrode pad 12 is formed.

  In the next step (see FIG. 2C), a metal thin film 15 is formed by sputtering on the entire surface where the insulating film (polyimide resin layer) 14 is formed. The metal thin film 15 has a two-layer structure of a chromium (Cr) layer or a titanium (Ti) layer constituting an adhesion metal layer and a copper (Cu) layer laminated on the adhesion metal layer. The metal thin film 15 can be formed by depositing Cr or Ti on the entire surface by sputtering (adhesive metal layer: Cr layer or Ti layer) and further depositing Cu on the entire surface by sputtering (Cu layer). The metal thin film 15 thus formed functions as a plating base film (feeding layer) in the electrolytic plating process required in the subsequent rewiring forming process and the metal post forming process.

  In the next step (see FIG. 2D), the surface of the metal thin film 15 (Cu layer surface) is dehydrated and baked, a liquid photoresist is applied and dried, and then a mask (not shown) is used. Then, exposure and development (patterning of a photoresist) are performed to form a resist layer R1. The patterning of the photoresist is performed in accordance with the shape of the rewiring pattern formed in the next step.

  In the next step (see FIG. 3A), electrolytic Cu plating is applied to the surface of the metal thin film 15 as a power feeding layer, and a Cu rewiring layer (rewiring pattern) 16 is formed using the patterned resist layer R1 as a mask. Form.

  In the next step (see FIG. 3B), for example, the photoresist (resist layer R1) is stripped and removed using a stripping solution containing an organic solvent.

  In the next step (see FIG. 3C), after cleaning the surface of the metal thin film 15 (Cu layer surface) and the surface of the rewiring layer 16, a photosensitive dry film (thickness of about 100 μm) is applied. Further, exposure and development (dry film patterning) are performed using a mask (not shown) to form a resist layer R2. The patterning of the dry film is performed in accordance with the shape of the metal post formed in the next step.

  In the next step (see FIG. 4A), similarly, the surface of the rewiring layer 16 is subjected to electrolytic Cu plating using the metal thin film 15 as a power feeding layer, and the patterned resist layer R2 is used as a mask. Cu posts (metal posts) 17 are formed in the terminal forming portions. The Cu post 17 has a height of about 100 μm, which is the same as the thickness of the dry film (resist layer R2).

  Further, a barrier metal layer 18 is formed on the top of the Cu post 17 by electrolytic plating. For example, the barrier metal layer 18 is provided with nickel (Ni) plating for improving adhesion on the surface of the Cu post 17 as a power feeding layer, and further palladium (Pd) plating for improving conductivity is applied on the Ni layer. After the application, the Pd layer can be formed by applying gold (Au) plating (Ni / Pd / Au). In this case, the Au layer may be formed directly on the Ni layer without providing the Pd layer (Ni / Au). At this time, the surface on which the rewiring pattern is formed (the upper surface in the illustrated example) is almost flat.

  In the next step (see FIG. 4B), the wafer back surface (the lower surface in the illustrated example) is ground using a known grinding apparatus, and the thickness of the wafer 30 is set to a predetermined thickness (for example, 250 μm). To about 300 μm). At this time, since the pattern surface (upper surface) of the structure manufactured in the previous step is substantially flat, it is easy to chuck the pattern surface side when holding the structure prior to grinding. Become. Therefore, the back surface of the wafer 30 can be ground until it has a predetermined thickness as indicated by an arrow in the figure in such a chucked state.

  Since the pattern surface is in a substantially flat state as described above, it is not necessary to apply a pattern surface protection tape (BG tape) used in the conventional process when grinding the back surface. That is, the surface of the Cu post 17 (barrier metal layer 18) and the surface of the dry film (resist layer R2) serve as a conventional BG tape.

  In the next step (see FIG. 4C), for example, the dry film (resist layer R2) is peeled and removed using an alkaline chemical such as sodium hydroxide (NaOH) or monoethanolamine.

  In the next step (see FIG. 4D), the exposed plating base film (metal thin film 15) is removed by wet etching. That is, the Cu layer in the upper layer portion of the metal thin film 15 is removed with an etching solution that dissolves Cu, and then the adhesion metal layer (Cr layer or Ti layer) in the lower layer portion is removed with an etching solution that dissolves Cr or Ti. As a result, the insulating film (polyimide resin layer) 14 is exposed as shown. Thereafter, predetermined surface cleaning or the like is performed.

  When an etching solution that dissolves Cu is used, Cu constituting the rewiring layer 16 is also removed, and the rewiring pattern appears to be disconnected, but in reality, such a problem does not occur. The reason is that, as described above, the upper layer portion of the metal thin film 15 is formed by sputtering of Cu, so that the film thickness is less than a micron order (about 0.5 μm), whereas the rewiring layer 16 is formed by electrolytic Cu plating. Therefore, even if Cu of the metal thin film 15 is completely removed, only the surface layer portion of the rewiring layer 16 (Cu) is removed. This is because the rewiring pattern does not break.

  In the next step (see FIG. 5A), in order to deal with a wafer crack, an insulating resin layer 21 for reinforcing and correcting wafer warpage after the resin sealing step is formed on the back surface of the wafer 30. To do. As a material of the insulating resin layer 21, for example, a thermosetting epoxy resin, a polyimide resin, a novolac resin, a solder resist, or the like is used. The insulating resin layer 21 is formed by coating and curing these resins and the like. Alternatively, instead of using these resins and the like, a film-like insulating sheet member may be attached.

  In the next step (see FIG. 5B), the entire top surface of the wafer 30 where the Cu post 17 is formed is covered (however, the top of the Cu post 17 (barrier metal layer 18) is exposed). ) Sealing with sealing resin (formation of sealing resin layer 19). This can be done, for example, as follows.

  First, a sealing mold divided into an upper mold and a lower mold is prepared, and this is heated to a predetermined temperature (about 175 ° C.). Next, a resin film is adsorbed on the upper mold, the wafer 30 is mounted in the recess of the lower mold, and a tablet-like thermosetting resin (for example, epoxy resin) having high adhesion as a sealing resin is further formed thereon. Put it on. Then, the thermosetting resin is melted and spread over the entire surface of the wafer by the heat of the sealing mold and the pressure by the press (about 3 minutes), and then the wafer 30 is taken out of the mold. And the process (cure) which hardens a thermosetting resin is performed (within the range of about 1 hour-12 hours). Since the wafer 30 is integrated with the resin film, the resin film is peeled off from the wafer 30. As a result, a wafer 30 is produced in which the surface is covered with the sealing resin layer 19 and the top of the Cu post 17 (barrier metal layer 18) is exposed as shown.

  In the next step (see FIG. 5C), a flux as a surface treatment agent is applied to the top of the exposed Cu post 17 (barrier metal layer 18), and then a solder used as an external connection terminal is applied by a printing method or It is formed by a ball mounting method and fixed by reflowing at a temperature of about 240 ° C. to 260 ° C. (joining of solder bumps 20). Thereafter, the surface is washed to remove the flux.

  In the last step (see FIG. 5D), the wafer 30 (including the insulating film 14, the sealing resin layer 19, and the insulating resin layer 21) to which the solder bumps 20 are bonded in the previous step is supported for dicing. After mounting on a member (not shown), it is cut by a dicer or the like (the dicer blade BL in the example shown) and divided into individual semiconductor chips (devices). As a result, the semiconductor device 10 (FIG. 1) having the CSP structure according to the present embodiment is manufactured.

  As described above, according to the method for manufacturing the semiconductor device 10 having the CSP structure according to the present embodiment, a relatively later stage in the wafer level package manufacturing process (a stage immediately after the Cu post 17 and the barrier metal layer 18 are formed). ) Is performed to back-grind the wafer 30 (see FIG. 4B), and the process up to the step of forming the Cu post 17 and the barrier metal layer 18 (see FIGS. 2A to 4A) is performed. 30 can be processed in a thick state (in this case, a thick wafer state of about 725 μm). Therefore, in realizing thinning of the wafer level package, the occurrence of “wafer cracking” as seen in the prior art is avoided. Can be prevented.

  Further, immediately before the back surface grinding of the wafer 30 (see FIG. 4A), the wafer surface (surface on which the pattern is formed) is the surface of the Cu post 17 (barrier metal layer 18) and the dry film. Since the surface of the (resist layer R2) is almost flat, it is not necessary to affix a thick film type expensive BG tape as used in the conventional process when grinding the back surface of the wafer. As a result, a dedicated laminator and a dedicated remover (including a peeling tape) are not required at all. This makes it possible to reduce manufacturing costs.

  In the embodiment described above, the back surface of the wafer 30 is ground after the formation of the Cu post 17 and the barrier metal layer 18 by electrolytic plating (before the dry film R2 is peeled off) (see FIG. 4B). Of course, the timing of the back grinding is not limited to this point. As is apparent from the gist of the present invention, the point is that the surface is in a substantially flat state immediately before the backside grinding of the wafer 30 and is as late as possible in the manufacturing process of the wafer level package. If it is enough. In consideration of this, for example, the back surface grinding of the wafer 30 may be performed at the stage (see FIG. 3A) after the formation of the rewiring layer 16 (before the removal of the photoresist R1).

  In the above-described embodiment, the passivation film 13 is provided as a protective film on one surface of the wafer in the process of FIG. 2A. However, in some cases, the passivation film 13 is not provided and the subsequent process is performed. The insulating film (polyimide resin layer) 14 formed in (the process of FIG. 2B) may also function as a passivation film. Or conversely, only the passivation film 13 may be provided without providing the insulating film 14.

  In the above-described embodiment, the case where a photosensitive polyimide resin is used as the insulating film 14 formed on the surface of the wafer 30 in the step of FIG. 2B has been described. The material of the insulating film is a photosensitive resin. Of course, the resin is not limited to, for example, a resin such as non-photosensitive polyimide resin or epoxy resin may be used.

  Further, in the above-described embodiment, the insulating resin layer 21 for reinforcing and correcting the warpage of the wafer is formed on the back surface of the wafer in order to deal with a wafer crack in the process of FIG. The resin layer 21 is not necessarily formed, and this step may be omitted depending on circumstances.

(Second Embodiment)
FIG. 6 schematically shows a cross-sectional structure of a semiconductor device having a CSP structure according to the second embodiment of the present invention.

  As illustrated, the semiconductor device 10a according to the second embodiment differs from the semiconductor device 10 according to the first embodiment described above (FIG. 1) in that the back surface of the silicon substrate 11a is exposed. . As described above, in the first embodiment, the reinforcing insulating resin layer 21 formed on the back surface of the wafer in order to deal with a wafer crack in the course of the manufacturing process of the wafer level package is left as it is (FIG. 5). In contrast, in the second embodiment, a film layer is formed on the back surface of the wafer as a countermeasure against wafer cracking in the middle of the manufacturing process, as in the first embodiment. Is peeled off from the back surface of the wafer (the back surface of the silicon substrate 11a) at the final stage of the manufacturing process, as will be described later. As a result, the back surface of the silicon substrate 11a is exposed as shown in FIG. Since the other configuration of the semiconductor device 10a according to the present embodiment is basically the same as the configuration according to the first embodiment (FIG. 1), description thereof is omitted.

  The film layer formed on the backside of the wafer during the manufacturing process does not cause warpage of the wafer when heat treatment such as thermosetting of the sealing resin is performed in addition to the function for reinforcement to prevent wafer cracking. It also has a function (function to correct wafer warpage). The material, thickness, form, and the like of this film layer will be appropriately described in the manufacturing method described later.

  Hereinafter, the semiconductor device 10a having the CSP structure according to the present embodiment will be described with reference to FIGS. In addition, the cross-sectional structure shown in each figure expands and shows a part (left part) of the cross-sectional structure shown in FIG.

  First, in the same manner as the processing performed in the steps of FIGS. 2A to 4A, a wafer 30a whose surface is covered with the passivation film 13 and the electrode pads 12 are exposed is manufactured. An insulating film (polyimide resin layer) 14 is formed on the electrode pad 12, a metal thin film 15 is formed on the electrode pad 12 and the insulating film 14, a Cu rewiring layer 16 is formed on the surface of the metal thin film 15 as a power feeding layer, Using the patterned dry film (resist layer R2) as a mask, a Cu post (metal post) 17 and a barrier metal layer 18 are formed on the terminal formation portion of the rewiring layer 16.

  In the next step (see FIG. 7A), the wafer back surface is ground by a grinding apparatus in the same manner as the processing performed in the step of FIG. 4B, and the thickness of the wafer 30a is set to a predetermined thickness (for example, , About 200 μm).

In the next step (see FIG. 7B), the back surface of the thinned wafer 30a is marked with a CO ₂ laser. That is, information such as a production number and a customer company name is written for each device.

  In the next step (see FIG. 7C), a film layer 22 having a predetermined thickness (for example, about 70 to 290 μm) is formed on the back surface of the wafer 30a in order to deal with wafer cracking and wafer warpage. . In this embodiment, a tape having heat resistance (up to about 240 ° C.) and chemical resistance (hereinafter referred to as “heat-resistant tape” for convenience) is used as the film layer 22. Preferably, a tape based on PET (polyester) having high heat resistance for a die attach film (DAF) process is used. The heat-resistant tape 22 has a multilayer structure in which an adhesive or the like is applied on a base material such as a PET film, and is attached to the back surface of the wafer 30a via the adhesive layer.

  In the present embodiment, the heat-resistant tape 22 is a tape having a property of being cured in response to ultraviolet (UV) irradiation (that is, a type that is peeled off by UV irradiation). The reason why this heat-resistant tape 22 needs “chemical resistance” is that an alkaline chemical solution must be used for peeling off the dry film (resist layer R2) in a later step, and it is exposed. This is because it is necessary to use an acidic or alkaline etching solution to remove the plating base film (metal thin film 15), and it is necessary to withstand these chemical solutions.

  In the next step (see FIG. 8A), the dry film (resist layer R2) is peeled off and exposed in the same manner as the processing performed in the steps of FIGS. 4C and 4D. The film (metal thin film 15) is removed.

  In the next step (see FIG. 8B), the heat-resistant tape 22 attached to the back surface of the wafer 30a is irradiated with ultraviolet rays (UV). This UV irradiation amount is set to an irradiation amount that is sufficient to cure the adhesive layer constituting the heat-resistant tape 22 to some extent and is not so great. The reason for performing UV irradiation at this stage will be described later.

  In the next step (see FIG. 8C), the entire surface on the side where the Cu post 17 of the wafer 30a is formed is covered in the same manner as the processing performed in the step of FIG. Then, the top of the Cu post 17 (barrier metal layer 18) is exposed) and sealed with a sealing resin.

  In the next process (see FIG. 8D), the external connection terminals (solder bumps 20) are joined in the same manner as the process performed in the process of FIG.

  In the next step (see FIG. 9A), the semiconductor wafer 30a to which the solder bumps 20 are bonded is pasted on the dicing tape 41 supported by the dicing frame 40. Adhere the attached side surface and mount. Furthermore, the semiconductor wafer 30a is cut along a line that defines the area of each device by a dicer or the like (in the example shown, a dicer blade BL). At this time, as shown by a broken line in the figure, the cut is made to the middle of the heat-resistant tape 22. As a result, the semiconductor wafer 30a is divided into individual semiconductor chips (devices) with the heat-resistant tape 22 attached.

  In the last step (see FIG. 9B), each semiconductor chip (device) 10a cut and divided in the previous step is picked up. At this time, the heat-resistant tape 22 adhered to the back surface of the semiconductor wafer 30a is completely peeled off from the back surface of the wafer while being adhered on the dicing tape 41. This is because UV irradiation (FIG. 8B) is performed on the heat resistant tape 22 in advance.

  That is, the heat-resistant tape 22 has a multilayer structure in which an adhesive or the like is applied on a base material (PET film) as described above, and when this pickup process is finally performed, the adhesive layer is There is no problem if it is peeled off from the back of the wafer in a state where it is completely attached to the substrate, but if it is subjected to a heat treatment such as cure (FIG. 8C) or reflow (FIG. 8D) before UV irradiation, adhesion will occur. Since the agent layer is altered, a part of the adhesive layer is stuck to the back surface of the wafer during pick-up, and the heat-resistant tape 22 cannot be removed cleanly. Therefore, UV irradiation is performed at a stage before heat treatment as in the present embodiment, and this adhesive layer is cured to some extent. It becomes possible to peel the heat-resistant tape 22 cleanly from the back surface of the wafer in a state where it is completely adhered to the substrate. However, if the UV irradiation amount is excessive, the heat resistant tape 22 may be peeled off at some stage during the pickup process due to some impact or the like. Must be set to

  As described above, according to the method for manufacturing the semiconductor device 10a having the CSP structure according to the second embodiment, a relatively later stage in the wafer level package manufacturing process as in the case of the first embodiment described above. The back grinding of the wafer 30a is performed at the stage (immediately after the formation of the Cu post 17 and the barrier metal layer 18) (see FIG. 7A). Further, after the wafer back grinding processing is performed, a dry film ( Since the resist layer R2) is peeled off and the plating base film (metal thin film 15) is removed by etching, the heat-resistant tape 22 having a predetermined thickness is attached to the back surface of the wafer 30a (FIG. 7C). After this step, the heat-resistant tape 22 functions as a reinforcing film layer against wafer cracking.

That is, according to the second embodiment, all the steps can be made to flow in a thick wafer state except for the step of FIG. 7B (marking by a CO ₂ laser), so the first embodiment described above. Compared with the above case, the risk of wafer cracking can be further reduced.

  Further, the heat-resistant tape 22 attached to the back surface of the wafer 30a is held flat so that the wafer 30a is not warped when heat treatment such as resin sealing and thermosetting (curing) is performed at a later stage. At the same time, the final pick-up process (FIG. 9B) can be completely peeled from the back surface of the wafer. That is, since the heat-resistant tape 22 attached to the back surface of the wafer for warping correction can be finally removed, there is no need to leave it as a permanent film as in the prior art. As a result, it is not necessary to perform various reliability tests (such as an adhesion reliability test with a wafer), and the problem that peeling occurs between the permanent film (film layer) and the chip back surface does not occur.

  In the second embodiment described above, the heat-resistant tape 22 is described as an example in which a type that peels after applying UV (so-called “UV peeling type”) is used. Of course, the form of the heat-resistant tape is not limited to this. For example, a type that is heated and peeled off without applying UV (so-called “thermal peeling type”) may be used. This has an advantage that the cost is lower than that of the UV peeling type.

  The heat-peeling type tape can be peeled off by applying a heat of about 50 to 60 ° C., for example, to reduce its adhesive strength and further applying a peeling force. It should be noted here that the film cannot be peeled off simply by applying heat. That is, at the stage after the heat-peeling type tape is applied, curing is performed at a higher temperature of about 175 ° C. (FIG. 8C), and reflow is performed at a temperature of about 240 ° C. to 260 ° C. (FIG. 8 ( d)), but the tape is not peeled off depending on only the temperature condition at this stage, and the tape (figure 9b) attached to the wafer in the stage of performing the final pickup process (FIG. 9B). The tape can be peeled from the back surface of the wafer by heating the heat-peeling type tape to a predetermined temperature (about 50 to 60 ° C.) and applying a force for peeling each device from the tape. For this reason, a heating mechanism for heating to the predetermined temperature at the stage of the pickup process is required.

(Third embodiment)
As described above, in order to avoid wafer cracking due to processing in a thin wafer state, it is desirable to perform wafer back grinding at a later stage as much as possible. If it is performed, as described in relation to the problems of the prior art, there is a risk that wafer cracking due to the protrusion of the mold resin may occur. 10 and 11 show a method for eliminating such inconvenience.

  FIG. 10 shows a part of the manufacturing process of the semiconductor device according to the third embodiment of the present invention, and FIG. 11 is for explaining the processing of the wafer edge portion performed in the process of FIG. FIG.

  Prior to the processing of each step shown in FIG. 10, first, the same processing as that performed in the steps of FIGS. 2 (a) to 5 (a) is performed. However, the wafer back surface grinding process (FIG. 4B) and the insulating resin layer 21 forming process (FIG. 5A) are excluded. Then, in the process of FIG. 10A, the entire surface of the wafer 30 on which the Cu post 17 is formed is covered in the same manner as the process performed in the process of FIG. The top 17 of the post 17 (barrier metal layer 18) is exposed) and sealed with a sealing resin. At this time, as shown in the figure, the resin (19) diffuses to the outer peripheral portion of the wafer 30, and the diffused resin protrudes to the wafer edge portion and goes around the wafer back surface. If the wafer back surface grinding process is performed in this state, there is a possibility that wafer cracking may occur as described above.

  Therefore, in the next step (see FIG. 10B), unnecessary resin that protrudes from the wafer edge portion is cut (removed) by round cutting (also referred to as “circular dicing method”) using a dicer (blade BL). ) Specifically, as shown in FIG. 11, first, the blade BL is lowered to a position offset by a predetermined radius from the center of the wafer 30 (see FIG. 11A), and the height of the blade BL is fixed. The portion of the wafer 30 at that position can be cut by rotating a chuck table (not shown) that adsorbs the wafer 30 (see FIG. 5B). Thereby, the unnecessary resin layer 19 in the wafer edge portion is removed.

  After removing the unnecessary resin layer 19 protruding from the wafer edge portion in this way, in the next step (see FIG. 10C), the grinding apparatus is performed in the same manner as the processing performed in the step of FIG. By grinding the back surface of the wafer, the wafer 30 is thinned to a predetermined thickness. Thereafter, although not particularly illustrated, solder bumps 20 are bonded to the top of the exposed Cu posts 17 (barrier metal layer 18), and the wafer 30 (including the insulating film 14 and the sealing resin layer 19) is diced. And divided into individual semiconductor chips (devices).

  As described above, according to the semiconductor device manufacturing method according to the third embodiment, when resin sealing is performed at a stage close to the final stage of the manufacturing process of the wafer level package, an unnecessary resin layer that protrudes from the wafer edge portion. Since the wafer back surface grinding process is performed after removing 19, the resin sealing process which has not been achieved so far without causing the wafer cracking caused by the protrusion of the resin as seen in the prior art. Subsequent wafer back surface grinding processing can be realized. As a result, almost all processes can be made to flow in a thick wafer state, so that the risk of wafer cracking can be reduced as compared to the case of making the wafer flow in a thick wafer state until the middle of the manufacturing process as in the first embodiment. This can be further reduced.

  In the third embodiment described above, the unnecessary unnecessary resin layer 19 is cut as a method of solving the problem of the resin protrusion at the wafer edge portion that occurs when the resin sealing is performed prior to the wafer back surface grinding process. Although the method of (removing) has been described as an example, it is needless to say that the method of solving the problem of the resin protrusion at the wafer edge portion is not limited to this. For example, a method may be adopted in which resin diffused in the outer peripheral portion of the wafer during resin sealing stays at the wafer edge portion and prevents it from entering the wafer back surface. FIG. 12 illustrates the method in that case.

  In the method shown in FIG. 12, prior to the process of the illustrated process, first, the same process as the process performed in the process of FIGS. 2A to 5A is performed. However, the wafer back surface grinding process (FIG. 4B) and the insulating resin layer 21 forming process (FIG. 5A) are excluded. 12A, a U-shaped groove G is formed in a ring shape along the wafer edge portion on the surface of the wafer 30 on which the Cu post 17 (barrier metal layer 18) is formed. This U-shaped groove G can be formed by using a circular dicing method as exemplified in FIG. 11 together with profile processing performed utilizing the shape of the blade BL of the dicer. In the example shown in the figure, it is a U-shaped groove G, but the cross-sectional shape of the groove to be formed is not limited to the “U-shaped”, for example, a V-shaped shape, a rectangular shape, and other shapes. Also good.

  After the U-shaped groove G is formed in the wafer edge portion in this way, in the next process (see FIG. 12B), the Cu post of the wafer 30 is performed in the same manner as the process performed in the process of FIG. Sealing is performed with a sealing resin 19 so as to cover the entire surface on the side where 17 is formed (however, the top of the Cu post 17 (barrier metal layer 18) is exposed). At this time, as shown in the drawing, the resin 19 diffused to the outer peripheral portion of the wafer 30 is dropped into a U-shaped groove G formed in the wafer edge portion. Thereafter, although not particularly illustrated, the back surface of the wafer is ground by a grinding device to thin the wafer 30 to a predetermined thickness, and the solder bumps 20 are joined to the top of the exposed Cu post 17 (barrier metal layer 18). After that, the wafer 30 (including the insulating film 14 and the sealing resin layer 19) is diced and divided into individual semiconductor chips (devices).

  As described above, according to the embodiment shown in FIG. 12, since the resin 19 diffused to the outer peripheral portion of the wafer 30 at the time of resin sealing is dropped into the U-shaped groove G of the wafer edge portion, the resin sticks out to the back surface of the wafer. Can be suppressed. As a result, as in the case of the third embodiment described above, without causing the wafer cracking due to the protrusion of the resin as seen in the prior art, the resin sealing process and the subsequent steps that could not be achieved so far Wafer backside grinding processing can be realized, and almost all processes can be made to flow in a thick wafer state. As a result, the risk of wafer cracking can be further reduced.

It is sectional drawing which shows typically the structure of the semiconductor device of the CSP structure which concerns on the 1st Embodiment of this invention. FIG. 3 is a cross-sectional view showing a manufacturing process (No. 1) of the semiconductor device of FIG. 1; FIG. 3 is a cross-sectional view showing a manufacturing process (part 2) subsequent to the manufacturing process of FIG. 2; FIG. 4 is a cross-sectional view showing a manufacturing process (part 3) following the manufacturing process of FIG. 3; FIG. 5 is a cross-sectional view (partially a perspective view) showing a manufacturing process (part 4) following the manufacturing process of FIG. 4; It is sectional drawing which shows typically the structure of the semiconductor device of the CSP structure which concerns on the 2nd Embodiment of this invention. FIG. 7 is a cross-sectional view showing a manufacturing process (No. 1) of the semiconductor device of FIG. 6; It is sectional drawing which shows the manufacturing process (the 2) following the manufacturing process of FIG. It is sectional drawing which shows the manufacturing process (the 3) following the manufacturing process of FIG. It is sectional drawing which shows a part of manufacturing process of the semiconductor device which concerns on the 3rd Embodiment of this invention. It is a figure for demonstrating the process of a wafer edge part performed at the process (b) of FIG. It is sectional drawing which shows a part of manufacturing process which concerns on the modification of embodiment of FIG.

Explanation of symbols

10, 10a ... Semiconductor device (CSP),
11, 11a ... Semiconductor substrate (silicon substrate),
12 ... Electrode pad (a part of the wiring layer of each device),
13 ... Passivation film (SiN layer or PSG layer),
14: Insulating film (polyimide resin layer),
15 ... Metal thin film (feed layer / plating base film),
16 ... conductor layer (redistribution layer / redistribution pattern),
17 ... Metal post (Cu post),
18 ... barrier metal layer,
19 ... sealing resin layer,
20: External connection terminals (solder bumps),
21 ... insulating resin layer,
22 ... Film layer (heat-resistant tape),
30, 30a ... Semiconductor wafer (silicon wafer),
40 ... Dicing frame,
41 ... Support member (dicing tape),
BL ... Dicer blade,
G ... U-shaped groove,
R1, R2 ... resist layer (plating resist),
VH: Opening (via hole).

Claims (10)

Forming an insulating film on the surface of the semiconductor wafer on the side where a plurality of devices are formed so as to have an opening through which the electrode pad of each device is exposed;
Forming a conductor layer patterned into a required shape on the insulating film so as to cover the opening from which the electrode pad is exposed;
Forming a resist layer on the conductor layer so as to have an opening exposing a terminal forming portion of the conductor layer;
Forming a metal post on a terminal forming portion of the conductor layer using the resist layer as a mask;
Grinding the surface of the semiconductor wafer opposite to the side on which the metal post is formed, and thinning it to a predetermined thickness;
After removing the resist layer, exposing the top of the metal post and sealing the wafer surface with a sealing resin;
Bonding a metal bump to the top of the metal post;
Dividing the semiconductor wafer to which the metal bumps are bonded into the device units. Forming an insulating film on the surface of the semiconductor wafer on the side where a plurality of devices are formed so as to have an opening through which the electrode pad of each device is exposed;
Forming a metal thin film on the entire surface of the insulating film so as to cover the opening from which the electrode pad is exposed;
Forming a resist layer patterned into a required shape on the metal thin film;
Forming a rewiring layer on the metal thin film using the resist layer as a mask;
Grinding the surface of the semiconductor wafer opposite to the side on which the rewiring layer is formed, and thinning the surface to a predetermined thickness;
After removing the resist layer, forming a metal post in the terminal formation portion of the rewiring layer;
Removing the metal thin film exposed on the wafer surface;
Exposing the top of the metal post and sealing the wafer surface with a sealing resin;
Bonding a metal bump to the top of the metal post;
Dividing the semiconductor wafer to which the metal bumps are bonded into the device units.   3. The semiconductor device according to claim 1, further comprising a step of forming an insulating resin layer on the thinned surface of the semiconductor wafer immediately before the step of sealing the wafer surface with the sealing resin. Manufacturing method. Forming an insulating film on the surface of the semiconductor wafer on the side where a plurality of devices are formed so as to have an opening through which the electrode pad of each device is exposed;
Forming a conductor layer patterned into a required shape on the insulating film so as to cover the opening from which the electrode pad is exposed;
Forming a resist layer on the conductor layer so as to have an opening exposing a terminal forming portion of the conductor layer;
Forming a metal post on a terminal forming portion of the conductor layer using the resist layer as a mask;
Grinding the surface of the semiconductor wafer opposite to the side on which the metal post is formed, and thinning it to a predetermined thickness;
Forming a heat-resistant film layer on the thinned surface of the semiconductor wafer;
After removing the resist layer, exposing the top of the metal post and sealing the wafer surface with a sealing resin;
Bonding a metal bump to the top of the metal post;
After the semiconductor wafer to which the metal bumps are bonded is mounted with the surface of the semiconductor wafer on which the film layer is formed adhered on a support member, the semiconductor wafer is mounted along a line that defines the area of each device. Cutting the semiconductor wafer;
And picking up each of the devices while the film layer is adhered onto the support member. In the step of forming the film layer, as the film layer, a heat-resistant tape having a property of curing in response to ultraviolet irradiation is used.
5. The method according to claim 4, further comprising: irradiating the heat resistant tape with a predetermined amount of ultraviolet light after removing the resist layer and before sealing the wafer surface with the sealing resin. 6. A method for manufacturing a semiconductor device. In the step of forming the film layer, as the film layer, using a heat-resistant tape having a property that the adhesive strength is reduced when heated,
5. The manufacturing of a semiconductor device according to claim 4, wherein in the step of picking up each device, the heat-resistant tape is heated to a predetermined temperature, and a force for peeling the devices from the heat-resistant tape is applied. Method. Forming an insulating film on the surface of the semiconductor wafer on the side where a plurality of devices are formed so as to have an opening through which the electrode pad of each device is exposed;
Forming a conductor layer patterned into a required shape on the insulating film so as to cover the opening from which the electrode pad is exposed;
Forming a resist layer on the conductor layer so as to have an opening exposing a terminal forming portion of the conductor layer;
Forming a metal post on a terminal forming portion of the conductor layer using the resist layer as a mask;
After removing the resist layer, exposing the top of the metal post and sealing the wafer surface with a sealing resin;
Removing unnecessary sealing resin protruding from the wafer edge when the wafer surface is sealed with the sealing resin;
Grinding the surface of the semiconductor wafer opposite to the side on which the metal post is formed, and thinning it to a predetermined thickness;
Bonding a metal bump to the top of the metal post;
Dividing the semiconductor wafer to which the metal bumps are bonded into the device units. Forming an insulating film on the surface of the semiconductor wafer on the side where a plurality of devices are formed so as to have an opening through which the electrode pad of each device is exposed;
Forming a conductor layer patterned into a required shape on the insulating film so as to cover the opening from which the electrode pad is exposed;
Forming a resist layer on the conductor layer so as to have an opening exposing a terminal forming portion of the conductor layer;
Forming a metal post on a terminal forming portion of the conductor layer using the resist layer as a mask;
After removing the resist layer, forming a groove in a ring shape along the wafer edge portion on the surface of the semiconductor wafer where the metal post is formed;
Exposing the top of the metal post and sealing the wafer surface with a sealing resin;
Grinding the surface of the semiconductor wafer opposite to the side on which the metal post is formed, and thinning it to a predetermined thickness;
Bonding a metal bump to the top of the metal post;
Dividing the semiconductor wafer to which the metal bumps are bonded into the device units.   9. The semiconductor device according to claim 1, wherein in the step of forming the metal post, a barrier metal layer is further formed on the top of the metal post after the metal post is formed. Manufacturing method.   9. The method of manufacturing a semiconductor device according to claim 1, wherein in the step of forming the insulating film, the opening is formed by photolithography.

Images