JP4619308B2 - Semiconductor device manufacturing method and supporting tape - Google Patents

Description

  The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device using a support. The present invention also relates to a support tape used when the semiconductor substrate and the support are peeled off.

  In recent years, in order to increase the mounting density, it is required to reduce the thickness and size of a semiconductor chip. In order to satisfy this requirement, it is necessary to make a semiconductor substrate such as silicon thinner. However, if the semiconductor substrate becomes thin, warping or breakage due to a decrease in strength occurs in the manufacturing process, making conveyance impossible. Therefore, it is generally performed to reduce the thickness by attaching a support such as a glass substrate or a protective tape to one surface of the semiconductor substrate and grinding the surface where the support is not attached with a grinder or the like. Yes.

  17 and 18 are cross-sectional views schematically showing a step of removing the support in the conventional method for manufacturing a semiconductor device. As shown in FIG. 17, a pad electrode 101 made of aluminum or the like is formed on the surface of a semiconductor substrate 100 made of silicon or the like via a first insulating film 102 such as a silicon oxide film. A part of the pad electrode 101 is covered with a passivation film 103 such as a silicon nitride film. Further, a glass substrate 104 as a support is attached to the surface of the semiconductor substrate 100 via an adhesive layer 105. Here, it is assumed that a plurality of through holes 106 for supplying a dissolving agent for the adhesive layer 105 are formed in the glass substrate 104.

  In addition, a via hole 107 that penetrates the semiconductor substrate 100 and reaches the pad electrode 101 from its back surface is formed. A second insulating film 108 such as a silicon oxide film is formed on the side wall of the via hole 107 and the back surface of the semiconductor substrate 100.

  Further, a barrier layer 109, a seed layer 110, and a through electrode 111 electrically connected to the pad electrode 101 are formed in the via hole 107, and a wiring layer connected to the through electrode 111 is formed on the back surface of the semiconductor substrate 100. 112 extends. A protective layer 113 is formed to cover the second insulating film 108, the wiring layer 112, and the through electrode 111. A predetermined region of the protective layer 113 is opened, and a ball-like conductive terminal 114 is formed in the opening. Yes.

  Then, as shown in FIG. 18, a dissolving agent for the adhesive layer 105 is supplied from the through hole 106, and the glass substrate 104 is peeled and removed. Then, it divides | segments into each semiconductor chip by cutting along the dicing line DL using a dicing blade or a laser.

The technology described above is described in the following patent documents.
JP 2005-191550 A JP 2001-185519 A

  However, in the above-described conventional method for manufacturing a semiconductor device, a fine through hole 106, a groove, or the like as a path through which the dissolving agent for the adhesive layer 105 can be supplied is formed on the glass substrate 104 as a support. There is a problem that becomes complicated and expensive.

  In addition, since the support in which the dissolving agent supply path is formed is used in this way, in the course of a series of manufacturing processes, outgas is generated from the place where the path is formed, or a corrosive substance enters the semiconductor device. Reliability may be adversely affected.

  Therefore, an object of the present invention is to reduce the manufacturing cost, improve the reliability, and the yield of a semiconductor device using a support. Furthermore, it aims at providing the manufacturing method of the semiconductor device suitable for thickness reduction and size reduction of a semiconductor device.

  The main features of the present invention are as follows. That is, the method for manufacturing a semiconductor device according to the present invention includes a step of attaching a first support to the first main surface of a semiconductor substrate having a first main surface and a second main surface through an adhesive layer. Removing a part of the semiconductor substrate to form an opening for exposing the adhesive layer from the second main surface of the semiconductor substrate; and after forming the opening, a solvent for the adhesive layer is formed. A step of attaching a second support that can be passed over the second main surface of the semiconductor substrate, and supplying the dissolving agent to the adhesive layer through the second support and the opening. And removing the first support from the semiconductor substrate.

  The method for manufacturing a semiconductor device according to the present invention is characterized in that a dissolving agent supply hole is formed in the second support.

  In addition, the support tape of the present invention has a second main surface of the semiconductor substrate before peeling the semiconductor substrate and the support attached to the first main surface of the semiconductor substrate via an adhesive layer. A support tape for fixing individual semiconductor chips after being peeled off and the support is peeled off, wherein the adhesive layer dissolving agent can pass from the front surface to the back surface.

  Further, the support tape of the present invention is characterized in that a dissolving agent supply hole penetrating from the front surface to the back surface is provided.

  According to the semiconductor device manufacturing method of the present invention, it is possible to prevent the influence of outgas generation and the entry of corrosive substances due to the presence of the dissolution agent supply path in the manufacturing process, so that a highly reliable semiconductor device can be obtained. Can be manufactured.

  Further, according to the support tape of the present invention, the dissolving agent can be supplied from the support tape side to the adhesive layer formed between the semiconductor substrate and the support, and the support is peeled off from the semiconductor substrate. Can do. At the same time, when the support is peeled off, the individual semiconductor chips already divided can be fixed so as not to fall apart.

  Next, embodiments of the present invention will be described with reference to the drawings. 1 to 13 are cross-sectional views shown in the order of manufacturing steps.

  First, as shown in FIG. 1, a semiconductor substrate 1 having an electronic device (not shown) (for example, a light receiving element such as a CCD or an infrared sensor, a light emitting element, or other semiconductor elements) formed on its surface is prepared. The semiconductor substrate 1 has a diameter of, for example, 8 inches (200 mm) and a thickness of about 300 μm to 700 μm. Then, a first insulating film 2 (for example, a silicon oxide film or a BPSG film formed by a thermal oxidation method or a CVD method) is formed on the surface of the semiconductor substrate 1 to a thickness of 2 μm, for example.

  Next, a metal layer such as aluminum (Al), aluminum alloy, or copper (Cu) is formed by sputtering, plating, or other film formation methods, and then the metal layer is etched using a resist layer (not shown) as a mask. The pad electrode 3 is formed on the first insulating film 2 to a thickness of 1 μm, for example. The pad electrode 3 is electrically connected to an electronic device on the semiconductor substrate 1 and its peripheral elements.

  Next, a passivation film 4 (for example, a silicon nitride film formed by a CVD method) that covers a part of the pad electrode 3 is formed on the surface of the semiconductor substrate 1. The first insulating film 2 and the passivation film 4 do not have to be formed on the boundaries of the individual semiconductor chips, but may be formed on the boundaries from the viewpoint of using as a stopper layer as will be described later. .

  Next, a support 6 is bonded onto the surface of the semiconductor substrate 1 including the pad electrode 3 via an adhesive layer 5 such as epoxy resin, resist, or acrylic.

  The support 6 may be, for example, a film-like protective tape, but is a rigid substrate such as glass, quartz, ceramic, plastic, metal, resin, etc., which firmly supports the semiconductor substrate 1 to be thinned, It is preferable in automating the conveyance not depending on.

  It is not necessary to process and form a path (through hole, groove, etc.) for supplying the dissolving agent for the adhesive layer 5 to the support 6. Accordingly, it is possible to prevent adverse effects such as outgas generation and invasion of corrosive substances, which are conventionally caused by the existence of the path, in subsequent processes. In addition, since it is not necessary to process and form the dissolving agent supply path with respect to the support 6, the cost for the support 6 can be reduced.

  The support 6 has a function of supporting the semiconductor substrate 1 and protecting the element surface. The support 6 is the same size as the diameter of the semiconductor substrate 1 or slightly larger (1 mm to 4 mm).

  Next, back grinding is performed on the back surface of the semiconductor substrate 1 using a back surface grinding device (a grinder or an etching device), and the thickness of the semiconductor substrate 1 is ground to a predetermined thickness (for example, about 50 μm).

  Next, as shown in FIG. 2, a resist layer 7 is selectively formed on the back surface of the semiconductor substrate 1. The resist layer 7 has an opening at a position corresponding to the pad electrode 3 on the back surface of the semiconductor substrate 1. Next, the semiconductor substrate 1 is etched using the resist layer 7 as a mask. By this etching, a via hole 8 that penetrates the semiconductor substrate 1 at a position corresponding to the pad electrode 3 from the back surface to the front surface is formed. The first insulating film 2 is exposed at the bottom of the via hole 8. Further, etching is performed using the resist layer 7 as a mask, and the exposed first insulating film 2 is removed. Note that the etching process of the first insulating film 2 may be performed simultaneously with other etching processes without being performed at this stage.

  Although not shown, the via hole 8 may not penetrate through the semiconductor substrate 1 from the back surface to the front surface, and may have a bottom portion in the middle of the semiconductor substrate 1.

  Next, after the resist layer 7 is removed, as shown in FIG. 3, a second insulating film 9 (for example, a silicon oxide film or silicon formed by a CVD method is formed on the entire back surface of the semiconductor substrate 1 including the inside of the via hole 8. Nitride film) is formed.

  Next, as shown in FIG. 4, a resist layer 10 is formed on the second insulating film 9. Next, as shown in FIG. 5, the second insulating film 9 at the bottom of the via hole 8 is removed by etching using the resist layer 10 as a mask. The second insulating film 9 can also be etched without a mask by utilizing the tendency that the back surface of the semiconductor substrate 1 is thickest and is formed thinner toward the side wall and bottom of the via hole 8. . Etching without a mask can streamline the manufacturing process.

  Next, as shown in FIG. 6, a barrier layer 15 is formed on the second insulating film 9 on the back surface of the semiconductor substrate 1 including the via hole 8. Further, a seed layer 16 is formed on the barrier layer 15. Here, the barrier layer 15 includes, for example, a titanium (Ti) layer, a titanium nitride (TiN) layer, a tantalum nitride (TaN) layer, and the like. The seed layer 16 serves as an electrode for plating a wiring layer 18 described later, and is made of a metal such as copper (Cu). These layers are formed by sputtering, CVD, or other film forming methods.

  Next, on the seed layer 16 including the inside of the via hole 8, a through electrode 17 made of copper (Cu) and a wiring layer 18 continuously connected thereto are formed by, for example, electrolytic plating. The through electrode 17 and the wiring layer 18 are electrically connected to the pad electrode 3 exposed at the bottom of the via hole 8 through the barrier layer 15 and the seed layer 16.

  The through electrode 17 may not be completely filled in the via hole 8, but may be incompletely filled as shown in FIG. According to such a configuration, the conductive material necessary for forming the through electrode 17 and the wiring layer 18 can be saved, and the through electrode 17 and the wiring layer 18 can be formed in a shorter time than when completely filled. This has the advantage of increasing throughput.

  Next, as shown in FIG. 7, a resist layer 19 for forming a wiring pattern is selectively formed on the wiring layer 18 on the back surface of the semiconductor substrate 1. Next, unnecessary portions of the wiring layer 18 and the seed layer 16 are removed by etching using the resist layer 19 as a mask. By this etching, the wiring layer 18 is patterned into a predetermined wiring pattern. Subsequently, the barrier layer 15 formed on the back surface of the semiconductor substrate 1 is selectively etched and removed using the wiring layer 18 as a mask.

  The formation of the barrier layer 15, the seed layer 16, the through electrode 17, and the wiring layer 18 is not limited to the above process. For example, a resist layer or the like is formed in a region on the back surface of the semiconductor substrate 1 where the barrier layer 15 or the wiring layer 18 is not formed, and then the barrier layer 15 or the wiring layer 18 or the like is formed in a region not covered with the resist layer or the like. The patterning may be performed by forming. In this step, the resist layer 19 is not necessary.

  Next, as shown in FIG. 8, a protective layer 20 made of an organic material such as a solder resist or an inorganic material such as a silicon nitride film is formed on the back surface of the semiconductor substrate 1. In the protective layer 20, a conductive terminal forming region is opened, an electrode connection layer (not shown) made of nickel and gold is formed on the wiring layer 18 exposed through the opening, and then solder is screen printed, and the solder is heat-treated. The ball-shaped conductive terminal 21 is formed by reflowing. The conductive terminal 21 can be formed by a so-called dispenser method (coating method) in which a ball-shaped terminal made of solder or the like is applied using a dispenser, an electrolytic plating method, or the like.

  Next, as shown in FIG. 9, a part of the semiconductor substrate 1 is removed, and an opening 22 for exposing a part of the adhesive layer 5 is formed. Specifically, for example, as shown in FIG. 9A, the opening 22 is formed with a dicing blade, a laser beam, or the like along a predetermined dicing line.

  Alternatively, as shown in FIG. 9B, a resist layer 23 is formed on the back surface of the semiconductor substrate 1, and using this as a mask, the protective layer 20, the second insulating film 9, the semiconductor substrate 1, and the first insulating film 2 are formed. , And the passivation film 4 are sequentially removed by etching to form the opening 22.

  In the case of etching, the cut surface is not subjected to mechanical stress as compared with the case of using a dicing blade, so that there is an advantage that the cut surface can be formed smoothly and cracks and chipping can be prevented. Therefore, it is preferable to form the opening 22 by etching from the viewpoint of preventing a mechanical defect and manufacturing a semiconductor device with high reliability and yield.

  In addition, without using the resist layer 23 as a mask, a predetermined opening can be provided in the protective layer 20 and the etching can be performed using this as a mask. In this case, the resist layer 23 is removed after the etching. However, if the adhesive layer 5 is exposed, the adhesive layer 23 may be removed when the resist layer 23 is removed depending on the material of the resist layer 23 and the adhesive layer 5. 5 is also removed at the same time. Therefore, from the viewpoint of preventing the adhesive layer 5 from being removed at the same time when the resist layer 23 is removed, the first insulating film 2 and the passivation film 4 are not etched at the time of etching using the resist layer 23 as a mask. To leave. Then, when removing the resist layer 23, the adhesive layer 5 can be protected by using these films (the first insulating film 2 and the passivation film 4) as a stopper layer. Then, after the resist layer 23 is removed, the first insulating film 2 and the passivation film 4 are removed by a method such as wet etching, so that the adhesive layer 5 can be partially exposed.

  Moreover, the exposure method of the contact bonding layer 5 is not restricted to this. For example, before attaching the support 6 to the semiconductor substrate 1 in FIG. 1, an opening is provided in advance on the surface side of the semiconductor substrate 1 by a dicing blade or etching in a region where the opening 22 is to be formed (hereinafter referred to as the first for convenience). Of the opening 22a). Then, after the protective layer 20 and the conductive terminal 21 are formed, the second opening 22b is formed by removing the semiconductor substrate 1 from the back side of the semiconductor substrate 1 by a dicing blade or etching, and the first opening 22a. It is also possible to form one opening 22 as a whole as shown in FIG. In FIG. 10, the first opening 22a is larger than the opening of the second opening 22b, but may be the opposite or the same size.

  Although the semiconductor chip can be divided by dicing in a separate process after partially exposing the adhesive layer 5, it is preferable to perform the two processes simultaneously. That is, by forming the opening 22 along the dicing line DL, the step of exposing the adhesive layer 5 and the division of the semiconductor chip can be performed simultaneously, and the manufacturing process is simplified and the cost can be reduced.

  Next, as shown in FIGS. 11 and 12, a support tape 25 provided with a plurality of fine holes (dissolving agent supply holes 24) is pasted so that at least the entire back side of the semiconductor substrate 1 is covered. . FIG. 12 is a schematic plan view of a state in which the support tape 25 is attached via an adhesive layer (not shown).

  The support tape 25 has a role of fixing the already divided semiconductor chips so that they do not fall apart when the support 6 is peeled from the semiconductor substrate 1. Further, the dissolving agent supply hole 24 passes through the support tape 25. Therefore, the support tape 25 also has a role for supplying the dissolving agent to the adhesive layer 5 through the opening 22 from the support tape 25 side.

  Further, the dissolving agent supply hole 24 may not be a clear hole as long as the dissolving agent of the adhesive layer 5 passes through the inside of the support tape 25 and reaches the opening 22 and further reaches the adhesive layer 5. In other words, the material and configuration of the support tape 25 here are not limited as long as the dissolving agent of the adhesive layer 5 can pass therethrough and has a function of fixing individual semiconductor chips after the support 6 is peeled off. It is.

  The solubilizer supply hole 24 can be formed by, for example, using a drilling device having a plurality of protrusions corresponding to the size of the hole and mechanically pressing the protrusions against the support tape 25 having no holes. .

  Although depending on the size of each individual semiconductor chip to be singulated, the size of the solvent supply hole 24 for one semiconductor chip is preferably about one third of the chip size as a whole or as a single unit. . Therefore, one solubilizer supply hole 24 may be formed so as to correspond to one chip, or a plurality of solubilizer supply holes 24 may be formed so as to correspond to one chip. The support tape 25 is made of, for example, polyimide or polyolefin as a base material, and is made of an acrylic or silicone material as an adhesive layer.

  Next, a dissolving agent 26 (for example, alcohol or acetone) is poured from the upper part of the support tape 25 and the side wall side of the semiconductor substrate 1. Specifically, for example, the support tape 25 is dipped in a container filled with the dissolving agent 26. Thus, the dissolving agent 26 passes through the support tape 25, travels through the interface between the protective layer 20 and the support tape 25, and is supplied to the adhesive layer 5 exposed through the opening 22. The adhesive strength of gradually decreases.

  As shown in FIGS. 11 and 12, the dissolving agent 26 is also supplied to the adhesive layer 5 from the side wall side of the semiconductor substrate 1. Since it takes a long time for the dissolving agent 26 from the side wall side of the semiconductor substrate 1 to reach the vicinity of the center of the semiconductor substrate 1, relatively many dissolving agent supply holes 24 are provided in the vicinity of the center of the semiconductor substrate 1. It is preferable to shorten the time required for the peeling process of the support 6.

  Then, as shown in FIG. 13, the support 6 is peeled from the semiconductor substrate 1. Thus, by supplying the dissolving agent 26 to the adhesive layer 5 and peeling the support 6, the load at the time of peeling the support 6 is reduced, and the problem that mechanical defects occur in the semiconductor device is reduced. Can be made. The support 6 can be recovered and reused.

  Next, individual semiconductor chips are picked up from the support tape 25. Specifically, for example, the support tape 25 can be peeled off by applying heat or UV irradiation. Here, since the support tape 25 is provided with the dissolving agent supply holes 24, the bonding area is smaller than that of a tape having no holes. Therefore, the load on the semiconductor chip when the support tape 25 is peeled off can be reduced, and mechanical defects of the semiconductor chip are prevented.

  Through the above steps, a chip size package type semiconductor device in which wiring from the pad electrode 3 formed on the front surface of the semiconductor substrate 1 to the conductive terminal 21 provided on the back surface is completed. When incorporating this semiconductor device into an electronic device, the conductive terminal 21 is electrically connected to an external circuit by being mounted on a wiring pattern on a circuit board.

  In addition, when the semiconductor device manufactured by the above process is used for stacking with another semiconductor device, the device such as an electronic device formed on the back surface of the semiconductor substrate 1 is then protected with a protective tape or the like. An electrode connection layer 30 made of nickel (Ni), gold (Au) or the like is formed on the pad electrode 3.

  Then, as shown in FIG. 14, the pad electrode 3 of one semiconductor device and the conductive terminal 21 of the other semiconductor device are connected via the electrode connection layer 30. The electrode connection layer 30 is necessary because the pad electrode 3 made of aluminum or the like is difficult to be joined to the conductive terminal 21 made of solder or the like, and the material of the conductive terminal 21 flows into the opposing pad electrode 3 side during lamination. It is because of preventing it. FIG. 14 shows a configuration in which the wiring layer 18 is not extended on the back surface of the semiconductor substrate 1.

  As described above, when the completed semiconductor device is used for stacking, the electrode connection layer 30 necessary for stacking is generally formed after completion. However, since the semiconductor substrate 1 has already been thinned, there is a problem that there is a high possibility that a mechanical defect will occur during conveyance such as handling. Moreover, since it is a process only with respect to the pad electrode 3 of the semiconductor substrate 1 surface, it is necessary to protect another surface in the said process. This complicates the manufacturing process and increases the manufacturing cost.

  Therefore, when manufacturing a semiconductor device for stacking, the electrode connection layer 30 is processed and formed on the pad electrode 3 before the support 6 is attached to the semiconductor substrate 1 and before the semiconductor substrate 1 is thinned. It is preferable to keep it. Since the processing is performed before the wiring layer 18 and the conductive terminals 21 are formed on the back surface of the semiconductor substrate 1, special protection of the back surface is unnecessary, and the manufacturing process is simplified. In addition, since the semiconductor device can be stacked at the same time as the semiconductor device is completed, workability and efficiency are good. Furthermore, when the through electrode 17 reaching the pad electrode 3 is formed, the electrode connection layer 30 also functions as a reinforcing member from the surface side of the semiconductor substrate 1 so that the pad electrode 3 is formed when the through electrode 17 is formed. There is also an advantage that problems such as omission, tearing, and bending can be prevented.

  Specifically, for example, the electrode connection layer 30 may be formed by a lift-off method or a plating method in which a nickel (Ni) layer and a gold (Au) layer are sequentially sputtered on the pad electrode 3 and then the resist layer is removed. it can. The material of the electrode connection layer 30 can be changed as appropriate according to the material of the conductive terminal 21. Therefore, in addition to nickel and gold layers, titanium (Ti) layer, tungsten (W) layer, copper (Cu) layer, tin (Sn) layer, vanadium (V) layer, nickel vanadium (NiV) layer, molybdenum (Mo) May be composed of a layer, a tantalum (Ta) layer, or the like, and the material is particularly limited as long as it has a function of protecting the pad electrode 3 through the electrical connection between the pad electrode 3 and the conductive terminal 21. Instead, it may be a single layer or a laminate thereof. Examples of the laminated structure are nickel layer / gold layer, titanium layer / nickel layer / copper layer, titanium layer / nickel layer / gold layer, titanium layer / nickel vanadium layer / copper layer, and the like.

  In the above embodiment, the BGA (Ball Grid Array) type semiconductor device having the ball-shaped conductive terminal 21 has been described. However, the present invention is an LGA (Land Grid Array) type having no ball-shaped conductive terminal. The present invention may also be applied to other CSP type and flip chip type semiconductor devices.

  Moreover, although the so-called through-electrode type semiconductor device has been described in the above embodiment, it goes without saying that the present invention is not limited to the above embodiment and can be changed without departing from the gist thereof. .

  For example, in the above embodiment, the support is attached to the surface side (element surface side) of the semiconductor substrate 1, but the support 6 is attached to the other surface side (non-element surface side) as shown in FIG. It is also possible to manufacture a desired semiconductor device by attaching. In this semiconductor device, a pad electrode 3, a wiring layer 18, a conductive terminal 21 and the like are formed on the front surface side (element surface side) of the semiconductor substrate 1. When incorporating this semiconductor device into an electronic device, the conductive terminal 21 is electrically connected to an external circuit by being mounted on a wiring pattern on a circuit board. In addition, after the support 6 is peeled and removed, an insulating film 31 (for example, a silicon oxide film formed by a CVD method) at a position corresponding to the through electrode 17 on the back surface of the semiconductor substrate 1 is opened. It is also possible to stack semiconductor devices by connecting conductive terminals of other semiconductor devices to the openings. In FIG. 16, the same reference numerals are given to the same components as those already described, and the description thereof is omitted. Thus, the support may be attached to any surface of the semiconductor substrate. The present invention can be widely applied to a method of manufacturing a semiconductor device using a support.

It is sectional drawing explaining the manufacturing method of the semiconductor device which concerns on embodiment of this invention. It is sectional drawing explaining the manufacturing method of the semiconductor device which concerns on embodiment of this invention. It is sectional drawing explaining the manufacturing method of the semiconductor device which concerns on embodiment of this invention. It is sectional drawing explaining the manufacturing method of the semiconductor device which concerns on embodiment of this invention. It is sectional drawing explaining the manufacturing method of the semiconductor device which concerns on embodiment of this invention. It is sectional drawing explaining the manufacturing method of the semiconductor device which concerns on embodiment of this invention. It is sectional drawing explaining the manufacturing method of the semiconductor device which concerns on embodiment of this invention. It is sectional drawing explaining the manufacturing method of the semiconductor device which concerns on embodiment of this invention. It is sectional drawing explaining the manufacturing method of the semiconductor device which concerns on embodiment of this invention. It is sectional drawing explaining the manufacturing method of the semiconductor device which concerns on embodiment of this invention. It is sectional drawing explaining the manufacturing method and support tape of the semiconductor device which concern on embodiment of this invention. It is a top view explaining the manufacturing method and support tape of the semiconductor device which concern on embodiment of this invention. It is sectional drawing explaining the manufacturing method and support tape of the semiconductor device which concern on embodiment of this invention. It is sectional drawing explaining the manufacturing method of the semiconductor device which concerns on embodiment of this invention. It is sectional drawing explaining the manufacturing method of the semiconductor device which concerns on embodiment of this invention. It is sectional drawing explaining the manufacturing method of the semiconductor device which concerns on other embodiment of this invention. It is sectional drawing explaining the manufacturing method of the conventional semiconductor device. It is sectional drawing explaining the manufacturing method of the conventional semiconductor device.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 2 1st insulating film 3 Pad electrode
4 Passivation film 5 Adhesive layer 6 Support 7 Resist layer 8 Via hole 9 Second insulating film 10 Resist layer 15 Barrier layer 16 Seed layer 17 Through electrode 18 Wiring layer 19 Resist layer
DESCRIPTION OF SYMBOLS 20 Protective layer 21 Conductive terminal 22 Opening 22a 1st opening 22b 2nd opening 23 Resist layer 24 Solvent supply hole 25 Support tape 26 Solvent 30 Electrode connection layer 31 Insulating film 100 Semiconductor substrate 101 Pad electrode 102 1st 1 insulating film 103 passivation film 104 glass substrate 105 adhesive layer 106 through hole 107 via hole 108 second insulating film 109 barrier layer 110 seed layer 111 through electrode 112 wiring layer 113 protective layer 114 conductive terminal DL dicing line

Claims (7)

Attaching a first support to the first main surface of the semiconductor substrate having the first main surface and the second main surface via an adhesive layer;
Removing a part of the semiconductor substrate to form an opening exposing the adhesive layer from the second main surface of the semiconductor substrate;
After forming the opening, a step of attaching a second support capable of allowing the dissolution agent of the adhesive layer to pass over the second main surface of the semiconductor substrate;
A step of supplying the dissolution agent to the adhesive layer through the second support and the opening, and peeling the first support from the semiconductor substrate. Production method. The method of manufacturing a semiconductor device according to claim 1, wherein a dissolving agent supply hole is formed in the second support. The method for manufacturing a semiconductor device according to claim 1, further comprising a step of grinding a second main surface of the semiconductor substrate after the step of attaching the first support. 4. The method of manufacturing a semiconductor device according to claim 1, wherein a path for supplying the dissolving agent is not formed in the first support. 5. The method of manufacturing a semiconductor device according to claim 1, wherein the first support is a rigid substrate. Before peeling off the semiconductor substrate and the support attached to the first main surface of the semiconductor substrate via an adhesive layer, the semiconductor substrate is attached to the second main surface of the semiconductor substrate, and the support is peeled off. A support tape for fixing individual semiconductor chips after being passed, wherein the dissolving agent of the adhesive layer can pass from the front surface to the back surface. The support tape according to claim 6, wherein a dissolving agent supply hole penetrating from the front surface to the back surface is provided.

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